Field of the Invention The invention pertains to methods and apparatus for image display.

Background A variety of projection displays and so-called flat panel displays have been developed based on liquid crystal display (LCD) panels. Image information is generally provided to these panels by applying appropriate voltages to a series of row and column electrodes on the LCD panel. The intersections of the row and column electrodes define picture elements (pixels) having optical properties that depend on voltages applied to the row and column electrodes. Some LCD panels also include an array of thin Him transistors (TFTs), and one or more TFTs can be associated with each pixel to permit the voltages applied to each pixel to be controlled more independently of the voltages applied to other pixels.

Some displays based on TFT LCD panels are provided with shading correction circuitry that compensates for certain LCD panel non-uniformities or deficiencies in other display system components such as the display optical system.

Typical non-uniformities result from LCD cell-gap variations and imperfections in the optical projection system. Non-uniformities can be particularly noticeable when projecting shades of grey because slight imbalances in projected colors produce greys that appear colored or tinted. In many cases, the appearance of projected pixels varies gradually from region to region on the LCD. Because of the gradual change in appearance, display quality can be improved by measuring the projected optical transfer function of LCD panels at selected points, and, based on these measurements, determining correction values for corresponding regions of the LCD

panels. These correction values can be included in LCD panel drive electronics to correct or compensate for non-uniformities.

Special-purpose integrated circuits can be used to provide such display correction, and correction values can be stored in a non-volatile memory in the display system. In one prior art projector, a SONY CXD3503R application-specific integrated circuit (ASIC) is provided for shading correction. This SONY ASIC uses correction values that are stored in an internal correction table memory for a matrix of 16 horizontal by 13 vertical points for each of the three LCD panels used to produce color images. The ASIC includes internal logic that interpolates vertically between these points to determine correction values and produces three analog outputs (one per LCD panel) that can be connected to brightness inputs (also known as amplifier bias inputs) of a display processing circuit such as a SONY CXA211 IE LCD display processor. These analog outputs provide analog voltages that vary as the display is scanned based on the stored correction values. Voltages applied to amplifier bias inputs of the display processor cause variable offsets to be added to the analog video input values. For example, adding a positive offset causes an associated pixel to appear slightly whiter. Similarly, adding a negative offset causes a displayed pixel to appear slightly blacker and reduces the brightness of full white.

While such systems permit improved display appearance, they also exhibit numerous deficiencies. For example, the correction values associated with pixels in a single row are constant over a zone that is typically 50 or more pixels wide and then change abruptly for pixels in the next zone in the same row. While analog filtering can be applied to smooth transitions at zone edges, visible discontinuities such as brightness changes or color changes between adjacent horizontal zones remain. In addition, such prior art systems apply only a positive or negative offset to image data values, corresponding to adding or subtracting a fixed amount of light to the associated pixels. Unfortunately, the real sources of the display variations that make correction necessary are generally not well corrected in this manner.

Even more sophisticated zone correction systems using two-dimensional real-time interpolation can exhibit contouring artifacts. These artifacts appear as lines that separate areas in which correction values differ by one or more grey levels and have an appearance similar to weather map isobars. Although the differences

are slight (perhaps only one grey level, or a 1 LSB step in the image data), the regular nature and sharp definition of the contours make them apparent.

In many images, visible contours are slight, and there is no additional resolution available to blend the contours into the image. One approach to digital quantization problems is to inject noise or dither the data. Such approaches can produce results similar to those obtained by increasing the number of available bits.

However, adding noise to image data can degrade image quality, and the generation of random numbers in digital logic is difficult.

Accordingly, improved display methods and apparatus are needed.

Summary Display correction systems comprise an offset interleaver configured to provide at least a first offset and a second offset. A counter is configured to identify a first offset pixel location and a second offset pixel location based on the first offset and the second offset, and a processor is configured to establish a first correction value associated with the first offset pixel location and a second correction value associated with the second offset pixel location. In additional examples, an image combiner is configured to combine a first pixel value associated with a selected display pixel with the first correction value and to combine a second pixel value associated with the selected display pixel with the second correction value. In further representative examples, the first offset and the second offset are associated with different locations in a column of pixels, a row of pixels, or in rows and columns of pixels. In other examples, the first offset and the second offset are equal and opposite.

Display processors comprise a correction processor configured to provide correction values associated with a display. An offset interleaver is configured to alternatingly establish at least a first offset and a second offset, and a correction value processor is configured to provide correction values associated with the first offset and the second offset. A video controller is configured to combine the correction value associated with the first offset to a first pixel value of a selected pixel and to combine the correction value associated with the second offset to a second pixel value of the selected pixel. In additional examples, the offset

interleaver is configured to provide the first offset and the second offset for at least a plurality of rows of pixels and the video controller is configured to combine correction values associated with the first offset to first set of pixel values associated with a row of pixels and to combine correction values associated with the second offset to a second set of pixel values of the row of pixels.

Image processing methods comprise obtaining a pixel value for at least one display pixel and establishing at least one correction value associated with a pixel offset from the display pixel. The pixel value and the correction value are combined. In additional examples, at least a first pixel value and a second pixel value are obtained for the at least one display pixel. A first correction value and a second correction value associated with at least a first pixel location and a second pixel location that are offset from the display pixel are established. The first correction value is combined with the first pixel value and the second correction value is combined with the second pixel value. In other examples, the combination of the first correction value and the first pixel value, and the combination of the second correction value and the second pixel value are displayed. In additional examples, the first pixel location and the second pixel are offset from the at least one display pixel both vertically and horizontally.

Display systems comprise a video driver configured to receive a video signal and produce an image signal based on a combination of image data from the video signal and interleaved correction data associated with at least one correction data offset. A liquid crystal display is configured to receive the image signal and provide a displayed image. In representative examples, a memory is configured to store correction parameters and an interpolator is configured to produce correction values based on the stored parameters. In other examples, the correction parameters are associated with a plurality of display zones. In additional examples, the interleaver is configured to produce interleaved correction data associated with a row offset and a column offset. In other examples, the correction data is associated with zone correction of the liquid crystal display.

Image correction controllers comprise a synch detector configured to detect a vertical synch signal and a horizontal synch signal and indicate an image top and an image side, respectively. A memory is configured to store at least a first pixel offset

and a second pixel offset and a counter is configured to detect a first pixel associated with the first offset and a second pixel associated with the second offset. A processor is configured to produce a first correction value associated with the first offset pixel and a second correction value associated with the second offset pixel. A video output is configured to alternatingly apply the first correction value and the second correction value to an image value associated with a pixel having no offset.

In representative examples, the processor produces the first and second correction values based on correction zone data stored in a memory.

These and other features are described below with reference to the accompanying drawings.

Brief Description of the Drawings FIG. 1 is a schematic diagram illustrating a division of a display region into zones associated with correction values.

FIG. 2 is a block diagram illustrating a method of determining display correction values.

FIGS. 3A-3C illustrate a portion of a display to which correction values are applied without dithering (FIG. 3A) and to which correction values are applied with dithering (FIGS. 3B-3C).

FIG. 4 is a block diagram of a representative system configured to apply display correction values and provide combined display data and image data to a display.

Detailed Description While visible contours in a displayed image can be introduced as a result of various types of display correction, example embodiments of display methods and systems are described below with referenced to zone-based corrections. Such methods and systems can be applied in association with other types of correction values such as, for example, row corrections, column corrections, or individual pixel corrections. For convenience, logical values associated with logical"TRUE"or "FALSE"are referred to as"EVEN"or"ODD,"or"1"or"0,"respectively. In some examples, offset values alternate between positive and negative values having

the same magnitude. In some examples, a selected offset can be used in two or more successive frames, and a different offset used. Offset values can also be interleaved in other repetitive patterns.

In some examples, a coordinate system used to define correction points, correction zones, or correction values is dithered. This dither moves the grid of correction zones a few pixels, vertically, horizontally, or both, at the beginning of each frame time in a repetitive pattern. Such methods blur contour lines, but, in some cases, can produce visible flicker in the areas in which correction is applied.

The repetitive pattern effectively reduces the refresh rate of the display.

With reference to FIG. 1, an image area 100 is divided into zones such as representative zones 102,105 based on a zone correction coordinate system 103.

The zones are typically associated with a group of pixels identified by a zone height and a zone width. The zones can be conveniently chosen to have a contant height and width, but in other examples, zone height and width can be varied from zone-to- zone. For example, in an SVGA display containing about 480, 000 pixels, the image area 100 may be divided to be 16 zones wide by 12 zones high so that the zones are 50 pixels by 50 pixels. Different divisions of the image area 100 into rectangular, square, or other zone shapes can also be used.

Application of correction values based on zones is based on counting pixel columns and rows after detecting vertical and horizontal synch pulses. An end of a vertical synch pulse is detected indicating a frame beginning, and a selected number of pixel rows are counted until an image top is reached. After identifying the image top, a next horizontal synch pulse is detected indicating a beginning of a row. A predetermined number of pixels (pixel columns) is counted until a left edge of the image is reached. The correction zones are then mapped onto the image based on the image top and the left edge. Correction values are determined using the zone correction data and applied to the image data. This mapping of correction zones is repeated for additional frames.

The mapping of correction zones to the image permits correction values to be applied. Various methods may be used to calculate correction values for the pixels in each correction zone 105. In one example, initial values for corner pixels in each zone are used to interpolate correction values for the remaining pixels in the zone.

Typically, no two pixels in a zone have the same correction values. For example, with reference to FIG. 1B, a circular image area 150 includes regions 152-154 associated with correction values-1,-2,-3, wherein a correction value difference of 1 corresponds to a minimum correction value difference. Such step-wise changes in correction values produce visible differences between the regions 152-154.

Typically, such an image area appears to include contour lines at boundaries of the regions 152-154 and other adjacent regions having different correction values.

Such image deficiencies can be reduced, compensated, or eliminated using a representative method illustrated in FIG. 2. In step 202, a frame counter FRAME is assigned a value of"EVEN"and a beginning of a frame is detected in a step 204, typically by detecting a vertical synch pulse. In a step 206, a vertical offset (VO) is obtained from a memory 208 that is configured to store one or more values of VO.

In the example of FIG. 2, the memory stores a first vertical offset VOl and a second vertical offset V02, but in other examples fewer or additional values can be stored.

Rows are then counted in a step 210 until a number of rows associated with the value VO has been detected, and an image top is located.

With the image top identified, a row counter ROW is assigned a value "EVEN"in a step 212, and a row start is detected in a step 214, typically based on a horizontal synch pulse. A horizontal offset value (HO) is retrieved from memory 220 in a step 218. Pixels are counted to the value HO to identify an image left edge ("image left") in a step 222. Image correction values for remaining pixels in the current row are determined in a step 224. The correction values can be retrieved from a memory 226 or determined based on stored values, such as values associated with the correction zones of FIG. 1. Upon completion of the selected row, a determination that the current frame includes additional rows is made in a step 228.

If more rows are available in the frame, then a row counter is assigned a value ROW XOR FRAME in a step 216, and processing of a next row begins again in the step 214. If the frame is complete and no additional rows are available, the frame counter FRAME is assigned a complementary value-FRAME in a step 230, and processing begins in the step 204.

In the method 200, zone correction values are interlaced. Frames and rows are considered to be either even-numbered or odd-numbered. Even and odd frames

can be assigned different vertical offsets (VOs), and rows can be assigned different horizontal offsets (HOs) based on an XOR function of the frame number FRAME and the row number ROW, i. e. , FRAME XOR ROW. Two equal magnitude horizontal offsets (HO1 and HO2) are typically used. For example, HOI =-3 pixels, and HO2 = +3 pixels. The following Table shows representative vertical and horizontal offsets associated with a first row and a second row of a first through a fourth frame. For convenience, the first and second rows and the first through fourth frames are identified as rows 1-2 and frames 1-4, respectively. Horizontal offsets are functions of FRAME and ROW, while vertical offsets are functions FRAME only. In this example, VOz = 0, V02 = +1, HO1 =-3, and H02 = +3. Frame Row HO VO No. No. FRAME ROW (pixels) (pixels) 1 1 0 0 -3 0 1 2 0 1 +3 0 2 1 1 0 +3 1 2 2 1 1-3 1 3 1 0 0-3 0 3 2 0 1 +3 0 4 1 1 0 +3 1 4 2 1 1 -3 1 Representative horizontal and vertical offsets for two rows in tour sequential frames.

FIGS. 3A-3C show an example of correction values determined based on alternating offsets. In the example of FIGS. 3A-3C, vertical offset values are not included but typically interlaced horizontal offsets are combined with vertical offsets. FIG. 3A shows a display area 310 that includes an array of display pixels to which correction values can be applied. Unshaded pixels, such as a representative pixel 312, represent pixels to which a correction value of"0"is applied. Shaded pixels, such as a representative pixel 314, represent pixels to which a correction value of"-1"is applied. A jagged boundary between pixels associated with"0"and "1"correction values is apparent, and, for reference, a smooth contour 316 is shown along the jagged boundary. For convenience, application of correction values is illustrated using rows 320,322, 324.

FIGS. 3B-3C show effects of applying correction values based on dithered offsets to the display area 310 of FIG. 3A. FIG. 3B illustrates application of

correction values to an even-numbered frame. Horizontal offsets for the rows are determined as outlined above. For the representative row 320, an associated horizontal offset is-3 pixels, and correction values for the row 320 are shifted left by three pixels. As shown in FIG. 3B, shading in the row 320 is left-shifted by 3 pixels with respect to the shading shown in FIG. 3A. For the row 322, an associated horizontal offset is +3 pixels, and correction values for the row 322 are shifted right by three pixels. As shown in FIG. 3B, shading in the row 322 is right-shifted by 3 pixels with respect to the shading of the row 322 shown in FIG. 3A. Correction of remaining rows is similar, with horizontal offsets alternating between-3 pixels and +3 pixels.

Correction of an odd-numbered frame is illustrated in FIG. 3C. Horizontal offsets are applied in a reverse order with respect to even-numbered frames. For example, an offset of +3 pixels is applied to the row 320 and an offset of-3 pixels is applied to the row 322. The application of correction values associated with these offsets is evident as a 3-pixel right-shift and a 3-pixel left-shift. Correction values can be applied to the remaining rows in the same manner.

Application of interlaced, dithered offsets produces a display region around the grey-level contour line 316 that has, in this example, an average grey level correction value between 0 and-1, or about-0.5. Thus, offset dithering produces an increase in apparent zone correction resolution to correction values that are less than a least significant bit (LSB) of a display system. Because the corrections are applied in closely spaced rows, the corrections appear blended to a typical display user, and flicker is not apparent A representative system configured to apply such display correction values is illustrated in FIG. 4. A video receiver 402 is configured to obtain input image data, typically as a video signal. A display processor 404 buffers the video signal and aligns the video image with a first row and column of a display. Typically the display processor includes offsets that are set so that the image data is applied to the appropriate rows and columns of pixels. A sync extractor 406 obtains horizontal and vertical sync pulses from the video input and a counter 408 is configured to count rows and/or columns and compare count values with offset values obtained from an offset interlacer 410. A correction processor provides display correction

values after the counter determines that a selected display row and/or column has been reached. A video combiner typically receives display data and correction data, and delivers the combined image/correction values to a display.

In the examples described above, application of correction values is based on alternating, interlaced, or other varied offsets applied to a coordinate system used to determine correction values. Image data can continue to be displayed and the correction values dithered.

It will be apparent to one skilled in the art that the example methods and apparatus can be modified in arrangement and detail. For example, video processing hardware can be implemented in, for example, an FPGA, discrete logic, an ASIC, a DSP, or other hardware. Alternatively, a general purpose or other processor can be configured to provide correction values using computer-executable instructions stored on a floppy disk, RAM or other memory. We claim all that is encompassed by the appended claims.