ANTI-FUSE STORAGE CIRCUIT

WIPO Patent Application WO/2023/279542

A1

Provided in the embodiments of the present disclosure is an anti-fuse storage circuit, comprising: a storage array, which comprises a plurality of anti-fuse storage units; bit lines, which are connected to the anti-fuse storage units that are arranged in the extension direction of the bit lines, wherein the anti-fuse storage units are electrically connected to the bit lines by means of first switch tubes; word lines, which are connected to the first switch tubes that are arranged in the extension direction of the word lines; second switch tubes, which are used to make the bit lines connected to a transmission wire; a reading module, a first input end of which is connected to the transmission wire, a second input end of which is used to receive a reference voltage, and a sampling input end of which is used to receive a sampling signal; and a signal generation module, which is used to generate the sampling signal according to a pre-charging voltage and a pre-charging signal, wherein the pre-charging signal is used to indicate that the transmission wire is pre-charged to the pre-charging voltage, and a delay duration between the sampling signal and the pre-charging signal is positively correlated to the magnitude of the pre-charging voltage, so as to ensure that when the pre-charging voltage is relatively large, the anti-fuse storage units have enough time to discharge current, thereby ensuring the accuracy of readout data.

JI RUMIN (CN)

PCT/CN2021/120303

January 12, 2023

September 24, 2021

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CHANGXIN MEMORY TECH INC (CN)

G11C17/16; G11C7/12; G11C8/08

US20090027973A1	2009-01-29
CN112582013A	2021-03-30
CN101145575A	2008-03-19

CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)

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