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Title:
ANTI-FUSE UNIT STRUCTURE, ANTI-FUSE ARRAY AND OPERATION METHOD THEREFOR, AND MEMORY
Document Type and Number:
WIPO Patent Application WO/2024/007360
Kind Code:
A1
Abstract:
Disclosed in the embodiments of the present disclosure are an anti-fuse unit structure, an anti-fuse array and an operation method therefor, and a memory. The anti-fuse unit structure comprises: a first anti-fuse transistor, which has a first end and a second end; a first selection transistor, which has a first end and a second end, the first end of the first selection transistor being electrically connected to the second end of the first anti-fuse transistor; and an enable signal line, which is electrically connected to the first end of the first anti-fuse transistor and used for programming the first anti-fuse transistor.

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Inventors:
HOU CHUANGMING (CN)
Application Number:
PCT/CN2022/105661
Publication Date:
January 11, 2024
Filing Date:
July 14, 2022
Export Citation:
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Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C17/16
Foreign References:
CN107785053A2018-03-09
CN113496988A2021-10-12
CN101595723A2009-12-02
US20160141049A12016-05-19
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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