Measuring a Phase Noise Description

Embodiments of the invention relate to an apparatus comprising a recursive delayer for measuring a phase noise and a method for measuring a phase noise.

Phase noise of signal sources is a severe cause of performance degradation in communication systems. Thus, in the production phase of radio frequency (RF) chips that are configured to handle electrical, optical and/or electromagnetic signals in the radio frequency range (3 KHz up to 300 THz), it is very important to accurately measure the phase noise of the device under test (DUT) , meanwhile keeping the cost of test (COT) as low as possible. Delay line discriminator techniques are well known for phase noise measurement and offer the advantage of avoiding external sources with good phase noise properties, for example a local oscillator having a substantially lower phase noise than the device under test. Especially for measurement of phase noise of highest performance devices under test a local oscillator is expected to exhibit less than state of the art phase noise. Delay line discriminator techniques are a phase noise measurement method which does not require a local oscillator. The radio frequency signal to be measured is split in two paths: One path is passed through a tunable phase shifter, and the second path is passed through a delay line. The signal at the output of the phase shifter is then mixed with the signal at the output of the delay line. Delay line discriminators provide a relatively easy and low cost solution for phase noise measurement . - -

A description of a conventional delay line discriminator can be found in the Microwave Journal of December 1983, page 103 ff . : "Theory and Design of the Delay Line Discriminator for Phase Noise Measurements" by Christopher Schiebold.

However, delay line discriminators are known to suffer severe sensitivity loss for close-in phase noise measurements . showing a poor performance, due to the non- zero correlation between the phase noise waveform and its delayed version. The poor performance for close-in phase measurements is due to the strong attenuation that low frequency components undergo when passing through the delay line discriminator. This attenuation can be so strong that the signal falls below the noise floor, making the phase noise measurement virtually impossible. The correlation between the phase noise waveform and its delayed version can be decreased and thus the sensitivity improved by using longer delay lines. However, long analog delay lines are difficult to build.

Phase noise measurements require a high precision measurement of the phase noise. This can be achieved by using long delay lines improving the measurement sensitivity without adding further complexity to the delay line to minimize the cost of the measurements.

Embodiments of the invention provide an apparatus for measuring a phase noise of a test signal, comprising a recursive delayer. Embodiments of the invention avoid an adjustable phase shifter which is complex to handle in discriminator-based phase noise measurements. Embodiments of the invention provide a cost-efficient device and method for phase noise measurements. Complex calibrations are not required in some cases as no adjustable phase shifter is needed such that an easy automation of a test process becomes possible. Embodiments of the invention do not require external sources with high precision phase noise - -

properties such as a local oscillator providing a reference phase. Embodiments of the invention increase the phase noise measurement sensitivity by means of a novel recursive delay line architecture, which exploits a feedback path to enhance the measurement sensitivity. Some embodiments of the invention show an outstanding gain in measurement sensitivity of about 40 dB over conventional delay line discriminators .

Embodiments of the invention provide an apparatus for measuring a phase noise of a test signal, the apparatus comprising a recursive delayer, a combiner and a phase noise determinator . The recursive delayer is configured to provide a delayed signal on the basis of the test signal. The combiner is configured to combine a first signal, which first signal is based on the test signal or identical to the test signal, with a second signal, which second signal is based on the delayed signal or identical to the delayed signal, to obtain a combiner output signal. The phase noise determinator is configured to provide a phase noise information in dependence on the combiner output signal.

Some embodiments of the invention comprise a recursive digital delayer configured to provide a delayed digital signal on the basis of the test signal. Other embodiments of the invention comprise an adjustable recursive delayer. Other embodiments of the invention provide an apparatus which is adapted to receive an analog signal, a digital signal or a square-wave signal.

Embodiments of the invention comprise an analog mixer configured to combine a first analog signal, which first analog signal is based on the test signal, with a second analog signal, which second analog signal is based on the delayed signal, to obtain an analog mixer output signal. Other embodiments of the invention comprise an analog mixer configured to combine a first analog signal, which first analog signal is based on the test signal, with a second _ _ digital signal, which second digital signal is based on the delayed signal, to obtain an analog mixer output signal. Other embodiments of the invention comprise a digital mixer configured to combine a first digital signal, which first digital signal is based on the test signal, with a second digital signal, which second digital signal is based on the delayed signal, to obtain a digital mixer output signal. Embodiments of the invention comprise an analog filter to filter the digital mixer output signal.

With reference to the accompanying figures la to 19, embodiments of an apparatus comprising a recursive delayer for measuring a phase noise of a test signal and a method for measuring a phase noise of a test signal will be described.

Fig. la shows a block diagram of a delay line discriminator, according to a conventional implementation;

Fig. lb shows a block diagram of an analog delay line discriminator, according to a conventional implementation; Fig. lc shows equivalent block diagrams with impulse and frequency responses of the analog delay line discriminator as depicted in Fig. lb, according to a conventional implementation; Fig. 2a shows a block diagram of an apparatus comprising a recursive delayer, according to an embodiment of the invention;

Fig. 2b shows a block diagram of another apparatus comprising a recursive delayer, according to an embodiment of the invention; Fig. 3a shows an equivalent block diagram of the apparatus as depicted in Fig. 2b with respect to the phase noise transmission, according to an embodiment of the invention;

Fig. 3b shows an equivalent block diagram of the apparatus as depicted in Fig. 3a illustrating the frequency response, according to an embodiment of the invention;

Fig. 4 shows the block diagram as depicted in Fig. 2b illustrating the transmission of a cosine-shaped test signal modulated in phase according to an embodiment of the invention;

Fig. 5 shows a block diagram of an apparatus comprising a recursive delayer, according to another embodiment of the invention; Fig. 6 shows a block diagram of an apparatus comprising a recursive delayer, according to another embodiment of the invention;

Fig. 7 shows a block diagram of an apparatus comprising a recursive digital delayer, according to an embodiment of the invention;

Fig. 8 shows a block diagram of an apparatus comprising a recursive digital delayer, according to another embodiment of the invention;

Fig. 9 shows a block diagram of an apparatus comprising a recursive digital delayer, according to another embodiment of the invention;

Fig. 10 shows a block diagram of an apparatus comprising a recursive digital delayer according to another embodiment of the invention; - -

Fig. 11 shows a block diagram of an apparatus comprising an adjustable recursive delayer, according to an embodiment of the invention;

Fig. 12 shows a block diagram of an apparatus comprising a recursive delayer, according to another embodiment of the invention; Fig. 13 shows a block diagram of an apparatus comprising a recursive delayer, according to another embodiment of the invention;

Fig. 14 shows an equivalent block diagram of the apparatus as depicted in Fig. 13, according to an embodiment of the invention;

Fig. 15 shows a block diagram of an apparatus comprising a recursive delayer, according to another embodiment of the invention;

Fig. 16a shows a diagram illustrating a power transmission of the apparatus as depicted in Fig. 14 for a carrier signal with a multi-tone modulation, applied as input signal to the apparatus, the multi-tone modulation having a power of -56 dBm;

Fig. 16b shows a diagram illustrating the power transmission of the apparatus as depicted in Fig. 14 for the input signal as depicted in

Fig. 16a, the multi-tone modulation having a power of -76 dBm;

Fig. 17a shows a diagram illustrating a power transmission of the conventional delay line discriminator as depicted in Fig. lb for the input signal as depicted in Fig. 16a, the multi-tone modulation having a power of -56 dBm; - -

Fig. 17b shows a diagram illustrating the power transmission of the conventional delay line discriminator as depicted in Fig. lb for the input signal as depicted in Fig. 16a, the multi-tone modulation having a power of -76 dBm;

Fig. 18a shows a diagram illustrating the signal-to-noise ratio of the apparatus as depicted in Fig. 14;

Fig. 18b shows a diagram illustrating the signal-to-noise ratio of the conventional delay line discriminator as depicted in Fig. lb; and Fig. 19 shows a flow chart for a method for measuring a phase noise of a test signal, according to an embodiment of the invention.

Fig. la shows a block diagram of a delay line discriminator according to a conventional implementation. A delay line discriminator 100 comprises a delay line 101, a phase shifter 102, a mixer 103 and a low-pass filter 104. The delay line discriminator 100 is adapted to measure the phase noise of a test signal 110, which may be provided by a source under test 105. The test signal 110 is input to the delay line 101 and to the phase shifter 102. The delay line 101 provides a delayed test signal 111, which is a delayed version of the test signal 110. The phase shifter 102 provides an output signal, which is a phase shifted test signal 112. The delayed test signal 111 and the phase shifted test signal 112 are input to the mixer 103, which provides a mixed signal 113, the mixed signal 113 being input to the low-pass filter 104. The low-pass filter 104 provides a low-pass filter output signal u(t), which may be analyzed by further units inside the delay line discriminator 100 or outside of the delay line discriminator 100. - -

The test signal 110 may have a cosine-shaped signal form with an angular frequency ω ₀ and a time-depending phase <|>(t), for example, having the form cos (root + <|>(t)). The delayed test signal 111 is a delayed version of the test signal 110, e.g. having the form cos(ro ₀ (t-T _d ) + <|>(t-T _d )). The phase shifted test signal 112 is a phase shifted version of the test signal 110, for example, with the phase shift φ having the signal form cos (root + φ(ί) + φ) . The delayed test signal 111 and the phase shifted test signal 112 have a relation with respect to the delay time T _d of the delay line 101 and the phase φ of the phase shifter 102, which is expressed by ro ₀ T _d + φ = n/2. This condition requires that the inputs to the mixer 103, that is the delayed test signal 111 and the phase shifted test signal 112, are in phase quadrature. The mixer 103 provides a mixed signal 113, which is input to the low-pass filter 104, the low-pass filter 104 providing a low-pass filtered output signal u(t).

The low-pass filtered output signal u(t) may have the signal form u(t) = φ(ί) - <|>(t-T _d ). A power spectral density of the low-pass filtered output signal u(t) expresses the power of the low-pass filtered output signal by P _u (f) = |H (f) | ² Ρψ (f) , wherein Ρψ(ί) is the power spectral density of the phase noise <|>(t) and |H(f)| ² is the power transmission factor for transmission of the power spectral density of the phase noise to the power spectral density of the low-pass filtered output signal u(t). / describes, for example, a frequency offset from the carrier frequency α>ο· The transfer function from the phase noise <j>(t) to the low- pass filtered output signal u(t) corresponds to H (/) = 1 -

Due to the property of the delayed test signal 111 and the phase shifted test signal 112 to be in phase quadrature, mixed cosine and sine terms in the low-pass filtered output signal u(t) are cancelled. The power spectral density of the low-pass filtered output signal u(t) becomes - - independent from the angular frequency (or carrier frequency) Oo of the test signal 110. To provide this phase quadrature property of the delayed test signal 111 and the phase shifted test signal 112, a tunable phase shifter 102 is required. The tunable phase shifter 102 has to be adjusted for each input frequency (or carrier frequency co ₀ ) of the test signal 110, making the calibration process time consuming and not well-indicated for automatic measurements. Due to the statistical correlation between the phase noise <|)(t) and the delayed version of the phase noise <j)(t-T _d ), the delay line discriminator 100 shows a low sensitivity for close-in phase noise measurements. The statistical correlation is dependent on the delay time T _d of the delay line 101 and may be reduced when increasing the delay time T _d . By increasing the delay time T _d the power transmission factor |H(f)| ² is increased resulting in a higher sensitivity of the phase noise measurement. However, increasing the delay time T _d is limited when using analog signals, as long delay lines would be expensive and complex to implement.

Fig. lb shows a block diagram of an analog delay line discriminator according to a conventional implementation. The delay line discriminator 130 comprises a splitter 131, a delay line 132, a phase shifter 133, a mixer 134, a low- pass filter 135 and an analog-to-digital converter 136. The delay line discriminator 130 is configured to receive a radio frequency signal x(t) and is configured to provide a delay line discriminator output signal z(n), which may be further evaluated by a digital signal processor (DSP) 137.

The splitter 131 is adapted to divide the radio frequency signal x(t) into two equal level signals, a first splitter output signal 141 and a second splitter output signal 142. The delay line 132 is adapted to delay the second splitter output signal 142 to provide a delayed second splitter output signal 143. The phase shifter 133 is adapted to phase shift the delayed second splitter output signal 143 to provide a phase shifter output signal w(t). The mixer 134 is adapted to mix the first splitter output signal 141 and the phase shifter output signal w(t) to provide a mixer output signal 144. The low-pass filter 135 is adapted to low-pass filter the mixer output signal 144 to provide the continuous-time delay line discriminator output signal z(t). The analog-to-digital converter 143 is adapted to convert the continuous-time delay line discriminator output signal z(t) to a discrete-time delay line discriminator output signal z (n) , which is the delay line discriminator output signal.

While the direct spectrum measurement and the reference source measurement rely on a clean, low phase noise radio frequency source, the delay line discriminator 130 shown in Fig. lb does not need a dedicated radio frequency source reference. A splitter 131 is used to divide the radio frequency signal x(t) into two equal level signals 141, 142. One signal 141 is applied directly to a mixer 144, while the second signal 142 is routed to a delay line 132. The output signal 143 of the delay line is passed through a phase shifter 133 to obtain a phase shifted signal co(t), and then w(t) is fed into the mixer 134. If the phase shifter 133 is tuned such that a phase shift of 90° is performed, then the low-pass filter output signal z(t) becomes z (t) = V _z (<|>(t)-<j)(t-r) ) , wherein V _z is the signal amplitude, ()>(t) is the phase noise of the radio frequency signal x(t) and <|)(t - τ) is the phase noise of the delayed radio frequency signal x(t - τ) , delayed by the time delay τ. The radio frequency signal x(t) may be expressed as an output of a physical oscillator written as x(t) = V _x (l + a(t))cos(e>ct + 4>(t)), - -

where V _x is the signal amplitude, a(t) represents the amplitude modulation noise, and <j>(t) the phase modulation noise, the latter also referred to as phase noise. The angular deviation (|>(t) may involve both deterministic and random components, however in general only the random fluctuations are of interest. By neglecting the amplitude modulation (AM) noise and for small phase modulations, i.e. |<j>(t)| « 1, we obtain x(t) = V _x (cos (co _c t ) -φ (t) sin (co _c t) ) , where we used the approximations cos(<|>(t)) « 1, and sin(<(>(t) ) * <|>(t) .

Fig. lc shows equivalent block diagrams with impulse and frequency responses of the analog delay line discriminator as depicted in Fig. lb, according to a conventional implementation. The figure shows the impulse response h(t) for transforming the phase noise cp(t) to the continuous time delay line discriminator output signal z(t), which can be represented by two Dirac impulses 5(t) and 6(t-T). Both Dirac impulses have a time distance of T corresponding to the time delay T. Fig. lc further illustrates the squared value of the frequency responses magnitude |H(f)| ² corresponding to the power transmission factor, by which the power of the phase noise P _<p (f) is transferred to the power of the delay line discriminator output signal P _z (f). The power transmission factor can be expressed as

|H(f) I ² = 2 - 2cos (2nfT) , wherein f denotes the frequency of the phase noise cp (t) and T denotes the time delay of the delay line 132. Reasonable values of T are in the order of a few nanoseconds, while reasonable values of f are smaller than 1 MHz in some cases . - -

Fig. 2a shows a block diagram of an apparatus comprising a recursive delayer, according to an embodiment of the invention. The apparatus 200 comprises a recursive delayer 201, a combiner 202 and a phase noise determinator 203. The apparatus 200 is adapted to receive a test signal 210 and to provide phase noise information 211. The recursive delayer 201 is configured to provide a delayed signal 212 on the basis of the test signal 210. The combiner 202 is configured to combine a first signal 213, which first signal 213 is based on the test signal 210 or is identical to the test signal 210, with a second signal 214, which second signal 214 is based on the delayed signal 212 or is identical to the delayed signal 212, to obtain a combiner output signal 215. The phase noise determinator 203 is configured to provide the phase noise information 211 in dependence on the combiner output signal 215.

In this embodiment of the invention the first signal 213 is equal to the test signal 210, and the second signal 214 is equal to the delayed signal 212. The first signal 213 may also be based on the test signal 210, or may be derived from the test signal 210 or may be dependent on the test signal 210. The second signal 214 may also be based on the delayed signal 212, may be derived from the delayed signal 212 or may be dependent on the delayed signal 212. The test signal 210 may be an analog or digital signal of an electric or optical source. The first signal 213 may (for example) be an amplified, attenuated, phase shifted, time shifted, frequency shifted, filtered, equalized, noise affected, digitally sampled or square-wave version of the test signal 210. The second signal 214 may (for example) be an amplified, attenuated, phase-shifted, time shifted, frequency-shifted, filtered, equalized, noise affected, digitally sampled or square-wave version of the delayed signal 212. - -

The recursive delayer 201 is configured to provide the delayed signal 212 on the basis of the test signal 210, such that the delayed signal 212 comprises a superposition of a plurality of time shifted signal components, which signal components are based on the test signal 210, and which signal components are shifted in time with respect to each other. The recursive delayer 201 is adapted to recursively delay a signal based on the test signal 210 or a signal identical to the test signal 210, to provide a recursively delayed signal corresponding to the delayed signal 212. The recursive delayer 201 is configured to provide the delayed signal 212 on the basis of the test signal 210, such that the plurality of time shifted signal components corresponds to a sequence of consecutive time shifted signal components.

The recursive delayer 201 comprises a time delay for delaying the test signal 210 or the signal based on the test signal 210.

For example, the recursive delayer may be configured to recursively delay the test signal, such that the delayed test signal comprises a superposition of a plurality of time-shifted versions of the test signal 210 (or of the signal based on the test signal 210) . In other words, the recursive delayer may comprise a feedback, such that an output signal of a delay line is fed back to the input of the delay line to obtain the recursive delay. Accordingly, the output signal of the delay line comprises a plurality of time-shifted versions of the test signal 210.

For example, if a short portion of the test signal (or of a signal based on the test signal) is considered, the short portion (shorter than the delay time of the delay line) will occur at the output of the delay line, as a component of the delay line output signal, after a certain delay time. If this one-time delayed portion of the test signal 210 (or of the signal based on the test signal 210) is fed - - back to the input of the delay line again, a two-times delayed version of said portion of the test signal 210 (or of the signal based on the test signal 210) will appear at the output of the delay line (as a "component" of the delay line output signal) after a further period of time. Accordingly, different multiple-times delayed versions of the portion of the test signal 210 (or of the signal based on the test signal 210) will appear at the output of the delay line. The different time-delayed versions of the portion of the test signal 210 may for example decay in amplitude over the iterations.

Taking the test signal 210 as a whole, it can be said that different time-shifted versions of the test signal may be superposed at the output of the delay line, wherein portions of the test signal 210 which have been recursively delayed multiple times may be attenuated when compared to portions of the test signal 210 which have been delayed less often (or only once) .

The recursive delayer 201 may effect a plurality of time delays for multiple delaying the test signal 210 (or the signal based on the test signal 210) . The output signal of the recursive delayer may for example be formed using a sequence (or superposition) of signal components which signal components may be time-shifted versions of the test signal. The recursive delayer 201 may be configured to obtain a signal component of the sequence of signal components by time-delaying the test signal 210 (or the signal based on the test signal 210) by the time delay or by a combined time delay, which combined time delay being a combination of the plurality of time delays.

The recursive delayer 201 may be configured to obtain a second signal component of the sequence of signal components, which second signal component is successive to a first signal component of the sequence of signal components, by time delaying the first signal component by - - a first time delay of the plurality of time delays. The recursive delayer 201 may further be configured to obtain a third signal component of the sequence of signal components, which third signal component is successive to the second signal component, by time delaying the second signal component by a second time delay of the plurality of time delays or by time delaying the first signal component by a sum of the first time delay and the second time delay. The first signal component is delayed by the first time delay to obtain the second signal component, the second signal component is delayed by the second time delay to obtain the third signal component. The third signal component may be obtained by delaying the first signal component by the first time delay and by the second time delay. The first time delay and the second time delay may be identical or may be different. However, the recursive delayer 201 may also delay signal components by multiple time delays. A respective signal component may be delayed by a plurality of time delays to obtain the delayed signal 212.

The recursive delayer 201 may for example be configured to effect a plurality of attenuations. The recursive delayer 201 may obtain one of the signal components of the sequence of signal components by attenuating the test signal 210 (or the signal based on the test signal) by one or more of the plurality of attenuations. The signal component of the sequence of signal components may be first attenuated, then time delayed or may be first time-delayed and then attenuated.

The plurality of time shifted signal components (or signal versions) may be added to obtain the delayed signal 212. The first signal 213 and the second signal 214 may be in phase quadrature corresponding to a 90° phase shift or a phase shift of 90° plus a multiple integer value of 180°. The recursive delayer 201 may be configured to provide the - - delayed signal 212 such that the signal components (or time-shifted versions of the test signal 210) of the plurality of signal components (or of the plurality of time-shifted versions of the test signal 210) are in phase with respect to each other, which corresponds to a phase shift of 0° plus an integer multiple of 360°. If the signal components of the plurality of signal components are in phase with respect to each other, each of the signal components of the plurality of signal components may be in phase quadrature to the first signal 213.

Examples for phase quadrature signals are a sine signal and a cosine signal. A multiplication of the sine signal with the cosine signal and a subsequent integration, low-pass filtering or summation of the multiplied signal results in a compensation of both phase-quadrature signals obtaining a compensated signal, which may be zero in an ideal case. The first signal 213 and the second signal 214 may also be periodic (or at least approximately, if phase noise is considered) rectangular signals or periodic square-wave signals being phase shifted by 90° or by 90° plus an integer multiple of 180° with respect to each other, such that a multiplication (or XOR combination) of the first signal 213 with the second signal 214 and a subsequent summation, low-pass filtering or integration results in a compensation, too. The subsequent summation, low-pass filtering or integration may be performed by the phase noise determinator 203. The phase noise determinator 203 may comprise a low-pass filter for low-pass filtering the combiner output signal 215 to obtain the compensated signal .

A phase modulation (or phase noise) of the test signal 210 may result in a phase modulation (or phase noise) of the first signal 213 and the second signal 214. In the presence of a phase noise or phase modulation of the test signal 210 (or by phase modulating the test signal 210) , aA phase modulation (or phase noise) of the first signal 213 and the - - second signal 214 may "pass" the multiplication and subsequent integration such that a power of the phase modulation is detectable by the phase noise determinator 203 providing the phase noise information 211. The phase modulation provides the first signal 213 and the second signal 214 deviating from its phase quadrature. This is for example due to the fact, that the phase modulation (or phase shift) contribution of the first and second signal are brought out of quadrature by different group delays acting on the first signal 213 and on the second signal 214. The deviation from the phase quadrature (or the mixer output signal resulting from this deviation) may be integrated by the subsequent integrator or low-pass filter. A power of the deviation corresponds to the phase noise power or the phase modulation power.

The device comprising the combiner (for example mixer or XOR-combiner) 202 and the phase noise determinator 203 can also be represented by a correlation device performing a correlation of the first signal 213 and the second signal 214. The result of the correlation corresponds to the phase noise information 211 and may represent the phase noise power. The device comprising the combiner 202 and the phase noise determinator 203 may be a cross-correlation device for calculating the cross-correlation between the first signal 213 and the second signal 214.

The apparatus 200 may represent an autocorrelation device calculating the autocorrelation of the test signal 210 and providing the phase noise information 211 as a measure of the phase noise power. The recursive delayer 201 may provide signal components representing time-shifted values of the test signal 210. The combiner 202 may perform a multiplication of the test signal 210 with the delayed test signal 212 comprising the time-shifted versions of the test signal 210. The second signal 214 corresponding to the delayed test signal 212 comprises the sequence of signal components, which may be time-shifted versions of the test - - signal 210. The combiner 202 may provide the combiner output signal 215 such that same signal comprises a superposition of autocorrelation values of the test signal 210. The phase noise determinator 203 may integrate the superposed autocorrelation values of the test signal 210 to provide the phase noise information 211 or the phase noise power. The apparatus 200 may represent an autocorrelation integrator for integrating the autocorrelation values of the test signal 210. By integrating the autocorrelation values of the test signal 210, a measurement sensitivity of the phase noise power may be. increased compared to a conventional delay line delaying the test signal 210 by a single delay. A single delay corresponds to a single signal value of the autocorrelation function of the test signal 210, that is the autocorrelation function of the test signal 210 for the said single delay. Depending on the form of the autocorrelation function of the test signal 210 the sensitivity of the phase noise information 211 may be improved.

The test signal 210 may be a noise signal, for example a white noise or a code sequence transporting the code information by a phase modulation of the test signal 210. The apparatus 200 is configured to detect the phase noise information 211 which is carried within the test signal 210. The apparatus may be a decorrelation receiver for decorrelating the phase modulation information carried within the test signal 210. The test signal 210 may carry a code which may be decoded by the apparatus 200 providing the phase noise information 211 corresponding to the decoded information. The test signal 210 may provide a carrier which is phase and/or amplitude modulated (for example in the form of noise) . The carrier may preferably be a sine or cosine-shaped signal. Alternatively, in some embodiments the carrier may be a noise, a pseudo random noise, a code sequence such as a gold code, an m sequence or may comprise a different signal form. Embodiments of the - - apparatus 200 comprising a recursive delayer 201 are depicted in the subsequent figures.

Fig. 2b shows a block diagram of an apparatus comprising a recursive delayer, according to another embodiment of the invention. The apparatus 200 comprises a recursive delayer 201, a combiner 202 and a phase noise determinator 203 which correspond to the respective devices as depicted in Fig. 2a. The apparatus 200 is adapted to receive a test signal 210 which may be provided by a source under test 220. The apparatus 200 is adapted to provide a phase noise information 211.

The recursive delayer 201 comprises a first delay line 221, a second delay line 222, a first adding device 223, a second adding device 224 and an attenuator 225. The first delay line 221 is adapted to delay the test signal 210 by a first delay time τ to provide a first delayed version 230 of the test signal 210. The second delay line 222 is adapted to delay an attenuated superposition signal 231 by a second delay time δ to provide a second superposition signal 232. The first adding device 223 is adapted to perform an additive superposition of the first delayed version 230 of the test signal 210 and the second superposition signal 232 to provide a first superposition signal 233. The attenuator 225 is adapted to attenuate the first superposition signal 233 to provide the attenuated superposition signal 231. The second adding device 224 is adapted to perform an additive superposition of the first delayed version 230 of the test signal 210 and the second superposition signal 232 to provide the delayed signal 212. In this embodiment the second signal 214 corresponds to the delayed signal 212 and the first signal 213 corresponds to the test signal 210.

The combiner 202 comprises a multiplicative mixer 240 which is adapted to mix the first signal 213 and the second signal 214 by a multiplication to provide the combiner - - output signal 215. The phase noise determinator 203 comprises a low-pass filter 241 which is adapted to low- pass filter the combiner output signal 215 to provide the low-pass filter output signal u(t). The low-pass filter output signal u(t) may represent the phase noise information 211. Alternatively, the phase noise determinator 203 may comprise an optional analog-to-digital converter 242 which is configured to convert the continuous time representation of the low-pass filter output signal u(t) to a discrete time representation of the low- pass filter output signal u(k) which may represent the phase noise information 211.

Fig. 3a shows an equivalent block diagram of the apparatus as depicted in Fig. 2b with respect to the phase noise transmission, according to an embodiment of the invention. The block diagram of the apparatus 200 as depicted in Fig. 2b without the optional analog-to-digital converter 242 represents a block diagram, of an impulse response h(t) providing the low-pass filter output signal u(t) when applied to the phase noise (|>(t). A mathematical description of the impulse response h(t) may be derived by setting the first delay time of the first delay line 221 to τ · T _d , by setting the attenuation of the attenuator 225 to A and by setting the second delay time of the second delay line 222 to δ · T _d . A description of the impulse response h(t) in the frequency domain is depicted in Fig. 3b.

Fig. 3b shows an equivalent block diagram of the apparatus as depicted in Fig. 3a illustrating the frequency response according to an embodiment of the invention. The equivalent block diagram 301 may be characterized (or expressed) by the formula

AT - -

The frequency response H(f) corresponds to the Fourier transform of the impulse response h(t). The frequency response H(f) describes the transformation of the phase noise φ(ί), which is the Fourier transform of <D(t), to the low-pass filter output signal u(f) which is the Fourier transform of u(t) in the frequency domain. For example, the variable f may determine the frequency offset of the phase noise from the carrier in the test signal 210, and the baseband frequency of the low-pass filter output signal u(f), taking into consideration a frequency down-conversion of the phase noise. The squared absolute value |H(f)| ² of the frequency response H(f) describes the power transmission of the power of the phase noise Ρφ(ΐ) represented in the frequency domain to the power of the low-pass filter output signal P _u (f) represented in the frequency domain. The relation is P _u (f) = I (H (f) | ² Ρ _Φ (f) .

For close-in phase noise having a product of f and τ · Ta close to 0 (and also for not-close-in phase noise), a recursive delay provides additional signal components having the additional delays ηδ T _d (with frequency-delay- product f · ηδ · T _d ) which result in a higher sensitivity of the frequency response due to the recursive additions of the second delay time δ · T _d . The sensitivity of the frequency response H(f) is improved. The power of the phase noise Ρψ(ί) may be attenuated or amplified by the power transmission factor |H(f)| ² such that the power of the phase noise Ρψ(ί) is shifted above the noise floor and becomes detectable. The noise power (e.g. the noise power which can be measured using the apparatus 200) will have a higher dynamic range. Measurements have shown that a gain of approximately 40 dB of the recursive delayer with respect to a conventional delayer is possible. In other words, in some cases a noise sensitivity of the apparatus 201 can be improved by 40 dB Using the recursive delayer. Fig. 4 shows the block diagram as depicted in Fig. 2b illustrating the transmission of a cosine-shaped test signal modulated in phase according to an embodiment of the invention. The test signal 210 may be expressed by a cosine-shaped signal cos (coot + <j)(t)), wherein ω ₀ denotes the angular frequency of a carrier and <|>(t) denotes the phase modulation or the phase noise of the carrier. The test signal 110 may alternatively have a rectangular shape, wherein harmonic signal components are filtered by a (low- pass) filter, so that the test signal 110 can affectively be treated as a cosine-shaped signal or as a sine-shaped signal. In general, the test signal 110 may be any at least approximately periodic signal, a carrier wave of which may be represented by a cosine-shaped (or a sine-shaped) signal. Thus, the test signal may even have a triangular shape or any other approximately periodic shape. The first delayed version 230 of the test signal 210 is provided by the first delay line 221 which is adapted to delay the test signal 210 by the first delay time τ. The first delay time τ is adjusted such that the cosine-shaped test signal 210 is converted to a sine-shaped first delayed version 230 of the test signal 210. The first delay time τ is adjusted to delay the test signal 210 by a fourth period of the test signal 210 (or of a fundamental frequency thereof) or by a fourth period plus a multiple number of half periods of the test signal 210 such that the cosine- shaped test signal 210 is converted to a sine-shaped first delayed version 230 of the test signal 210. The first delayed version 230 of the test signal 210 may be expressed as sin(co ₀ t + <|)(t--c)).

The second delay line 222 is adapted to delay the attenuated superposition signal 231 by a time delay of δ providing the second superposition signal 232. The second delay time δ is adjusted such that signal components of the sequence of signal components have a sine-shaped signal form. Both, the attenuated superposition signal 231 and the second superposition signal 232 have sine-shaped signal forms (or are in-phase with the first delayed version 230 of the test signal 210 with respect to a fundamental frequency) . The second delay time δ is adjusted to delay the attenuated superposition signal 231 by a half signal period or multiples of a half signal period such that the attenuated superposition signal 231 having a sine-shaped signal form is transformed in the second superposition signal 232 having a sine-shaped or a reverse sine-shaped signal form. In other words, the second delay time δ may be adjusted such that the second superposition signal 232 is in phase (±10°) with the first delayed version 230 of the test signal 210 or 180° out of phase (±10°) with respect to the first delayed version of the test signal. The second adding device 224 is adapted to perform an additive superposition of the first delayed version 230 of the test signal 210 having a sine-shaped signal form and the second superposition signal 232 having a sine-shaped signal form to provide the second signal 214. The signal form of the second signal 214 can be represented by a superposition of sine-shaped signal forms. The second signal may be expressed as

sin[ _Q t + (ί - f)3 T Α ^η ≤ίη[ω ₀ ί +≠(t- r-nS}

By multiplication of the at least approximately cosine- shaped (phase-noise affected) test signal which corresponds to the first signal 213 with the at least approximately sine-shaped signal components of the sequence (or superposition) of signal components corresponding to the second signal 214, the mixer 240 provides the mixer output signal 215. The mixer output signal 215 is low-pass filtered by the low-pass filter 241 which provides the low- pass filter output signal that may be expressed as

The low-pass filter output signal u(t) depends on the phase noise <|)(t), on the delayed versions of the phase noise <j)(t- τ) or φ(ί-τ-ηδ), respectively, and on the attenuation A of the attenuator 225. n denotes the sequence number of the sequence of signal components which corresponds to a recursion index. The low-pass filter output signal u(t) does not depend on the carrier frequency coo of the carrier (or fundamental) of the test signal 210. The low-pass filter output signal u(t) or an optional discrete-time representation of the low-pass filter output signal u(k) corresponds to the phase noise information 211. Fig. 5 shows a block diagram of an apparatus comprising a recursive delayer according to another embodiment of the invention. The apparatus 500 comprises a recursive delayer 501 configured to provide a delayed signal 512 on the basis of the test signal 210. In this embodiment the recursive delayer 501 is adapted to receive the test signal 210 and to provide the delayed signal 512. The apparatus 500 further comprises a combiner 202 corresponding to the combiner 202 as depicted in Fig. 2b and a phase noise determinator 203 corresponding to the phase noise determinator 203 as depicted in Fig. 2b. The combiner 202 is configured to combine a first signal 513, which is based on the test signal 210, with a second signal 514, which second signal 514 is identical to the delayed signal 512, to obtain a combiner output signal 515. The first signal 513 is a delayed version of the test signal 210, delayed by a first delay time τ. The apparatus 500 comprises a first delay line 521 which is adapted to delay the test signal 210 by the first delay time τ to provide the first signal 513. Thus, the phase noise determinator 503 corresponds to the phase noise determinator 203 as depicted in Fig. 2b. The recursive delayer 501 comprises a first adding device 523, a second adding device 524, an attenuator 525 and a second delay line 522. The first attenuation device 523 is adapted to perform an additive superposition of the test signal 210 and a second superposition signal 532 to provide a first superposition signal 533. The attenuator 525 is adapted to attenuate the first superposition signal 533 by an attenuation A to provide an attenuated superposition signal 531. The second delay line 522 is adapted to delay the attenuated superposition signal 531 by a delay time δ to provide the second superposition signal 532. The second adding device 524 is adapted to perform an additive superposition of the test signal 210 and the second superposition signal 532 to provide the delayed signal 512, which is identical to the second signal 514.

In this embodiment of the invention the test signal 210 has an at least approximately cosine-shaped signal form and may be expressed as cos (a> ₀ t + <|)(t)). The first delay line 521 is adapted to delay the test signal 210 such that the first signal 513 has the signal form sin(co ₀ t + <|>(t-O ) . The first signal 513 (or the carrier thereof) is in phase quadrature with respect to the test signal 210. The first delay time τ is adapted to provide the phase quadrature property of the first signal 513 with respect to the test signal 210. The first delay time τ may be a quarter period or a quarter period plus a multiple number of half periods of the carrier of the test signal 210. The frequency of the carrier is represented by the angular frequency oo ₀ . The recursive delayer 501 is configured to provide a delayed signal 512 comprising a superposition of a plurality of time-shifted signal components such that the signal components of the delayed test signal 512 are in phase (or in reverse phase) with respect to the test signal 210. The second delay line 522 comprises a second delay time δ which is adjusted to provide said signal components being in- - phase. The second delay time δ may be a half period or a multiple number of half periods of the carrier frequency coo of the test signal 210. The delayed signal 512 comprising the superposition of the plurality of time shifted signal components, has a signal form which may be expressed by

AT

cos[£ fc 4· (t)3 + ^ A ⁿ cos [afct ÷ ( - n<¾]

n=l

Fig. 6 shows a block diagram of an apparatus comprising a recursive delayer according to another embodiment of the invention. The apparatus 700 comprises a recursive delayer 701, a combiner 202 corresponding to the combiner 202 as depicted in Fig. 2b, a phase noise determinator 203 corresponding to the phase noise determinator 203 without the optional analog-to-digital converter 242 as depicted in Fig. 2b and further comprises a phase shifter 710. The recursive delayer 701 is adapted to recursively delay the test signal 210 to provide a delayed signal 712 which is identical to the second signal 714. The phase shifter 710 is adapted to phase shift the test signal 210 to provide the first signal 713. The phase shifter 710 shifts the test signal 210 by a phase of φ.

The recursive delayer 701 comprises an adding device 723 which is adapted to perform an additive superposition of the test signal 210 and the delayed signal 712 to provide a first superposition signal 733. The recursive delayer 701 further comprises an attenuator 725 which is adapted to attenuate the first superposition signal 733 by an attenuation A to provide an attenuated superposition signal 731. The recursive delayer 701 further comprises a delay line 722 which is adapted to delay the attenuated - - superposition signal 731 by a time delay δ to provide the delayed signal 712.

The test signal 210 comprises a carrier of an angular frequency ω ₀ and a phase modulation or phase noise <|)(t), respectively, having the signal form cos (coot+φ ( t ) ) . The first signal 713 which is an output signal of the phase shifter 710 shifting the test, signal 210 by the phase <p may be expressed by cos(co ₀ t + <j)(t) + <p) . The delayed signal 712 may be expressed by

The continuous time representation of the low pass filter output signal u(t) may be expressed as

Fig. 7 shows a block diagram of an apparatus comprising a recursive digital delayer according to an embodiment of the invention. The apparatus 1000 comprises a recursive digital delayer 1001, a combiner 1002 and a phase noise determinator 1003. The recursive digital delayer 1001 is configured to provide a delayed digital signal 1012 on the basis of a digital test signal 1010. The combiner 1002 is adapted to combine a first signal 1013, which first signal 1013 is identical to the digital test signal 1010 or optionally identical to the (analog) test signal 210, with a second signal 1014, which second signal 1014 is identical to the delayed digital signal 1012, to obtain a combiner output signal 1015. The phase noise determinator 1003 is configured to provide a phase noise information u(k) in dependence on the combiner output signal 1015.

The digital test signal 1010 may represent a discrete-time version of the test signal 210 which may be provided by a source under test 220. The discrete-time version of the test signal 210 may be provided by an analog-to-digital converter 1042 being adapted to convert the test signal 210 to the digital test signal 1010. In this embodiment the apparatus 1000 does not comprise the analog-to-digital converter 1042. In other embodiments the apparatus 1000 comprises the analog-to-digital converter 1042. The combiner 1002 may be an analog combiner (e.g. a multiplier or mixer) adapted to perform an analog combination of the first signal 1013 and the second signal 1014 to provide an analog combiner output signal 1015. The combiner 1002 may also be a digital combiner (e.g. an XOR combiner) adapted to digitally combine the first signal 1013 with the second signal 1014 to provide a digital combiner output signal 1015 (e.g. a binary signal). The phase noise determinator 1003 comprises a low-pass filter adapted to low-pass filter the combiner output signal 1015 to provide a low pass filter output signal u(k) corresponding to the phase noise information. The low pass filter 1041 may preferably be an analog low pass filter providing an analog low pass filter output signal u(t). The analog filters may for example be implemented using a RC-circuit. However, other implementations are also possible. The first signal 1013 and/or the second signal 1014 may be analog or digital signals. The low-pass filter 1041 may be an analog filter for analog low-pass filtering a digital (e.g. binary) combiner output signal 1015. The latter case may be advantageous for removing aliasing components from the digital combiner output signal 1015 to have a better detection of the phase noise power corresponding to the phase noise information u(k). The analog-to-digital converter 1042 may also provide a square-wave test signal as the digital test signal 1010. A square-wave test signal comprises two signal states, a first signal state corresponding to a positive signal value of the test signal 210 and a second signal state corresponding to a negative signal value of the test signal 210. Both signal values represent a logical value, which may be processed by a digital combiner, for example an XOR gate or XNOR gate.

The digital test signal 1010 may for example have a rectangular-shaped (or approximately rectangular shaped) signal form. The rectangular-shaped signal form may for example be derived from the analog signal 210 using a threshold comparator, wherein the threshold comparator may act, for example, as a single-bit analog-to-digital converter (taking over the functionality of the analog-to- digital converter 1042) . Alternatively, a signal provided by a digital circuit (for example a digital oscillator) may serve as a digital test signal 1010.

For example, the digital test signal 1010 may be derived from a cosine-shaped signal of the form cos (co ₀ t+i> (t) ) using a threshold comparator. Accordingly, the digital test signal 1010 may for example describe a sign of an analog test signal 210. A fundamental frequency signal of the digital test signal may therefore be approximated by a signal component of the form cos (ω ₀ η+Φ (n) ) (or sin (ω ₀ η+Φ (n) ) , or any time-shifted version thereof) . Naturally, the digital test signal 1010 may comprise harmonic components, which however do not have significant impact (or disturbing impact) on the functionality of the circuit disclosed herein. Alternatively, the analog test signal 210 may be sampled with a higher accuracy (higher than a single-bit accuracy) . Accordingly, the digital test signal 1010 may approximate the analog test signal 210 with improved accuracy. For example, the digital test signal 1010 may comprise the form cos (ω ₀ η+Φ(η)), wherein n denotes the discrete sampling times at which the test signal 210 is sampled.

Assuming a single-bit analog-to-digital conversion of a digital test signal 1210 having a fundamental component of the form cos (ω ₀ η+Φ (n) ) , the digital test signal 1010 may take the form sign (cos (ω ₀ η+Φ (n) )) , wherein sign(x) (also designated as sign{x}) designates a function yielding the sign of the argument x. Similarly, a time-shifted version of the digital test signal 1010 may take the form sign{ cos (ω ₀ (n-d) +Φ (n-d) ) } . Ά phase-shaped version of the digital test signal 1010 may take the form sign (sin (ω ₀ η+Φ (n) ) ) . The sign function "sign(x)" used here provides an output value of 1 (or logic "high") for positive input values and provides an output value of -1 (or logic "low") for negative input values. Further, the sign function used here may for example provide the value of +1 or -1 for an input value of 0.

Accordingly, the sign function used here may deviate from the mathematically defined sign function with its three possible output levels {-1,0,+1}, because the mathematically defined sign function does not accurately describe the conversion into a digital signal with two levels .

The structure of the recursive digital delayer 1001 corresponds to the structure of the recursive delayer 201 as depicted in Fig. 2b with the difference, that internal components of the recursive digital delayer 1001 are adapted to process digital signals. The recursive digital delayer 1001 comprises a first digital delay line 1021, a second digital delay line 1022, a first adding device 1023, a second adding device 1024 and an attenuator 1025. The first digital delay line 1021 is adapted to digitally delay the digital test signal 1010 by a first digital delay time τ to provide the first delayed version 1030 of the digital test signal 1010. The first adding device 1023 is adapted to perform an additive superposition of the first delayed version 1030 of the digital test signal 1010 and a second superposition signal 1032 to provide a first superposition signal 1033. The attenuator 1025 is adapted to attenuate the first superposition signal 1033 by an attenuation A to provide an attenuated superposition signal 1031. The second digital delay line 1022 is adapted to digitally delay the attenuated superposition signal 1031 by a second digital delay time δ to provide the second superposition signal 1032. The second adding device 1024 is adapted to perform an additive superposition of the first delayed version 1030 of the digital test signal 1010 and the second superposition signal 1032 to provide the delayed digital signal 1012 which corresponds to the second signal 1014.

The first and second digital delay lines 1021, 1022 may comprise or may be realized by buffers providing a digital delay corresponding to the time an input of the buffer is buffered. The buffers may optionally be controlled by a control signal, for example by a clock signal. The attenuator 1025 may be realized by a digital multiplication. The first and second digital delay lines 1021, 1022 may also comprise Hilbert transformators providing 90° phase-shifted output signals with respect to their input signals. In this embodiment the first digital delay line 1021 provides the first delayed version 1030 of the digital test signal 1010 such that same is in phase quadrature to the digital test signal 1010. The second digital delay line 1022 provides the second superposition signal 1032 such that same is in phase or in reverse phase with the first superposition signal 1033, and in phase or - - in reverse phase with the first delayed version 1030 of the digital test signal 1010. The second digital delay line 1022 may be realized for example, by a series connection of two buffers (or two Hilbert transformers) providing a phase shift of 180° of the second superposition signal 1032 with respect to the first superposition signal 1033. The first digital delay line 1021 may be realized by a single buffer (or a single Hilbert transformer) providing the first delayed version 1030 of the digital test signal 1010 being in phase quadrature to the digital test signal 1010.

The recursive digital delayer 1001 may be implemented by a digital electronic circuit, for example by an ASIC, by a field programmable gate array or by a programmable logic device. In some cases the recursive delayer may even be implemented using a microchip or microprocessor or may be implemented on a computer system. Also the apparatus 1000 may be implemented by an electronic circuit, for example an integrated circuit, a microprocessor or a logic device. The apparatus 1000 may be configured to receive a digital test signal 1010 having a signal form sign{ cos ((Ook + φ (k) ) } . The recursive digital delayer 1001 may be adapted to provide the second signal 1014 such that the second signal 1014 is in phase quadature to the first signal 1013 which corresponds to the digital test signal 1010.

The digital test signal 1010 is a discrete time representation of the test signal 210 having the signal form sign {cos(co ₀ t + φ (t))}, corresponding to a carrier with the angular frequency ω ₀ and a phase modulation or phase noise of <|)(t) .

Fig. 8 shows a block diagram of an apparatus comprising a recursive digital delayer, according to another embodiment of the invention. The apparatus 1100 comprises a recursive digital delayer 1101, a combiner 1102 and a phase noise determinator 1103. The phase noise determinator 1103 comprises a low-pass filter 1141 and an analog-to-digital - - converter 1142. The apparatus 1100 is adapted to receive a test signal x(t) and adapted to provide a phase noise information 1111. The recursive delayer 1101 is configured to provide a delayed signal x _D (t-x) on the basis of the test signal x(t). The combiner 1102 is configured to combine a first signal 1113 which first signal 1113 is identical to the test signal x(t), with a second signal 1114, which second signal 1114 is identical to the delayed signal x _D (t-x), to obtain a combiner output signal m. The phase noise determinator 1103 is configured to provide a phase noise information 1111 in dependence on the combiner output signal m. The recursive digital delayer 1101 comprises a digital delay time τ by which the recursive digital delayer 1101 recursively delays the test signal x(t) to obtain the delayed test signal x _D (t-x). The recursive digital delayer 1101 is configured to provide the delayed signal x _D (t-x) on the basis of the test signal x(t), such that the delayed signal x _D (t-x) comprises a superposition of a plurality of time-shifted signal components, which signal components are based on the test signal x(t), and which signal components are shifted in time with respect to each other. The recursive digital delayer 1101 may optionally comprise an analog-to-digital converter (e.g. a 1-bit-quantizer) which is not depicted in Fig. 8 to convert the test signal x(t) to its discrete-time representation x _D (t) . The recursive digital delayer 1001 may further comprise a recursive delay line for recursively delaying the discrete-valued (or discrete time) representation of the test signal x(t) and to provide the delayed signal x _D (t-x).

The individual signal components of the delayed digital signal x _D (t-τ) are not explicitly depicted in Fig. 8, they are subsumed by the delayed digital signal x _D (t-x) . The recursive digital delayer 1101 may correspond to the recursive digital delayer 1001 as depicted in Fig. 7. The recursive digital delayer 1101 may alternatively correspond to one of the delayers as depicted in one of the figures 2a - - to 10, wherein components of the delayers are adapted to process digital signals and may comprise, for example, buffers for a delay line, multiplications for an attenuator, RC-circuits (or Hilbert transformators) for a phase shifter or complex valued multiplications for a phase shifter .

Fig. 9 shows a block diagram of an apparatus comprising a recursive digital delayer according to another embodiment of the invention. The apparatus 1200 comprises a recursive digital delayer 1201, a combiner 1202 and a phase noise determinator 1203. The apparatus 1200 is adapted to receive a test signal x(t) and to provide a phase noise information 1211. The apparatus 1200 further comprises a comparator 1230 which is adapted to convert the test signal x(t) to a square-wave test signal x _D (t), wherein the square-wave test signal x _D (t) comprises a first digital value for a positive signal value of the test signal x(t) and comprises a second digital value for a negative signal value of the test signal x(t).

The digital delayer 1201, which may be a recursive digital delayer, comprises a digital delay time τ and may be adapted to recursively delay the square wave test signal x _D (t) to provide a delayed square-wave signal x _D (t-t). The delayed square-wave signal x _D (t-x) may comprise a superposition of a plurality of time-shifted signal components, shifted by the digital delay time τ or a multiple of the digital delay time τ, wherein the signal components are based on the test signal x(t) or based on the square-wave test signal x _D (t), and which signal components are shifted in time with respect to each other by the digital delay time τ or by a multiple of the digital delay time τ. The combiner 1202 is configured to combine a first signal 1013, which first signal 1013 is based on the test signal x(t) and which first signal 1013 is identical to the square-wave test signal x _D (t), with a second signal 1214, which second signal 1214 is identical to the delayed - - digital signal x _D (t-t), to obtain a combiner output signal m(t) .

The combiner 1202 comprises a digital XOR gate which is adapted to perform a logical XOR operation with respect to the first signal 1213 and the second signal 1214 to provide the combiner output signal m(t). Alternatively or in addition, the combiner 1202 may comprise a digital XNOR gate, to perform a logical XNOR operation with respect to the first and second signals 1213, 1214 to provide the combiner output signal m(t) . The phase noise determinator 1203 comprises a latch or flip flop 1232 being adapted to store the combiner output signal m(t) to provide the phase noise information 1211.

The digital output x _D (t) of the comparator 1230 may represent values (-1,+1) instead of (0,1). The previously described analog mixer 1102 as depicted in Fig. 8 can be replaced by a digital XOR gate 1231. Omission of the low pass filter 1141 as depicted in Fig. 11, which has no obvious simple digital correspondent, gives rise to worries about harmful aliasing effects. However, in some embodiments the Aliasing effects are negligible. The initial comparator stage 1230 adds high frequency harmonics to the signal x(t), for example up to the N-th harmonic, which are then (under-) sampled by the flip flop 1232, introducing aliasing. Furthermore, there will be more intermodulation products from the squaring process that may disrupt the ability to distinguish phase noise contributions from different frequencies. The comparator 1230 is adapted to remove amplitude modulation. The XOR gate 1231 performs a mixing function for binary signals representing (-1,+1) to provide the combiner output signal m(t) which comprises intermodulation terms, as there is no filter present that will remove high frequency components. The intermodulation terms around DC approximate the phase noise differences (p(t) - (p(t-nx), wherein n denotes a sequence number of the signal components provided - - by the recursive digital delayer 1201. Unfortunately, other intermodulation products which are related to high frequencies may alias to low frequencies and thus may disrupt the ability to differentiate frequencies of the phase noise spectrum. Nevertheless, in some cases (e.g. for signals having a narrow phase noise distribution) , the Aliasing may be tolerable.

Another embodiment of the invention as depicted in Fig. 10 introduces an analog filter subsequent to the XOR gate to cancel out aliasing signal components.

Fig. 10 shows a block diagram of an apparatus comprising a recursive digital delayer, according to another embodiment of the invention. The apparatus 1300 comprises a recursive digital delayer 1201 corresponding to the recursive digital delayer 1201 as depicted in Fig. 9, a combiner 1202 corresponding to the combiner 1202 as depicted in Fig. 9, a comparator 1230 corresponding to the comparator 1230 as depicted in Fig. 9 and a phase noise determinator 1303. The embodiment of the invention as depicted in Fig. 10 differs from the embodiment of the invention as depicted in Fig. 9 by the phase noise determinator 1303. The phase noise determinator 1303 comprises an analog filter 1341 and an optional analog-to-digital converter 1342. The analog filter 1341 is adapted to filter the combiner output signal m(t), which represents a digital signal, to provide the analog filter output signal d. The analog filter 1341 may filter a digital signal to provide an analog signal. The analog filter output signal d may represent the analog phase noise information 1311. The analog filter output signal d may be optionally converted to a discrete-time representation by the optional analog-to-digital converter 1342 providing the phase noise information 1311 in digital representation. The analog filter 1341 is adapted to remove the higher order intermodulation frequencies aliased to low frequencies such that the analog - - filter output signal d has a high dynamic range for representing the phase noise of the input signal x(t).

Fig. 11 shows a block diagram of an apparatus comprising an adjustable recursive delayer according to an embodiment of the invention. The apparatus 1400 comprises an adjustable recursive delayer 1401, a combiner 1402 and a phase shifter 1403. The apparatus 1400 is adapted to receive a test signal 1410 and _. to provide a phase noise information 1411 which may be identical to a combiner output signal 1415. The combiner is configured to combine a first signal 1413, which first signal 1413 is based on the test signal 1410, with a second signal 1414, which second signal 1414 may be identical to a delayed signal 1412, to obtain the combiner output signal 1415. The phase shifter 1403 is adapted to shift the phase of the test signal 1410 by a phase pi to obtain the first signal 1413. The adjustable recursive delayer 1401 is adapted to recursively delay the test signal 1410 to provide the delayed signal 1412. The adjustable recursive delayer 1401 comprises an adding device 1423, a first attenuator 1425, a second attenuator 1426, a second phase shifter 1427, an optional controller 1428 and an optional power sensor 1429. The adding device 1423 is adapted to perform an additive superposition of the test signal 1410 and an attenuated second superposition signal 1434 to provide a first superposition signal 1432. The first attenuator 1425 is adapted to attenuate the first superposition signal 1432 by an attenuation Al to provide the delayed signal 1412 corresponding to the second signal 1414. The second phase shifter 1427 is adapted to phase shift the delayed signal 1412 by a phase of p2 to provide a second superposition signal 1433. The second attenuator 1426 is adapted to attenuate the second superposition signal 1433 by an attenuation A2 to provide the attenuated second superposition signal 1434. pi, p2, Al and/or A2 may be - - predetermined parameters or adjustable parameters, for example adjusted by an (adaptive) control algorithm.

The optional power sensor 1429 is adapted to sense a power of the delayed signal 1412 to provide a power control signal 1435. The optional controller 1428 is adapted to receive the power control signal 1435, to process a control algorithm depending on the power control signal 1435 and to provide a first attenuator control signal 1436, a second attenuator control signal 1437 and/or a second phase shifter control signal 1438 depending on the control algorithm. The first attenuator 1425 may be optionally configured to adjust the attenuation Al responsive to the first attenuator control signal 1436. The second attenuator 1426 may be optionally configured to adjust the attenuation A2 responsive to the second attenuator control signal 1437. The second phase shifter 1427 may be optionally configured to adjust the phase shift p2 responsive to the second phase shifter control signal 1438.

The optional controller 1428 may be configured to provide the second phase shifter control signal 1438 such that the second phase shifter 1427 adjusts the phase p2 for a maximum power of the delayed signal 1412. The optional controller 1428 may be configured to provide the first attenuator control signal 1436 and the second attenuator control signal 1437 such that the first attenuator 1425 and the second attenuator 1426 adjust their respective attenuations Al and/or A2 to a value slightly below instability with respect to the delayed signal 1412.

The apparatus 1400 may comprise an analog first phase shifter 1403 and/or an analog second phase shifter 1427. However, the apparatus 1400 may also comprise a digital phase shifter 1403 and/or a digital second phase shifter 1427. A digital phase shifter may be, for example, a Hilbert transformer or a complex-valued multiplication unit. By sensing the power of the delayed signal 1412 which - - comprises a superposition of a plurality of time shifted signal components, which signal components are based on the test signal 1410, and which signal components are shifted in time with respect to each other, the controller 1428 is able to control the power of the delayed signal 1412 such that an instability of the adjustable recursive delayer 1404 may be avoided. The phase shifter 1403 may process an analog test signal 1410 and the adjustable recursive delayer 1401 may process a digital version of the test signal 1410. Alternatively, the adjustable recursive delayer 1401 may process an analog test signal 1410 and the phase shifter 1403 may process a digital version of the test signal 1410. Naturally, analog signals may be processed within the first phase shifter 1403 and in the recursive delayer 1401.

A further embodiment of the invention comprises the adjustable recursive delayer 1401 without the optional controller 1428 and without the power sensor 1429. The first attenuation Al, the second attenuation A2 and the phase shift p2 may be adjusted by an offline procedure, for example, such that optimal values for the three parameters are determined. The adjustable recursive delayer 1401 may become non-adjustable by fixing the first attenuation Al, the second attenuation A2 and the phase shift p2 to the predetermined optimal values. A non-adjustable recursive delayer 1401 is easier to implement due to a reduced complexity which also may reduce costs. An adjustable recursive delayer 1401, however, may be used for an automatic test equipment, wherein the optional controller 1428 and the optional power sensor 1429 can automatically adjust the phase p2 for maximum power and wherein the optional controller 1428 and the optional power sensor 1429 can drive the second phase shifter 1427 to (automatically) adjust Al and/or A2 to a value slightly below instability of the adjustable recursive delayer 1401. - -

Fig. 12 shows a block diagram of an apparatus comprising a recursive delayer according to another embodiment of the invention. The apparatus 1500 comprises a recursive delayer 1501, a combiner 1502, a phase noise determinator 1503 and a phase shifter 1504. The apparatus 1500 is adapted to receive a test signal 1510 and to provide a phase noise information z(n). The recursive delayer 1501 is adapted to provide a delayed signal w(t) on the basis of the test signal 1510. The combiner 1502 is configured to combine a first signal 1513, which first signal 1513 is based on the test signal 1510, with a second signal w(t), which second signal w (t) is identical to a delayed signal w(t), to obtain a combiner output signal 1515. The phase noise determinator 1503 is configured to provide a phase noise information z(n) in dependence on the combiner output signal 1515. The phase shifter 1504 is adapted to shift the test signal 1510 in phase to provide the first signal 1513 which is input to the combiner 1502. The recursive delayer 1501 comprises an adding device 1505, a delay line 1506 and a second phase shifter 1507. The adding device 1505 is adapted to perform an additive superposition of the test signal 1510 and a phase-shifted second signal 1534 to provide a superposition signal 1532. The delay line 1506 is adapted to delay the superposition signal 1532 by a delay time T to provide the second signal w(t). The second phase-shifter 1507 is adapted to shift the second signal w(t) in phase to provide the phase shifted second signal 1534. The phase noise determinator 1503 comprises a band-pass filter 1541 and an (optional) analog-to-digital converter 1542. The band pass filter 1541 is adapted to band-pass filter the combiner output signal 1515 to provide a band-pass filter output signal z(t). The (optional) analog-to-digital converter 1542 is adapted to convert the continuous time representation of the band-pass filter output signal z(t) to a discrete-time representation z(n) which corresponds to the phase noise information. - -

Fig. 13 shows a block diagram of an apparatus comprising a recursive delayer according to another embodiment of the invention. The apparatus 1600 comprises a recursive delayer 1601, a combiner 1602 or a mixer, respectively, and a phase noise determinator 1603. The recursive delayer 1601 is adapted to provide a delayed signal w(t) on the basis of the test signal 1610. The combiner 1602 is configured to combine a first signal 1613, which first signal 1613 is based on the test signal 1610, with a second signal 1614, which second signal 1614 is identical to the delayed signal w(t), to obtain a combiner output signal 1615. The phase noise determinator 1603 is configured to provide a phase noise information z(n) 1611 in dependence on the combiner output signal 1615.

The apparatus 1600 further comprises a power splitter 1630, a first phase shifter 1631, a second phase shifter 1632 and a first amplifier 1633. The test signal 1610 may be provided by a waveform generator 1640, which is adapted to provide the test signal 1610 based on an arbitrary I, Q (in-phase, quadrature) signal 1641, which may be preconfigured by a MATLAB device 1642. A MATLAB device may be a computer running the MATLAB software, which is a software for mathematical calculations provided by the company "MATHWORKS". Also another mathematical calculation and design software by other companies may be used. The I,Q signal 1641 describes the in-phase component I and the phase quadrature component Q of the test signal 1610 to be provided by the waveform generator 1640.

The phase noise determinator 1603 comprises a second amplifier 1643 being adapted to amplify the combiner output signal 1615 to provide a continuous time representation of the phase noise information z(t). The phase noise determinator 1603 may optionally comprise an oscilloscope 1644 corresponding to an analog-to-digital converter to convert the continuous-time representation - -

z(t) to the discrete-time representation z(n) of the phase noise information 1611. The phase noise information 1611 may be analyzed by the MATLAB device 1642. The recursive delayer 1601 comprises a first fixed attenuator 1650, a power combiner 1651, a first delay line 1652, a band pass filter 1653, a second delay line 1654, a second fixed attenuator 1655, a third amplifier 1656 and a power divider 1657.

The power splitter 1630 is adapted to split a power of the test signal 1610 to provide a first power splitter output signal 1660 and a second power splitter output signal 1661. The power splitter 1630 is adapted to provide the first and second power splitter output signals 1660, 1661 having approximately the same power. The first phase-shifter 1631 is adapted to shift the phase of the first power splitter output signal 1660 to provide a first phase shifted signal 1662. The first amplifier 1633 is adapted to amplify the first phase-shifted signal 1662 to provide a first amplified phase shifted signal 1663. The second phase shifter 1632 is adapted to phase shift the first amplified phase-shifted signal 1663 to provide the first signal 1613 which is input to the combiner 1602 at a first "LO" input.

The first fixed attenuator 1650 is adapted to attenuate the second power splitter output signal 1661 to provide a first power combiner input signal 1664. The power combiner 1651 is adapted to combine the powers of the first power combiner input signal 1664 and a recursive loop signal 1665 to provide a power combiner output signal 1666. The first delay line 1652 is adapted to delay the power combiner output signal 1666 by a first delay time to provide a first delayed combination signal 1667. The band-pass filter 1653 is adapted to band-pass filter the first delayed combination signal 1667 to provide a band-pass filter output signal 1668. The second delay line 1654 is adapted to delay the band-pass filter output signal 1668 by a - - second delay time to provide a second delayed combination signal 1669. The second fixed attenuator 1655 is adapted to attenuate the second delayed combination signal 1669 to provide a second fixed attenuator output signal 1670. The third amplifier 1656 is adapted to amplify the second fixed attenuator output signal 1670 to provide a power divider input signal 1671. The power divider 1657 is adapted to split the power divider input signal 1671 to provide the recursive loop signal 1665 and the second signal w(t) 1614 which is input to the combiner 1602 at a second "RF" input of the combiner 1602. The power divider 1657 may be configured to divide the power of the power divider input signal such that the second signal 1614 and the recursive loop signal 1665 have approximately the same power.

Fig. 14 shows an equivalent block diagram of the apparatus as depicted in Fig. 16 according to an embodiment of the invention. The gains or attenuations, respectively, of the first phase shifter 1631, the second phase shifter 1632 and the first amplifier 1633 (an additional non-idealities and attenuations of cables and real hardware components) may be substituted by a first gain/attenuation device 1701 which is adapted to amplify/attenuate the first power splitter output signal 1660 to provide the first signal 1613. The gains or attenuations from the waveform generator 1640 to the input of the power splitter 1630 may be substituted by a second gain/attenuation device 1702 being adapted to amplify or attenuate the test signal 1610 to provide a power splitter input signal 1710. The gain or attenuation of the first fixed attenuator 1650 (and additional cables and connecting components) may be substituted by a third gain/attenuation device 1703 which is adapted to attenuate or amplify the second power splitter output signal 1661 to provide the power combiner input signal 1664. The gains or attenuations of the first delay line 1652, the band pass filter 1653, the second delay line 1654, the second fixed attenuator 1655 and the third amplifier 1656 (and additional cables and connecting components) may be - - substituted by a fourth gain/attenuation device 1704 which is adapted to amplify/attenuate the power combiner output signal 1666 to provide the power divider input signal 1671. The gain or attenuation of the recursive loop for connecting the second output of the power divider 1657 with the second input of the power combiner 1651 (comprising cables and connecting components) may be substituted by a fifth gain/attenuation device 1705 which is adapted to amplify/attenuate a second power divider output signal 1711 to provide a second power combiner input signal 1712. The recursive loop signal 1665 as depicted in Fig. 16 corresponds to the second power divider output signal 1711 and to the second power combiner input signal 1712, as in Fig. 16 no explicit device is depicted between the second output of the power divider 1657 and the second input of the power combiner 1651.

The gain or attenuation of the second amplifier 1643 may be substituted by a sixth gain/attenuation device 1706 being adapted to amplify/attenuate the combiner output signal 1615 to provide the second amplifier output signal z(t) .

The first gain/attenuation device 1701 comprises a gain or an attenuation A _x . The second gain/attenuation device 1702 comprises a gain or an attenuation A ₀ . The third gain/attenuation device 1703 comprises a gain or an attenuation A _w . The fourth gain/attenuation device 1704 comprises a gain or an attenuation A _T . The fifth gain/attenuation device 1705 comprises a gain or an attenuation A _f . The sixth gain/attenuation device 1706 comprises a gain or an attenuation G _v .

Fig. 15 shows a block diagram of an apparatus comprising a recursive delayer according to another embodiment of the invention. The apparatus 1800 comprises a recursive delayer 1801, a combiner 1602 corresponding to the combiner 1602 as depicted in Fig. 13, a phase noise - -

determinator 1603 corresponding to the phase noise determinator 1603 as depicted in Fig. 13, a power splitter 1630 corresponding to the power splitter 1630 as depicted in Fig. 13, a first phase shifter 1631, a second phase shifter 1632 and a first amplifier 1633 corresponding to the devices 1631, 1632, 1633 as depicted in Fig. 13. The recursive delayer 1801 is similar to the recursive delayer 1601 as depicted in Fig. 13. The recursive delayer 1801 differs from the recursive delayer 1601 as depicted in Fig. 13 in the loop of the recursive delayer 1801. The recursive delayer 1801 is adapted to connect the second output of the power divider 1657 carrying the second power divider output signal 1711 by a reference impedance of for example 50 ohm to electrical ground. The recursive delayer 1801 is further adapted to connect the second input of the power combiner 1651 carrying the second power combiner input signal 1712 by a reference impedance of for example 50 ohm to electrical ground. The recursive digital delayer 1801 may implement the recursive loop by connecting the second power divider output signal 1711 to the second power combiner input signal 1712 by an electrical loop via ground.

Fig. 16a shows a diagram illustrating a power transmission of the apparatus 1600 as depicted in Fig. 14 for a carrier signal with multi-tone modulation, applied as input signal to the apparatus 1600, the multi-tone modulation having a power of -56 dBm. Fig. 16b shows a diagram illustrating the power transmission of the apparatus 1600 as depicted in Fig. 14 for the input signal as depicted in Fig. 16a, the multi- tone modulation having a power of -76 dBm. The results of the first set of measurements refer to the recursive delay line structure, and are plotted in Figure 16a/b. The tones at frequencies of 1 MHz and 100 KHz are clearly visible both when P _k = -46 dBc/Hz, as shown in - -

Figure 16a, and also when P _k = -66 dBc/Hz, as shown in Figure 19b. The tone at frequency 10 KHz is still observable for P _k = -46 dBc/Hz, and it is buried in the noise for P _k = -66 dBc/Hz. Instead, the value of frequency response |H(/) | ² for / = 1 KHz is not large enough to allow the detection of the tone of index k=0. As expected, when Pic is decreased of 20 dB, also S ₂ (/ _k ) , k = 0,1,..., 3 shows the same decrease, according to the postulated linear behavior of the system. Interestingly, we can notice that the slope of the power spectrum, and thus equivalently the slope of |H(/) I ² , is very close to the theoretical value of 20 dB for each decade in the frequency domain, and precisely is equal to 18.95 dB. This 1 dB variation can be ascribed to the non-linear behavior of the RF components, and in particular to non perfectly frequency-flat gain of the last baseband amplifier.

Fig. 17a shows a diagram illustrating a power transmission of the conventional delay line discriminator 130 as depicted in Fig. lb for the input signal as depicted in Fig. 16a, the multi-tone modulation having a power of -56 dBm.

Fig. 17b shows a diagram illustrating the power transmission of the conventional delay line discriminator 130 as depicted in Fig. lb for the input signal as depicted in Fig. 16a, the multi-tone modulation having a power of -76 dBm. The same input signal as described in Fig. 16a has been applied to the conventional delay line, and the measured results of the signal output PSD are plotted in Figure 17a/b. The most interesting conclusion that we may draw from these results is that the frequency response of the recursive delay line shows a gain of almost 40 dB over the conventional delay line discriminator. - -

18a shows a diagram illustrating the signal-to ratio of the apparatus 1600 as depicted in Fig. 14.

Fig. 18b shows a diagram illustrating the signal-to- noise ratio of the conventional delay line discriminator 130 as depicted in Fig. lb.

The noise figure of the recursive delay line is larger than the noise figure of the single delay line receiver. This can be observed by looking at the noise floor in Figure 16a/b and Figure 17a/b, and in more details in Figure 18a/b. On the one hand, the continuous line plots the PSD of the signal z(t) when x(t)=0, and thus only noise is present at the receiver's input. On the other hand, the dashed line plots the spectrum of the signal z(t) when the multi-tone modulation is turned off, and thus only the carrier is present at the delay line's input. While we can see in Figure 18b that the difference between the two curves is not significant, a much larger discrepancy can be observed in Figure 18a, which plots the signal spectrum for the recursive delay line structure. Basically, we can conclude that the product of the noise at LO mixer' s input with the carrier signal at the RF mixer' s input (and vice versa) is not negligible, and it must be added to the noise £ noise term for a more accurate evaluation of the system' s noise figure. Thus, we may roughly estimate the SNR at /=lMHz as 56 dB and 27 dB for the recursive and conventional delay line architectures, leading to a final performance improvement of about 30dB.

Fig. 19 shows a flow chart for a method for measuring a phase noise of a test signal according to an embodiment of the invention. The method 10 comprises a first step 11 "recursively delaying a signal on the basis of the test signal to obtain a delayed signal", a second step 12 "combining a first signal, which first signal is based on the test signal or identical to the test signal, with a second signal, which second signal is based on the delayed - - signal or identical to the delayed signal to obtain a combination signal" and a third step 13 "providing a phase noise information in dependence on the combination signal". Depending on certain implementation requirements of the inventive methods, the inventive methods can be implemented in hardware or in software. The implementation can be •performed using a digital storage medium, in particular a disc, DVD or a CD having electronically readable control signals stored thereon, which cooperate with a programmable computer system such that the inventive methods are performed. Generally, the present invention is, therefore, a computer program product with a program code stored on a machine-readable carrier, the program code being operative for performing the inventive methods when the computer program product runs on a computer. In other words, the inventive methods are, therefore, a computer program having a program code for performing at least one of the inventive methods when the computer program runs on a computer.

To summarize the above-mentioned, delay line discriminators provide a relative easy and low-cost solution for phase noise measurements. However, they are known to suffer severe sensitivity loss for close-in phase noise measurements. The performance of a novel delay line based architecture, which exploits a feed-back path to enhance the measurement sensitivity is investigated. First, a theoretical derivation and analytical results are presented to illustrate the concept of the new architecture, and then a simple experiment based on real world measurements performed with a prototype instrument are shown and discussed. The measured data show an outstanding gain of about 40 dB over the conventional delay line discriminator, enhancement which is however slightly attenuated by the approximatively 10 dB increased noise figure of the novel architecture, due to the feedback path. The results are obtained for a single frequency, and further investigations are required to extend its measurement capability to a - - wideband regime. In particular, the design of tunable phase shifter over large bandwidth is expected to be a difficult challenge . The output of a physical oscillator can be written as

x{t) = V _:i ,\l + a{t)\ cos|a; _c t + ({t)l ( i )

where V _x is the signal amplitude, a(t) represents the AM noise, and A(t) the PM noise, the latter also referred to as phase noise. The angular deviation A(t) may involve both deterministic and random components, however in general only the random fluctuations are of interest. By neglecting the AM noise, we can rewrite (1) as

x(t.) = _a . cos[o _c i + <j>(t)] = 1 {cos [< (£)] cos(u _c i) - siii[<?i>(£)] sin(a» _c i)},

(2) and, for small phase modulations, i.e. |0(t) |«l, obtain

where we used the approximations cosfO(t)] « 1 and sin[D(t) ] * Φ(ί) .

While the direct spectrum measurement and the reference source measurement rely on a clean, low phase noise RF source, the delay line discriminator shown in Fig. 13 does not need a dedicated RF source reference. A splitter is used to divide the RF signal into two equal level signals. One is applied directly to a mixer, while the second one is - - routed to a delay line, next is passed through a phase shifter, and then is fed into the mixer.

Let us define with w(t) the signal at the output of the phase shifter, after passing through the delay line. It is given as

w(t) =V _X cos[c _c (f — r) -+- 4>{t— T)— a] ,

where a is the adjustable phase shift introduced by the phase shifter, and τ the lag of the delay line. Then, the signal at the output of the mixer and after a lowpass filter h _LPF (t) is given by

z(t) = [x(t)w(t)] * h _LP¥ (t)

= V _z cos( (i) - φ{ί - T) + Θ],

= V, { os{0) - sm(e)[0(t) - 6{t - r)]} _r

where Θ = 2nf _c x + a is the phase shift between the two signals at the mixer's input, and V _z is the signal

amplitude which can be written as

A _S ys being the overall gain (attenuation) of the system. We will use indistinctly the terms gain and attenuation, both defined as the ratio between the output and input signal power. In general we will use the term gain if the ratio is larger than than unity, and the term attenuation otherwise. If the phase shifter a is tuned such that θ ≡ π/2, then the output signal becomes - -

which can be thought as the response of the LTI filter h{t) to the input φ (t) , as shown in Figure lc, and written as

z{t) = V-4>{t) * h(t), _{( 8 )}

where * denotes the convolution operation, and

h(t) 6(t) - S{t - r) . (9)

Using (8), we can compute the (normalized) power spectral density (PSD) of the output signal z (t) as

S ₂ (/) = ² !#(/)! (/) ₍₁₀₎

where S _Z ( ), SctHJ) represent the power spectral densities of the signals z (t) , <P(t) , respectively, and H(f) is the frequency response of the filter with impulse response (t), given by H(f) = 1 - exp(-j2nfz). Then we have

\HU)\ ² = (f)H*{f) = 2 - exp(-j27r/r) - exp(+j2^/r) = 2(1 - οοβ(2π/τ)] = [2 shi(7r/r)] ² .

(11)

We consider voltages across 1 Ohm resistors, so that the instantaneous power is given by p(t) = v (t) i (t) = v ² (t) , - - and S(f) = ^(R _v (T)}, where ^{.} is the Fourier transform operator, and R _v (T) = E (v (t) v (t+τ) } is the voltage autocorrelation function.

Since reasonable values of τ are in the order of few nanoseconds, for small values of the frequency (typically for f<l MHz), it holds f«l and \H(f)\ can be accurately approximated with

and therefore

S _s [f) » (27r/r) ² V?S*(/).

The equation above shows that the phase noise PSD S (f) can be obtained through the PSD measurement of the output signal z (t) , provided that the frequency response's magnitude \H(f)\ and the system attenuation A _sys are known. Using the dB scale, the PSD of the output signal z (t) in [dBm/Hz] becomes

S-(f) [dBm/Hz] = (-164 + r + f) [dB] + PJdBm] + - _sys [dB] + P _fi {f) [dBc/Hz]

where r[dB] ≡ 20 log ₁₀ (τ/lns) , f [dB] ≡ 20 log ₁₀ (f/ΙΗζ) , P _x [dBm] = 10 logio ( (V _x ) ² /lmV) is the carrier power (across a 1Ω resistor) in dB, and A _sys [dB] = 20 log ₁₀ (A _sys ). Equation (13) shows that the power spectral density P _z (f): increases of 20 dB for each decade in the frequency - -

(offset) domain;

increases of 20 dB for each decade in the de domain;

in addition, it obviously depends on the phase no PSD, the carrier power and the system attenuation.

In order to get a feeling on the magnitude of the involved quantities, let us consider a typical source for GSM applications, with S ₀ = [-60,-80,-110,-130,-140] ^T dBc/Hz, measured at the frequencies offsets

[lKHz, lOKHz, lOOKHz, lMHz, 10MHz]. (15)

In addition, let us consider a carrier power P _x = 0 dBm, a delay line with x=lns, and an ideal system with A _sys = OdB. Then we obtain

S _z (f) [dBm/Hz] = (-164 + /) [dB] + ¾(/) [dBm/Hz], , , _fi >

which, when evaluated at the frequencies of interests, provide the vector

S _z = -164 + [60, 80, 100, 120, 140] ^T + = [-164, -164, -174, -174, -164] ^7' [dBm/Hz].

(17)

The last equation shows that the delay line discriminator method considerably attenuates the power spectral density of the phase noise for frequencies close to the carrier, and consequently suffers from reduced sensitivity to close- in phase noise measurements. The low-frequencies strong - - attenuation has however the merit to significantly reduce the dynamic range of the signal at the ADC's input, with important benefits in terms of quantization noise. In particular, for the examined case, the signal power will most likely drop below the noise floor, and the measurement would be impossible.

Two ways to improve the measurement are suggested by (14), and namely: a) we can demand to the DUT (device under test) to increase the power of the carrier P _x ; b) we can use longer delay lines. However, both these approaches are limited by technological constraints, since neither the power P _x nor the delay τ can be made arbitrarily big. Realistic values can bring to a gain of 30 dB (e.g P = 10 dBm, τ = 10 ns), which might be yet insufficient for raising up the signal spectrum from the noise floor.

The biggest concern of the delay line discriminator architecture is the poor performance for close-in phase measurements, due to the strong attenuation that low- frequency components undergo when passing through the delay line discriminator. This attenuation can be so strong that the signal falls below the noise floor, making the phase noise measurement virtually impossible. In this subsection instead we propose a novel receiver architecture, shown in Fig. 3, which reduces the signal attenuation, i.e. it enhances the frequency response \H(f)\ ^z .

It is similar to the receiver architecture presented in the previous section, with the notable difference that after the delay line, the signal is split in two parts: one is routed to the mixer, and the other is first passed through a phase shifter, and then feeded back to the delay line. We call this structure recursive delay line, because at each iteration the accumulated delay is increased by τ ns . The phase shifter is the most critical component, as it must be programmed to phase align the signal from the feedback path with the signal coming from the direct path. As usual, we - - denote with x(t) the signal under test, and with w(t) the signal after the (recursive) delay line. By denoting with A _T and with Aj the attenuations corresponding to the direct path (i.e. the attenuation due to the delay line) and to the feedback line, respectively, we can write

w(t) + < (t. - 2r)] +

CO

?ι=1 (18)

and thus

⁼ * ^^r^ ^cos ^ - sm(W(*) - <b(t - nr)]}

If the phase difference between the two mixer's input signals is tuned to 90 degree, then we have

Neglecting the (irrelevant) sign, the impulse recursive delay line response is given as

(21) - -

and the frequency response is given by

(22)

which can be written

1 - A _T Af '

(23)

whereas we recall that for the conventional delay line the frequency response is given by

With the approximation

we finally obtain

(24) - -

The PSD of the output signal z(t) in [dBm/Hz] becomes

¾(/) [dBm Hz] = ( -164 + τ + /) [dB] + C?[dB] + P |dBm] + A _sy .s[dB | + Ρ{!) [dBc/Hz].

(25)

where

6 ] ^ 2() io _g ,„[ _(i _ ;^ _4/)2 ]

(26)

represents the gain of the recursive delay line architecture over the conventional structure, as seen by comparing (25) with (14).

It is clear from (26) that the largest gain is obtained when the attenuations A _T and A _T A/ are the smallest possible. We can realistically consider A _T = -1 dB and Af = -0.5 dB, to which ideally corresponds an outstanding gain of G = 62 dB. Even though most likely the delay line has attenuation larger than 1 dB, we can add an amplifier to make the overall open-loop gain as close as possible to 0 dB

The block diagram plotted in Figure 13 describes the components used to build a prototype of the recursive delay line, where all the components have been connected with SMA cables. First, we needed a signal source with a controllable phase noise. For this purpose, we used the IQ arbitrary waveform generator capability provided by the Agilent E4438C vector signal generator. Since in general the signal generated by a physical oscillator can be written as _ _

x(t) = cos[cut + (j){t)} = cos[ (i)] cos(w _c i) - tim ^' {0(t)]sm(j _c t),

a phase noise waveform <P(t) with arbitrary PSD can be synthesized by providing the Agilent instruments with the I and Q samples computed as cos(<P(t)) and sin (<P(t) ) _f respectively. Once the desired PSD is chosen, a single realization of the stochastic process Φ (t) is generated with an algorithm implemented with Matlab, and the I and Q samples are computed and downloaded to the instrument by using a GPIB interface. The instrument can be controlled by using the Instrument Control Toolbox available in Matlab, and by using a dedicated IVI-COM driver, available from the Agilent website.

As pointed out in the previous section, the gain of the recursive delay line over conventional delay line discriminators depends critically on the attenuation of the open-loop and feed-back paths, which are schematically indicated in Figure 14 as A _T and A/, respectively. Figure 14 is an equivalent description of the real hardware setting, plotted in Figure 13, where the non-ideality and attenuation of cables and real components are grouped together, according to the physical position in the prototype. Thus, for instance, the attenuation due to the cable connecting the Agilent source with the power splitter, and the loss due to power splitter itself, are grouped in the block with gain (attenuation) A ₀ . Similarly, the non-ideality of the power combiner, the loss of the delay line, the attenuator, the gain of the amplifier, and the loss of the power divider before the mixer, are grouped in the term A _z , the open-loop gain. A _x represents the attenuation experienced from the signal traveling from the output of the first power splitter to the input of the mixer, A _w is the fixed attenuator inserted before the closed-loop implementing the recursive delay line, A/ is the attenuation of the signal passing through the feedback - - path, and G _v is the gain of the baseband amplifier, required to raise the signal level to values adequate for the oscilloscope. The choice and position of the components in Figure 14 is dictated by the following considerations:

1) It must hold A _T < 0 dB and A _f < 0 dB, for all the frequencies, in order to avoid unwanted oscillations. Meanwhile, they must be as close as possible to 0 dB, in order to guarantee the desired gain (26) over the conventional delay line.

2) The recommended signal power at the LO mixer's input is 7 dBm, and the input 1 dB compression point is equal to 1 dBm. In order to satisfy the first condition, an amplifier with ideally a gain slightly smaller than the attenuation due to the RF passive components should be placed just after the power combiner. Unfortunately, the gain of the available amplifier largely exceeded the attenuation of the delay lines and power slitter/combiner, thus an extra attenuator had to be placed in the direct path of the loop. In addition, care must be taken to make sure that the amplifier operates in the linear regime, requiring the insertion of another attenuator (A _w ) between the first splitter and the power combiner. The insertion of such attenuators has the significant drawback of considerably increasing the noise figure of the overall system, with consequent loss of measurement sensitivity. These considerations lead to the choice of the architecture depicted in Figure 16, where the value of the first attenuator is -8 dB, and the value of the second attenuator, positioned between the delay line and the amplifier, is -10 dB.

The value of the parameters in the equivalent representation of Fig. 14 have been measured as: Ao = -4.6 dB, A _x = +21 dB, A _w = -8 dB, A _r = -0.35 dB, and A _f = -0.42 dB. The power of the input signal x(t) has been chosen - - equal to -10 dBm, and thus the power of the LO signal is approximatively equal to 6.5 dBm, and the power of the RF signal is approximatively equal to -5 dBm. A final remark regards the absence of the phase shifter in the feedback path of the recursive delay line. In order to demonstrate the concept of this novel architecture, we focused on a single frequency, and thus we choose the frequency for which the signal after the feedback path is phase aligned with the the signal directly entering the recursive delay line. One frequency verifying this condition has been found to be equal to 3.226027 GHz.

As already anticipated, the insertion of (at least in theory) unnecessary attenuators largely increases the noise figure of the system, making the current version of the prototype unsuited to absolute measurements of sources with good phase noise properties. However, after all, the main point of this experiment was to verify and quantify the gain of the recursive delay line structure over conventional delay line discriminators. This comparison is the topic of what follows.

By recalling that for both structures it holds

¾(/) = l? |ff(/)| ² S*(/), ₂

where the absolute value of the frequency response is analytically evaluated as

\H(f)\ * 27Γ/Τ, (29) - - for the conventional delay line discriminator, and is given as

for the recursive delay line, our goal is to measure and compare the frequency responses of the two competing architectures. The recursive delay line's hardware set up is the one shown in Figure 13, while the hardware configuration of the conventional delay line discriminator is shown in Figure 15. With this choice, the value of V _z is the same for both the architectures, and thus the performance of the two measurements systems can be compared by simply measuring the PSD of the output signal z(t), i.e. S _z (f) . Before to proceed with the PSD measurements, we do a simple verification on the assumption that V _z is the same for both architectures. By tuning the phase shifter in such a way that Θ = 0, from (5) and (19) we obtain

:3i)

for the conventional and recursive delay line architectures, respectively. Measuring z (t) in both cases at the oscilloscope (without the amplifier G _v , which is inherently passband) , we get z(t) ^(c> = 13.74 mV and z(t) ^lr> = 146 mV. Their ratio in dB is approximatively 20.5 dB, which is in excellent agreement with the theoretical value of 201og ₁₀ (A _T /l-A _T Af) = 20.74 dB, computed by substituting in - - the previous expression the measured values of A _T = -0.35 dB and A _f = -0.42 dB.

After this verification, we can compare the performance of the two architectures, by measuring the PSD of z(t) for θ-π/2, with the same input signal x(t). For all the measurements the oscilloscope sampling frequency has been set to 10 sa/s. The values are read using Agilent VEE software, and then exported to Matlab, where the PSD of the samples z[n] is computed using the Welch's algorithm, where the voltages have been normalized to a reference impedance of 50 Ω. The oscilloscope's memory is equal to 32768 samples, and 15 blocks of samples are acquired and used to evaluate the PSD. Thus, in total we have 32768 x 15 = 491520 samples, corresponding to an observation window of 49.2 msec.

In order to highlight the frequency response, we choose to excite the system with a multitone input signal, where the tones have the following frequency offset from the carrier f _c = 3.226027 GHz:

/ ^/, . (33)

for k = 0,1,..., 3. The input carrier power has been set to -10 dBm, and the power of the multi-tones first to -56 dBm, and then to -76 dBm. Hence, the PSD Ξ _φ (/) is given by

where P _k = {-56, -76} + 10 = {-46, -66} dBc/Hz. - -

The results of the first set of measurements refer to the recursive delay line structure, and are plotted in Figure 16a/b. The tones at frequencies of 1 MHz and 100 KHz are clearly visible both when P _k = -46 dBc/Hz, as shown in Figure 16a, and also when P _k = -66 dBc/Hz, as shown in Figure 16b. The tone at frequency 10 KHz is still observable for P _k = -46 dBc/Hz, and it is buried in the noise for P _k = -66 dBc/Hz. Instead, the value of frequency response \H(f)\ ² for / = 1 KHz is not large enough to allow the detection of the tone of index k=0. As expected, when P _k is decreased of 20 dB, also S _z (f _k ), k = 0,1,..., 3 shows the same decrease, according to the postulated linear behavior of the system. Interestingly, we can notice that the slope of the power spectrum, and thus equivalently the slope of \ (f)\ ² , is very close to the theoretical value of 20 dB for each decade in the frequency domain, and precisely is equal to 18.95 dB . This 1 dB variation can be ascribed to the non-linear behavior of the RF components, and in particular to non perfectly frequency-flat gain of the last baseband amplifier.

The same input signal has been applied to the conventional delay line, and the measured results of the signal output PSD are plotted in Figure 17a/b. The most interesting conclusion that we may draw from these results is that the frequency response of the recursive delay line shows a gain of almost 40 dB over the conventional delay line discriminator ! However, the noise figure of the recursive delay line is larger than the noise figure of the single delay line receiver. This can be observed by looking at the noise floor in Figure 16a/b and Figure 17a/b, and in more details in Figure 18a/b. On the one hand, the continuous line plots the PSD of the signal z (t) when x(t)=0, and thus only noise is present at the receiver's input. On the other hand, the dashed line plots the spectrum of the signal z(t) when the multi-tone modulation is turned off, and thus only the - - carrier is present at the delay line's input. While we can see in Figure 18b that the difference between the two curves is not significant, a much larger discrepancy can be observed in Figure 18a, which plots the signal spectrum for the recursive delay line structure. Basically, we can conclude that the product of the noise at LO mixer's input with the carrier signal at the RF mixer's input (and viceversa) is not negligible, and it must be added to the noise term for a more accurate evaluation of the system' s noise figure. Thus, we may roughly estimate the SNR at /=lMHz as 56 dB and 27 dB for the recursive and conventional delay line architectures, leading to a final performance improvement of about 30dB.