APPARATUS AND METHOD FOR ACTIVATING BASEBAND COMPONENTS WHILE IN DISCONTINUOUS RECEPTION MODE BACKGROUND [0001] Embodiments of the present disclosure relate to apparatus and method for wireless communication. [0002] Wireless communication systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, and broadcasts. In cellular communication, such as the 4th-generation (4G) Long Term Evolution (LTE) and the 5th- generation (5G) New Radio (NR), the 3rd Generation Partnership Project (3GPP) defines various operations for discontinuous reception (DRX). SUMMARY [0003] According to one aspect of the present disclosure, a first exemplary baseband chip is provided. The baseband chip may include a plurality of baseband components configured to enter an inactive state at a start of an inactive period of a DRX cycle. The baseband chip may include an always-on component. The always-on component may be configured to remain in an active state during the inactive period of the DRX cycle. The always-on component may be configured to sequentially activate a first subset of the plurality of baseband components during a first portion of the inactive period of the DRX cycle. The always-on component may be configured to concurrently activate a second subset of the plurality of baseband components during a second portion of the DRX cycle following the first portion. [0004] According to another aspect of the disclosure, a second exemplary baseband chip is provided. The baseband chip may include a plurality of baseband components configured to enter an inactive state at a start of an inactive period of a DRX cycle. The baseband chip may include an always-on component. The always-on component may be configured to remain in an active state during the inactive period of the DRX cycle. The always-on component may be configured to sequentially activate a first subset of the plurality of baseband components during a first portion of the inactive period of the DRX cycle. The baseband chip may include a PHY controller bootloader configured to concurrently activate a second subset of the plurality of baseband components during a second portion of the DRX cycle following the first portion. In some embodiments, the physical layer (PHY) controller bootloader may be part of the first subset of the plurality of baseband components sequentially activated by the always-on component during the first portion of the inactive period of the DRX cycle. [0005] According to yet another aspect of the present disclosure, a method of wireless communication of a baseband chip is provided. The method may include entering, by a plurality of baseband components, an inactive state at a start of an inactive period of a DRX cycle. The method may include remaining, by an always-on component, in an active state during the inactive period of the DRX cycle. The method may include sequentially activating, by the always-on component, a first subset of the plurality of baseband components during a first portion of the inactive period of the DRX cycle. The method may include concurrently activating, by the always- on component, a second subset of the plurality of baseband components during a second portion of the DRX cycle following the first portion. [0006] These illustrative embodiments are mentioned not to limit or define the present disclosure, but to provide examples to aid understanding thereof. Additional embodiments are discussed in the Detailed Description, and further description is provided there. BRIEF DESCRIPTION OF THE DRAWINGS [0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure. [0008] FIG.1A illustrates a block diagram of an example baseband chip. [0009] FIG. 1B illustrates an example timing diagram for waking up various baseband components while operating in DRX mode. [0010] FIG. 2 illustrates an exemplary wireless network, according to some embodiments of the present disclosure. [0011] FIG. 3 illustrates a block diagram of an exemplary node, according to some embodiments of the present disclosure. [0012] FIG. 4 illustrates a block diagram of an exemplary apparatus including a first baseband chip, a second baseband chip, a radio frequency (RF) chip, and a host chip, according to some embodiments of the present disclosure. [0013] FIG. 5A illustrates a first exemplary timing diagram for waking up various baseband components while operating in DRX mode, according to some embodiments of the present disclosure. [0014] FIG. 5B illustrates a second exemplary timing diagram for waking up various baseband components while operating in DRX mode, according to some embodiments of the present disclosure. [0015] FIG. 5C illustrates a third exemplary timing diagram for waking up various baseband components while operating in DRX mode, according to some embodiments of the present disclosure. [0016] FIG. 6 is a flowchart of a first exemplary method of wireless communication, according to certain embodiments of the present disclosure. [0017] FIG. 7 is a flowchart of a second exemplary method of wireless communication, according to certain embodiments of the present disclosure. [0018] Embodiments of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION [0019] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications. [0020] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” “certain embodiments,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. [0021] In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context. [0022] Various aspects of wireless communication systems will now be described with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the particular application and design constraints imposed on the overall system. As used herein, the term “baseband component” means any software, firmware, and/or hardware circuits configured to perform any operation associated with the baseband chip. [0023] The techniques described herein may be used for various wireless communication networks, such as code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, orthogonal frequency division multiple access (OFDMA) system, single-carrier frequency division multiple access (SC- FDMA) system, wireless local area network (WLAN) system, and other networks. The terms “network” and “system” are often used interchangeably. A CDMA network may implement a radio access technology (RAT), such as Universal Terrestrial Radio Access (UTRA), evolved UTRA (E-UTRA), CDMA 2000, etc. A TDMA network may implement a RAT, such as the Global System for Mobile Communications (GSM). An OFDMA network may implement a RAT, such as LTE or NR. A WLAN system may implement a RAT, such as Wi-Fi. The techniques described herein may be used for the wireless networks and RATs mentioned above, as well as other wireless networks and RATs. [0024] DRX is an important power-saving technique in cellular communications. There are two types of DRX modes: connected-mode DRX (CDRX) and idle-mode DRX (IDRX). In either mode, DRX may be implemented to reduce power consumption by allowing a user equipment (UE) to periodically enter a deep-sleep state during an inactive period of a DRX cycle. During the inactive period, the UE is not expected to monitor the physical downlink control channel (PDCCH) for incoming downlink (DL) data packets. A DRX cycle also includes an active period (also referred to an “on-duration”) during which the UE is awake and monitors the PDCCH for incoming DL data before returning to the deep-sleep state at the start of a subsequent DRX cycle. To ensure the baseband components are up and running at the start of the on-duration, the UE powers on its baseband components during a wake-up period of the inactive period that precedes the active period. One challenge of DRX relates to the length of the wake-up period and the amount of power consumed while waking up the baseband components from the deep-sleep state. An example baseband chip and a timing diagram associated with its inactive period, wake- up period, and active period are described below in connection with FIGs.1A and 1B, respectively. [0025] For example, FIG.1A illustrates a block diagram 100 of an example baseband chip 102 configured to perform DRX. FIG. 1B illustrates an example timing diagram 115 for waking up baseband components from a deep-sleep state. FIGs.1A and 1B will be described together. [0026] Referring to FIG. 1A, baseband chip 102 includes a central processing unit (CPU) 110, a direct memory access (DMA) memory 120, an always-on component (AON) 130, a system- on-chip (SoC) bus 140 (e.g., a bus interconnect), a PHY subsystem 150, and a double date rate (DDR) controller 160, which is coupled to a DDR chip 108 located external to baseband chip 102. As shown, PHY subsystem 150 includes a PHY control bus 152, a PHY controller 154, a baseband- radio frequency (BB-RF) interface 156 coupled to an RF chip 104, and signal processing component(s) 158. [0027] To enable wireless communication (e.g., such as LTE, 5G NR, etc.), baseband chip 102 supports both lower PHY layer (also referred to as “Layer 1”) operations and upper layers (e.g., Layer 2, Layer 3, etc.) operations of the wireless protocol stack. Operations associated with the upper layer(s) may be performed by CPU 110, while PHY layer operations are performed by PHY subsystem 150. The control and scheduling of operations at PHY subsystem 150 may be performed/coordinated by PHY controller 154, which may include one or more processors, microcontrollers, hardware accelerators, or a combination thereof. Communications between the PHY subsystem 150 and the other baseband components depicted in FIG. 1A may be facilitated via SoC bus 140. RF/BB-interface 156 is responsible for sending/receiving data to/from RF chip 104, and may be implemented as a standardized high-speed interface (e.g., peripheral component interconnect express (PCIe), mobile industry processor interface (MIPI), universal serial bus (USB), serial advanced technology attachment (SATA), a proprietary interface, etc.). Signal processing component(s)158 process downlink (DL) data packets received from RF chip 104 via RF/BB-interface 156. Once PHY packet processing is complete, the DL data packets may be sent to the upper layers. Moreover, signal processing component(s) 158 may receive uplink (UL) data packets (e.g., medium access control packets) from the upper layers for PHY processing before transmission over the air via RF chip 104. [0028] Although not shown, baseband chip 102 may include a primary crystal (e.g., 38.4 MHz or 76.8MHz crystal) that sets the clock frequency used to run the majority of the components depicted in FIG.1A, while a secondary crystal (e.g., 32kHz crystal) is used to run AON 130. The secondary crystal consumes less power than the primary crystal and remains on during the deep- sleep state to run AON 130. The primary crystal, on the other hand, is powered off during the deep-sleep state along with its associated baseband components. Among other tasks, AON 130 is responsible for activating baseband chip 102 in the lead up to the active period 103 of a DRX cycle. In the example baseband chip 102 depicted in FIG.1A, AON 130 activates baseband components sequentially during inactive period 101. For instance, AON 130 first powers up SoC bus 140, followed by DDR controller 160. AON 130 activates PHY controller 154 once DDR controller 160 is up and running, and DDR controller 160 downloads the data/codes to PHY controller 154 from in DDR chip 108. Then, PHY controller 154 activates RF/BB-interface 156 before powering on signal processing components 158. One limiting factor as to when RF/BB-interface 156 will be ready to receive incoming data from RF chip 104 is the settling time of the analog circuit of RF/BB-interface 156. The analog circuit of RF/BB-interface 156 needs a longer time to settle that most of the other components. At best, RF/BB-interface 156 may be up and running at the same time as signal processing components 158 by the desired time to receive data. [0029] The drawback of the sequential wake-up process described above is its undesirable length and the associated power consumption. Because the time at which baseband chip 102 is expected to be activated to receive DL data (e.g., the start of the active period) is fixed and the settling time of the analog circuit in RF/BB-interface 156 can be lengthy, using PHY controller 154 to wakeup RF/BB-interface 156 is costly in terms of time and power. [0030] Thus, there exists an unmet need for a wakeup procedure that reduces overall length and power consumption of the collective wakeup period during a DRX cycle. [0031] To overcome these and other challenges, the present disclosure provides an exemplary wakeup procedure that reduces the overall wake-up period of the baseband chip by activating a first subset of baseband components sequentially and a second subset of baseband components concurrently. For example, in some embodiments, the AON may sequentially activate the SoC bus and the DDR controller and concurrently activate the PHY controller and the RF/BB- interface in order to reduce the overall length of the collective wakeup period for these components. In another example, the AON may sequentially activate the SoC bus, the DDR controller, and a PHY controller bootloader (also referred to herein as “bootloader”), while the PHY controller bootloader concurrently activates the PHY controller and the RF/BB-interface. In either embodiment, once the PHY controller is up in running, it may activate the signal processing component(s) so that is up and running by the start of the DRX cycle’s active period. By waking up certain baseband components concurrently, the length of the collective wake-up period, thereby reducing its associated power consumption. Additional details of the exemplary wakeup procedure are provided below in connection with FIGs.2-7. [0032] FIG.2 illustrates an exemplary wireless network 200, in which some aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure. As shown in FIG. 2, wireless network 200 may include a network of nodes, such as a user equipment 202, an access node 204, and a core network element 206. User equipment 202 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Internet-of-Things (IoT) node. It is understood that user equipment 202 is illustrated as a mobile phone simply by way of illustration and not by way of limitation. [0033] Access node 204 may be a device that communicates with user equipment 202, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, or the like. Access node 204 may have a wired connection to user equipment 202, a wireless connection to user equipment 202, or any combination thereof. Access node 204 may be connected to user equipment 202 by multiple connections, and user equipment 202 may be connected to other access nodes in addition to access node 204. Access node 204 may also be connected to other user equipments. When configured as a gNB, access node 204 may operate in millimeter wave (mmW) frequencies and/or near mmW frequencies in communication with the user equipment 202. When access node 204 operates in mmW or near mmW frequencies, the access node 204 may be referred to as an mmW base station. Extremely high frequency (EHF) is part of the RF in the electromagnetic spectrum. EHF has a range of 30 GHz to 300 GHz and a wavelength between 1 millimeter and 10 millimeters. Radio waves in the band may be referred to as a millimeter wave. Near mmW may extend down to a frequency of 3 GHz with a wavelength of 200 millimeters. The super high frequency (SHF) band extends between 3 GHz and 30 GHz, also referred to as centimeter wave. Communications using the mmW or near mmW radio frequency band have extremely high path loss and a short range. The mmW base station may utilize beamforming with user equipment 202 to compensate for the extremely high path loss and short range. It is understood that access node 204 is illustrated by a radio tower by way of illustration and not by way of limitation. [0034] Access nodes 204, which are collectively referred to as E-UTRAN in the evolved packet core network (EPC) and as next generation radio access network (NG-RAN) in the 5G core network (5GC), interface with the EPC and 5GC, respectively, through dedicated backhaul links (e.g., S1 interface). In addition to other functions, access node 204 may perform one or more of the following functions: transfer of user data, radio channel ciphering and deciphering, integrity protection, header compression, mobility control functions (e.g., handover, dual connectivity), inter-cell interference coordination, connection setup and release, load balancing, distribution for non-access stratum (NAS) messages, NAS node selection, synchronization, radio access network (RAN) sharing, multimedia broadcast multicast service (MBMS), subscriber and equipment trace, RAN information management (RIM), paging, positioning, and delivery of warning messages. Access nodes 204 may communicate directly or indirectly (e.g., through the 5GC) with each other over backhaul links (e.g., X2 interface). The backhaul links may be wired or wireless. [0035] Core network element 206 may serve access node 204 and user equipment 202 to provide core network services. Examples of core network element 206 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is a core network for the LTE system. Other core network elements may be used in LTE and in other communication systems. In some embodiments, core network element 206 includes an access and mobility management function (AMF), a session management function (SMF), or a user plane function (UPF) of the 5GC for the NR system. The AMF may be in communication with a Unified Data Management (UDM). The AMF is the control node that processes the signaling between the user equipment 202 and the 5GC. Generally, the AMF provides QoS flow and session management. All user Internet protocol (IP) packets are transferred through the UPF. The UPF provides user equipment (UE) IP address allocation as well as other functions. The UPF is connected to the IP Services. The IP Services may include the Internet, an intranet, an IP Multimedia Subsystem (IMS), a PS Streaming Service, and/or other IP services. It is understood that core network element 206 is shown as a set of rack-mounted servers by way of illustration and not by way of limitation. [0036] Core network element 206 may connect with a large network, such as the Internet 208, or another Internet Protocol (IP) network, to communicate packet data over any distance. In this way, data from user equipment 202 may be communicated to other user equipments connected to other access points, including, for example, a computer 210 connected to Internet 208, for example, using a wired connection or a wireless connection, or to a tablet 212 wirelessly connected to Internet 208 via a router 214. Thus, computer 210 and tablet 212 provide additional examples of possible user equipments, and router 214 provides an example of another possible access node. [0037] A generic example of a rack-mounted server is provided as an illustration of core network element 206. However, there may be multiple elements in the core network including database servers, such as a database 216, and security and authentication servers, such as an authentication server 218. Database 216 may, for example, manage data related to user subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 218 may handle authentication of users, sessions, and so on. In the NR system, an authentication server function (AUSF) device may be the entity to perform user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between core network element 206, authentication server 218, and database 216, may be local connections within a single rack. [0038] Each element in FIG. 2 may be considered a node of wireless network 200. More detail regarding the possible implementation of a node is provided by way of example in the description of a node 300 in FIG. 3. Node 300 may be configured as user equipment 202, access node 204, or core network element 206 in FIG.2. Similarly, node 300 may also be configured as computer 210, router 214, tablet 212, database 216, or authentication server 218 in FIG. 2. As shown in FIG. 3, node 300 may include a processor 302, a memory 304, and a transceiver 306. These components are shown as connected to one another by a bus, but other connection types are also permitted. When node 300 is user equipment 202, additional components may also be included, such as a user interface (UI), sensors, and the like. Similarly, node 300 may be implemented as a blade in a server system when node 300 is configured as core network element 206. Other implementations are also possible. [0039] Transceiver 306 may include any suitable device for sending and/or receiving data. Node 300 may include one or more transceivers, although only one transceiver 306 is shown for simplicity of illustration. An antenna 308 is shown as a possible communication mechanism for node 300. Multiple antennas and/or arrays of antennas may be utilized for receiving multiple spatially multiplex data streams. Additionally, examples of node 300 may communicate using wired techniques rather than (or in addition to) wireless techniques. For example, access node 204 may communicate wirelessly to user equipment 202 and may communicate by a wired connection (for example, by optical or coaxial cable) to core network element 206. Other communication hardware, such as a network interface card (NIC), may be included as well. [0040] As shown in FIG. 3, node 300 may include processor 302. Although only one processor is shown, it is understood that multiple processors can be included. Processor 302 may include microprocessors, microcontroller units (MCUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. Processor 302 may be a hardware device having one or more processing cores. Processor 302 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also permitted under the broad category of software. [0041] As shown in FIG. 3, node 300 may also include memory 304. Although only one memory is shown, it is understood that multiple memories can be included. Memory 304 can broadly include both memory and storage. For example, memory 304 may include random-access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferro- electric RAM (FRAM), electrically erasable programmable ROM (EEPROM), compact disc read- only memory (CD-ROM) or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 302. Broadly, memory 304 may be embodied by any computer-readable medium, such as a non-transitory computer-readable medium. [0042] Processor 302, memory 304, and transceiver 306 may be implemented in various forms in node 300 for performing wireless communication functions. In some embodiments, at least two of processor 302, memory 304, and transceiver 306 are integrated into a single system- on-chip (SoC) or a single system-in-package (SiP). In some embodiments, processor 302, memory 304, and transceiver 306 of node 300 are implemented (e.g., integrated) on one or more SoCs. In one example, processor 302 and memory 304 may be integrated on an application processor (AP) SoC (sometimes known as a “host,” referred to herein as a “host chip”) that handles application processing in an operating system (OS) environment, including generating raw data to be transmitted. In another example, processor 302 and memory 304 may be integrated on a baseband processor (BP) SoC (sometimes known as a “modem,” referred to herein as a “baseband chip”) that converts the raw data, e.g., from the host chip, to signals that can be used to modulate the carrier frequency for transmission, and vice versa, which can run a real-time operating system (RTOS). In still another example, processor 302 and transceiver 306 (and memory 304 in some cases) may be integrated on an RF SoC (sometimes known as a “transceiver,” referred to herein as an “RF chip”) that transmits and receives RF signals with antenna 308. It is understood that in some examples, some or all of the host chip, baseband chip, and RF chip may be integrated as a single SoC. For example, a baseband chip and an RF chip may be integrated into a single SoC that manages all the radio functions for cellular communication. [0043] Referring back to FIG. 2, in some embodiments, user equipment 202 may include a baseband chip configured to perform one or more of the exemplary wake-up procedures described herein. By performing one of the exemplary wake-up procedures described below, the length and power consumption of the collective wake-up period for its baseband chip may be reduced by activating a first subset of baseband components sequentially and a second subset of baseband components concurrently. Additional details of the exemplary wakeup procedure implemented by user equipment 202 are provided below in connection with FIGs.5A-5C. [0044] FIG. 4 illustrates a block diagram of an apparatus 400 including a baseband chip 402, an RF chip 404, and a host chip 406, according to some embodiments of the present disclosure. Apparatus 400 may be implemented as UE 202 of wireless network 200 in FIG. 2. As shown in FIG. 4, apparatus 400 may include baseband chip 402, RF chip 404, host chip 406, and one or more antennas 410. In some embodiments, baseband chip 402 is implemented by a processor and a memory, and RF chip 404 is implemented by a processor, a memory, and a transceiver. Besides the on-chip memory 418 (also known as “internal memory,” e.g., registers, buffers, or caches) on each chip 402, 404, or 406, apparatus 400 may further include an external memory 408 (e.g., the system memory or main memory) that can be shared by each chip 402, 404, or 406 through the system/main bus. Although baseband chip 402 is illustrated as a standalone SoC in FIG. 4, it is understood that in one example, baseband chip 402 and RF chip 404 may be integrated as one SoC or one SiP; in another example, baseband chip 402 and host chip 406 may be integrated as one SoC or one SiP; in still another example, baseband chip 402, RF chip 404, and host chip 406 may be integrated as one SoC or one SiP, as described above. [0045] In the uplink, host chip 406 may generate raw data and send it to baseband chip 402 for encoding, modulation, and mapping. Interface 414 of baseband chip 402 may receive the data from host chip 406. Baseband chip 402 may also access the raw data generated by host chip 406 and stored in external memory 408, for example, using the direct memory access (DMA). Baseband chip 402 may first encode (e.g., by source coding and/or channel coding) the raw data and modulate the coded data using any suitable modulation techniques, such as multi-phase shift keying (MPSK) modulation or quadrature amplitude modulation (QAM). Baseband chip 402 may perform any other functions, such as symbol or layer mapping, to convert the raw data into a signal that can be used to modulate the carrier frequency for transmission. In the uplink, baseband chip 402 may send the modulated signal to RF chip 404 via interface RF/BB-interface 460. RF chip 404, through the transmitter, may convert the modulated signal in the digital form into analog signals, i.e., RF signals, and perform any suitable front-end RF functions, such as filtering, digital pre-distortion, up-conversion, or sample-rate conversion. Antenna 410 (e.g., an antenna array) may transmit the RF signals provided by the transmitter of RF chip 404. [0046] In the downlink, antenna 410 may receive RF signals from an access node or other wireless device. The RF signals may be passed to the receiver (Rx) of RF chip 404. RF chip 404 may perform any suitable front-end RF functions, such as filtering, IQ imbalance compensation, down-paging conversion, or sample-rate conversion, and convert the RF signals (e.g., transmission) into low-frequency digital signals (baseband signals) that can be processed by baseband chip 402. [0047] As illustrated in FIG. 4, baseband chip 402 may include (in addition to on-chip memory 418) a plurality of baseband components, e.g., such as an AON 420, an SoC bus 430, a DDR controller 440, a PHY controller 450, RF/BB-interface 460, and signal processing component(s) 470, just to name a few. In some embodiments, AON 420 may sequentially activate SoC bus 430 and DDR controller 440 during a first time period and concurrently activate PHY controller 450 and RF/BB-interface 460 during a second time period, as shown in FIG. 5A. In some embodiments, AON 420 may sequentially activate SoC bus 430 and DDR controller 440 during a first time period and concurrently activate PHY controller 450 and an analog circuit (not shown) of RF/BB-interface 460 during a second time period, as shown in FIG. 5B. Here, once PHY controller 450 is up and running, it may concurrently activate a digital circuit (not shown) of RF/BB-interface 460 and signal processing component(s) 470. In some embodiments, AON 420 may sequentially activate SoC bus 430, DDR controller 440, and the PHY bootloader (not shown) of PHY controller 450 during a first time period, while the PHY bootloader concurrently activates PHY controller 450 and RF/BB-interface 460 during a second time period following the first time period. In each of these embodiments, once up and running, PHY controller 450 may activate signal processing component(s) 470 during a third time period that overlaps with the second time period. RF/BB-interface 460 may need some time (e.g., 1ms, 2ms, 3ms, etc.) to wake-up and settle, while PHY controller 450 may also require some time (e.g., 1ms, 2ms, 3ms, etc.) to wake- up and boot-up. Thus, by activating PHY controller 450 and RF/BB-interface concurrently (e.g., in parallel) using one of the above-described embodiments, the collective wake-up period of the baseband components may be reduced by up to or greater than 20%, with a reduction in wake-up period power consumption of up to or greater than 30%, as compared to the wake-up period of FIG. 1A. Exemplary timing diagrams for each of the exemplary wakeup procedures that enable the above described time and power savings are provided below in connection with FIGs.5A-5C. [0048] FIG. 5A illustrates a first exemplary timing diagram 500 for waking up baseband chip 402 in the lead up to an active period of a DRX cycle, according to some embodiments of the present disclosure. FIG. 5B illustrates a second exemplary timing diagram 525 for waking up baseband chip 402 in the lead up to an active period of a DRX cycle, according to some embodiments of the present disclosure. FIG. 5C illustrates a third exemplary timing diagram 550 for waking up baseband chip 402 in the lead up to an active period of a DRX cycle, according to some embodiments of the present disclosure. FIGs.5A-5C will be described together. [0049] The exemplary timing diagrams 500, 525, 550 are depicted in relation to the inactive period 501 and the active period 503 of a DRX cycle. During inactive period 501, the UE is not expected to monitor the PDCCH for incoming DL data, while the UE is expected to monitor the PDCCH for incoming DL data during active period 503. Moreover, inactive period 501 may include a deep-sleep state (e.g., power-off period in which main crystal and baseband components are powered off) and a wake-up state (e.g., power-up period, boot-up period, etc.) for each of the baseband components. The length of the deep-sleep state and the wake-up state for a baseband component may depend on the order in which it is activated/woken up during the exemplary wake- up procedure. [0050] For example, referring to FIG.5A, the deep-sleep state of SoC bus 430 occurs from t ₀ to t ₁ , while its wake-up state is from t ₁ to t ₂ ; the deep-sleep state of DDR controller 440 occurs from t ₀ to t ₂ , while its wake-up state is from t ₂ to t ₃ ; the deep-sleep state of PHY controller 450 occurs from t ₀ to t ₃ , while its wake-up state is from t ₃ to t ₄ ; the deep-sleep state of RF/BB-interface 460 occurs from t ₀ to t _3, while its wake-up state is from t ₃ to t ₆ ; and the deep-sleep state of signal processing component(s) 470 occurs from t ₀ to t ₅ , while its wake-up state is from t ₅ to t ₆ . [0051] Referring to FIG.5B, the deep-sleep state of SoC bus 430 occurs from t ₀ to t ₁ , while its wake-up state is from t ₁ to t ₂ ; the deep-sleep state of DDR controller 440 occurs from t ₀ to t ₂ , while its wake-up state is from t ₂ to t ₃ ; the deep-sleep state of PHY controller 450 occurs from t ₀ to t ₃ , while its wake-up state is from t ₃ to t ₄ ; the deep-sleep state of an analog circuit 530 of RF/BB- interface 460 occurs from t ₀ to t ₃ , while its wake-up state is from t ₃ to t ₅ ; the deep-sleep state of a digital circuit 520 of RF/BB-interface 460 is from t ₀ to t ₄ , while its wake-up period is from t ₄ to t ₅ ; and the deep-sleep state of signal processing component(s) 470 occurs from t ₀ to t ₄ , while its wake- up state is from t ₄ to t ₅ . [0052] Referring to FIG.5C, the deep-sleep state of SoC bus 430 occurs from t ₀ to t ₁ , while its wake-up state is from t ₁ to t ₂ ; the deep-sleep state of DDR controller 440 occurs from t ₀ to t ₂ , while its wake-up state is from t ₂ to t ₃ ; the deep-sleep state of PHY controller 450 occurs from t ₀ to t ₃ , while its wake-up state is from t ₃ to t ₅ , with a power-up period in which a PHY bootloader is activated from t ₃ to t ₄ and a boot-up period of the actual PHY controller 450 by the bootloader from t ₄ to t ₅ ; the deep-sleep state of RF/BB-interface 460 occurs from t ₀ to t ₄ , while its wake-up state is from t ₄ to t ₆ ; and the deep-sleep state of signal processing component(s) 470 occurs from t ₀ to t ₅ , while its wake-up state is from t ₅ to t ₆ . [0053] Turning to exemplary wake-up sequence of FIG. 5A, to begin, AON 420 (which remains powered on during inactive period 501) activates SoC bus 430 at t ₁ . SoC bus 430 may be activated first to facilitate communication between other baseband components during the exemplary wake-up procedure. Once SoC bus 430 is up and running, AON 420 may activate DDR controller 440 at t ₂ . AON 420 may concurrently activate PHY controller 450 and RF/BB-interface 460 at t ₃ . The PHY controller bootloader (also referred to herein as “PHY bootloader”) may be activated first during this period; and once activated, the PHY bootloader may communicate with DDR controller 440 so that the data and/or software codes maintained in external memory 408 (e.g., a DDR chip) can be accessed by the PHY bootloader, which it uses to activate PHY controller 450. PHY controller 450 is fully up and running at t ₄ , and it activates signal processing component(s) 470 at t ₅ . Thus, RF/BB-interface 460 and signal processing component(s) 470 may be ready at the start of active period 503 so that an incoming DL signal can be received at t ₆ . In that sense, AON 420 may sequentially activate a first subset of baseband components (e.g., SoC bus 430 and DDR controller 440) during a first time period (e.g., t ₀ to t ₃ ) and may concurrently activate a second subset of baseband components (e.g., PHY controller 450 and RF/BB-interface 460) during a second time period (e.g., t ₃ to t ₆ ). PHY controller 450 activates signal processing component(s) 470 during a third time period (e.g., t ₅ to t ₆ ) that overlaps with the second time period (e.g., t ₃ to t ₆ ). By concurrently activating PHY controller 450 and RF/BB-interface 460 using AON 420, the deep-sleep state of each of SoC bus 430, DDR controller 440, and PHY controller 450 can be extended, as compared to those components of FIG.1A. In so doing, the collective duration of the wake-up period, and hence, the power consumption during inactive period 501 of the DRX cycle depicted in FIG. 5A may be reduced, as compared to other baseband chips. In that sense, t ₁ in FIG.5A may occur later in the inactive period 501 than does t ₁ in the active period 101 of FIG. 1B. [0054] Referring to the exemplary wake-up sequence of FIG. 5B, AON 420 may first activate SoC bus 430 at time t ₁ so that it is up and running by t ₂ . Then, at t ₂ , AON 420 may activate DDR controller 440, which is up and running by t ₃ . In this embodiment, AON 420 may concurrently activate PHY controller 450 and the analog circuit 530 of RF/BB-interface 460 at t ₃ . Analog circuit 530 may have a longer warm-up and/or settling time than digital circuit 520, and hence, analog circuit 530 may be activated first. Analog circuit 530 may be configured using settings maintained in the retention storage of digital circuit 520 during a previous active period of a previous DRX cycle. AON 420 may activate digital circuit 520 of RF/BB-interface 460 at time t ₄ , which may be the same time at which PHY controller 450 activates signal processing component(s) 470 so that it is ready along with RF/BB-interface 460 at t ₅ . Thus, RF/BB-interface 460 and signal processing component(s) 470 may be ready at the start of active period 503 so that a DL signal can be received if sent by the base station at t ₅ . In that sense, AON 420 may sequentially activate a first subset of baseband components (e.g., SoC bus 430 and DDR controller 440) during a first time period (e.g., t ₀ to t ₃ ) and may concurrently activate a second subset of baseband components (e.g., PHY controller 450 and analog circuit 530 RF/BB-interface 460) during a second time period (e.g., t ₃ to t ₅ ). AON 420 activates digital circuit 520 of RF/BB- interface 460, and PHY controller 450 activates signal processing component(s) 470 during a third time period (e.g., t ₄ to t ₅ ) that overlaps with the second time period (e.g., t ₃ to t ₅ ). In so doing, the collective duration of the wake-up period, and hence, the power consumption during inactive period 501 of the DRX cycle depicted in FIG.5B may be reduced, as compared to other baseband chips. In that sense, t ₁ in FIG. 5B may occur later in the inactive period 501 than does t ₁ in the active period 101 of FIG.1B. [0055] Turning to the exemplary wake-up sequence of FIG. 5C, AON 420 may first activate SoC bus 430 at time t ₁ so that it is up and running by t ₂ . Then, at t ₂ , AON 420 may activate DDR controller 440, which is up and running by t ₃ . At t ₃ , AON 420 may activate the bootloader of PHY controller 450 at t ₃ so that it is up and running by t ₄ . The bootloader may then concurrently activate PHY controller 450 and RF/BB-interface 460. PHY controller 450 may be ready by t ₅ , while RF/BB-interface 460 may be up and running by t ₆ . At t ₅ , PHY controller 450 may activate signal processing component(s) 470 at t ₅ so that it along with RF/BB-interface 460 are both ready by t ₆ , which is the start of active period 503. In that sense, AON 420 may sequentially activate a first subset of baseband components (e.g., SoC bus 430, DDR controller 440, and the bootloader of PHY controller 450) during a first time period (e.g., t ₀ to t ₄ ), and the bootloader of PHY controller 450 may concurrently activate a second subset of baseband components (e.g., PHY controller 450 and RF/BB-interface 460) during a second time period (e.g., t ₄ to t ₆ ). In so doing, the collective duration of the wake-up period, and hence, the power consumption during inactive period 501 of the DRX cycle depicted in FIG.5C may be reduced, as compared to other baseband chips. In that sense, t ₁ in FIG. 5C may occur later in the inactive period 501 than does t ₁ in the active period 101 of FIG.1B. [0056] FIG. 6 illustrates a flowchart of a first exemplary method 600 of wireless communication, according to embodiments of the disclosure. Exemplary method 600 may be performed by an apparatus for wireless communication, e.g., such as a user equipment, a node, an apparatus, a baseband chip, an AON, an SoC bus, a DDR controller, a PHY controller, a bootloader of a PHY controller, an RF/BB-interface, and/or signal processing component(s). Method 600 may include steps 602-606 as described below. [0057] Referring to FIG. 6, at 602, the apparatus may enter an inactive state at the start of an inactive period of a DRX cycle. For example, referring to FIGs.5A and 5B, SoC bus 430, DDR controller 440, PHY controller 450, RF/BB-interface 460, and/or signal processing component(s) 470 may be powered down along with the primary crystal of baseband chip 402 at t ₀ , which is the start of inactive period 501 of the DRX cycle. [0058] At 604, the apparatus may sequentially activate, by an always-on component, a first subset of the plurality of baseband components during a first portion of an inactive period of the DRX cycle. For example, referring to FIGs.5A and 5B, AON 420 may sequentially activate a first subset of baseband components (e.g., SoC bus 430 and DDR controller 440) during a first time period (e.g., t ₀ to t ₃ ), as described above in more detail. [0059] At 606, the apparatus may concurrently activate, by the always-on component, a second subset of the plurality of baseband components during a second portion of the DRX cycle following the first portion. For example, referring to FIG. 5A, the AON 420 may concurrently activate a second subset of baseband components (e.g., PHY controller 450 and RF/BB-interface 460) during a second time period (e.g., t ₃ to t ₆ ), as described above. In another example, referring to FIG. 5B, AON 420 may concurrently activate a second subset of baseband components (e.g., PHY controller 450 and analog circuit 530 RF/BB-interface 460) during a second time period (e.g., t ₃ to t ₅ ). [0060] FIG. 7 illustrates a flowchart of a second exemplary method 700 of wireless communication, according to embodiments of the disclosure. Exemplary method 700 may be performed by an apparatus for wireless communication, e.g., such as a user equipment, a node, an apparatus, a baseband chip, an AON, an SoC bus, a DDR controller, a PHY controller, a bootloader of a PHY controller, an RF/BB-interface, and/or signal processing component(s). Method 700 may include steps 702-706 as described below. [0061] Referring to FIG. 7, at 702, the apparatus may enter an inactive state at the start of an inactive period of a DRX cycle. For example, referring to FIGs.5A and 5B, SoC bus 430, DDR controller 440, PHY controller 450, RF/BB-interface 460, and/or signal processing component(s) 470 may be powered down along with the primary crystal of baseband chip 402 at t ₀ , which is the start of inactive period 501 of the DRX cycle. [0062] At 704, the apparatus may sequentially activate, by an always-on component, a first subset of the plurality of baseband components that includes a PHY bootloader during a first portion of an inactive period of the DRX cycle. For example, referring to FIG.5C, AON 420 may sequentially activate a first subset of baseband components (e.g., SoC bus 430, DDR controller 440, and the bootloader of PHY controller 450) during a first time period (e.g., t ₀ to t ₄ ), as described above. [0063] At 706, the apparatus may concurrently activate, by a PHY controller bootloader, a second subset of the plurality of baseband components during a second portion of the DRX cycle following the first portion. For example, referring to FIG. 5C, the bootloader of PHY controller 450 may concurrently activate a second subset of baseband components (e.g., PHY controller 450 and RF/BB-interface 460) during a second time period (e.g., t ₄ to t ₆ ), as described above. [0064] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or encoded as instructions or code on a non-transitory computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computing device, such as node 300 in FIG. 3. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, HDD, such as magnetic disk storage or other magnetic storage devices, Flash drive, SSD, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system, such as a mobile device or a computer. Disk and disc, as used herein, includes CD, laser disc, optical disc, digital video disc (DVD), and floppy disk where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. [0065] According to one aspect of the present disclosure, a first exemplary baseband chip is provided. The baseband chip may include a plurality of baseband components configured to enter an inactive state at a start of an inactive period of a DRX cycle. The baseband chip may include an always-on component. The always-on component may be configured to remain in an active state during the inactive period of the DRX cycle. The always-on component may be configured to sequentially activate a first subset of the plurality of baseband components during a first portion of the inactive period of the DRX cycle. The always-on component may be configured to concurrently activate a second subset of the plurality of baseband components during a second portion of the DRX cycle following the first portion. [0066] In some embodiments, to sequentially activate the first subset of the plurality of baseband components during the first portion of the DRX cycle, the always-on component may be configured to activate a bus interconnect. In some embodiments, to sequentially activate the first subset of the plurality of baseband components during the first portion of the DRX cycle, the always-on component may be configured to activate a DDR controller after the bus interconnect. [0067] In some embodiments, to concurrently activate the second subset of the plurality of baseband components during the second portion of the inactive period of the DRX cycle, the always-on component is configured to concurrently activate a PHY controller and at least one circuit of an RF chip/BB-interface at a start of the second portion of the inactive period of the DRX cycle. In some embodiments, the start of the second portion of the inactive period may coincide with an end of the first portion of the inactive period. In some embodiments, the at least one circuit of the RF/BB-interface may include one or more of an analog circuit of the RF/BB-interface or a digital circuit of the RF/BB-interface. [0068] In some embodiments, PHY controller may be configured to activate at least one signal processing component during a third portion of the inactive period that overlaps with the second portion and begins after a start of the second portion of the inactive period. [0069] In some embodiments, the RF/BB-interface and the at least one signal processing component may be ready to receive a downlink transmission from an RF chip at a same time that coincides with a start of an active period of the DRX cycle. [0070] In some embodiments, the PHY controller and the analog circuit of the RF/BB- interface may be concurrently activated. In some embodiments, the always-on component may be further configured to configure the RF/BB-interface analog circuit based on one or more settings maintained in a retention storage of the digital circuit of the RF/BB-interface. In some embodiments, the one or more settings may be maintained in the retention storage of the digital circuit of the RF/BB-interface during a previous active period of a previous DRX cycle. [0071] In some embodiments, the PHY controller may be configured to activate the digital circuit of the RF/BB-interface during a fourth portion of the inactive period of the DRX cycle following the second portion and before the third portion. [0072] According to another aspect of the disclosure, a second exemplary baseband chip is provided. The baseband chip may include a plurality of baseband components configured to enter an inactive state at a start of an inactive period of a DRX cycle. The baseband chip may include an always-on component. The always-on component may be configured to remain in an active state during the inactive period of the DRX cycle. The always-on component may be configured to sequentially activate a first subset of the plurality of baseband components during a first portion of the inactive period of the DRX cycle. The baseband chip may include a PHY controller bootloader configured to concurrently activate a second subset of the plurality of baseband components during a second portion of the DRX cycle following the first portion. In some embodiments, the PHY controller bootloader may be part of the first subset of the plurality of baseband components sequentially activated by the always-on component during the first portion of the inactive period of the DRX cycle. [0073] In some embodiments, to sequentially activate the first subset of the plurality of baseband components during the first portion of the DRX cycle, the always-on component may be configured to activate a bus interconnect. In some embodiments, to sequentially activate the first subset of the plurality of baseband components during the first portion of the DRX cycle, the always-on component may be configured to activate a DDR controller after the bus interconnect. In some embodiments, to sequentially activate the first subset of the plurality of baseband components during the first portion of the DRX cycle, the always-on component may be configured to activate the PHY controller bootloader during a third portion of the inactive period following the second portion. [0074] In some embodiments, to concurrently activate the second subset of the plurality of baseband components during the second portion of the inactive period of the DRX cycle, the PHY controller bootloader is configured to concurrently boot a PHY controller and activate at least one circuit of an RF/BB-interface at a start of the second portion of the inactive period of the DRX cycle. In some embodiments, the start of the second portion of the inactive period may coincide with an end of the first portion of the inactive period. In some embodiments, the at least one circuit of the RF/BB-interface may include one or more of an analog circuit of the RF/BB-interface or a digital circuit of the RF/BB-interface. [0075] In some embodiments, the PHY controller may be configured to activate at least one signal processing component during a third portion of the inactive period that overlaps with the second portion and begins after a start of the second portion of the inactive period. [0076] In some embodiments, the RF/BB-interface and the at least one signal processing component may be ready to receive a downlink transmission from an RF chip at a same time that coincides with a start of an active period of the DRX cycle. [0077] In some embodiments, the PHY controller bootloader and the analog circuit of the RF/BB-interface may be concurrently activated. In some embodiments, the always-on component may be further configured to configure the analog circuit of the RF/BB-interface based on one or more settings maintained in a retention storage of the digital circuit of the RF/BB-interface. In some embodiments, the one or more settings may be maintained in the retention storage of the digital circuit of the RF/BB-interface during a previous active period of a previous DRX cycle. [0078] According to yet another aspect of the present disclosure, a method of wireless communication of a baseband chip is provided. The method may include entering, by a plurality of baseband components, an inactive state at a start of an inactive period of a DRX cycle. The method may include remaining, by an always-on component, in an active state during the inactive period of the DRX cycle. The method may include sequentially activating, by the always-on component, a first subset of the plurality of baseband components during a first portion of the inactive period of the DRX cycle. The method may include concurrently activating, by the always- on component, a second subset of the plurality of baseband components during a second portion of the DRX cycle following the first portion. [0079] In some embodiments, the sequentially activating the first subset of the plurality of baseband components during the first portion of the DRX cycle may include activating, by the always-on component, a bus interconnect. In some embodiments, the sequentially activating the first subset of the plurality of baseband components during the first portion of the DRX cycle may include activating, by the always-on component, a double data rate (DDR) controller after the bus interconnect. [0080] In some embodiments, the concurrently activating the second subset of the plurality of baseband components during the second portion of the inactive period of the DRX cycle may include concurrently activating, by the always-on component, a PHY controller and at least one circuit of an RF/BB-interface at a start of the second portion of the inactive period of the DRX cycle. In some embodiments, the start of the second portion of the inactive period may coincide with an end of the first portion of the inactive period. In some embodiments, the at least one circuit of the RF/BB-interface may include one or more of an analog circuit of the RF/BB-interface or a digital circuit of the RF/BB-interface. [0081] In some embodiments, the method may include activating, by the PHY controller, at least one signal processing component during a third portion of the inactive period that overlaps with the second portion and begins after a start of the second portion of the inactive period. [0082] In some embodiments, the RF/BB-interface and the at least one signal processing component may be ready to receive a downlink transmission from an RF chip at a same time that coincides with a start of an active period of the DRX cycle. [0083] In some embodiments, the PHY controller and the analog circuit of the RF/BB- interface may be concurrently activated. In some embodiments, the method may include configuring, by the always-on component, the analog circuit of the RF/BB-interface based on one or more settings maintained in a retention storage of the digital circuit of the RF/BB-interface. In some embodiments, the one or more settings may be maintained in the retention storage of the digital circuit of the RF/BB-interface during a previous active period of a previous DRX cycle. [0084] In some embodiments, the method may include activating, by the PHY controller, the digital circuit of the RF/BB-interface during a fourth portion of the inactive period of the DRX cycle following the second portion and before the third portion. [0085] The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance. [0086] Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. [0087] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way. [0088] Various functional blocks, modules, and steps are disclosed above. The particular arrangements provided are illustrative and without limitation. Accordingly, the functional blocks, modules, and steps may be re-ordered or combined in different ways than in the examples provided above. Likewise, certain embodiments include only a subset of the functional blocks, modules, and steps, and any such subset is permitted. The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.