Title:
APPARATUS AND METHOD FOR CHANNEL ENCODING/DECODING IN COMMUNICATION OR BROADCASTING SYSTEM
Document Type and Number:
WIPO Patent Application WO/2018/182371
Kind Code:
A1
Abstract:
A method for channel encoding in a communication or broadcasting system is provided. The method includes determining a block size Z, and performing encoding based on the block size and a parity check matrix corresponding to the block size, wherein the parity check matrix is determined based on a base matrix and a plurality of circulant permutation matrices, and wherein a part of a column index indicating a position of a non-zero element in each row of the base matrix includes an index according to mathematical expression 22 above.
Inventors:
KIM KYUNGJOONG (KR)
MYUNG SEHO (KR)
AHN SEOKKI (KR)
JEONG HONGSIL (KR)
JANG MIN (KR)
MYUNG SEHO (KR)
AHN SEOKKI (KR)
JEONG HONGSIL (KR)
JANG MIN (KR)
Application Number:
PCT/KR2018/003808
Publication Date:
October 04, 2018
Filing Date:
March 30, 2018
Export Citation:
Assignee:
SAMSUNG ELECTRONICS CO LTD (KR)
International Classes:
H03M13/11; H03M13/00; H03M13/29; H04L1/00
Foreign References:
| CN102185615A | 2011-09-14 | |||
| KR20080035585A | 2008-04-23 |
Other References:
SANGMIN KIM ET AL.: "Flexible LDPC decoder architecture for high-throughput applications", APCCAS 2008 - 2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, 2008, Macao, pages 45 - 48, XP031404929, Retrieved from the Internet
VIKRAM ARKALGUD CHANDRASETTY ET AL.: "A Highly Flexible LDPC Decoder using Hierarchical Quasi-Cyclic Matrix with Layered Permutation", JOURNAL OF NETWORKS, vol. 7, no. 3, March 2012 (2012-03-01), pages 441 - 449, XP055624842, Retrieved from the Internet
MARJAN KARKOOTI ET AL.: "Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation", IEEE 17TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP'06), September 2006 (2006-09-01), pages 360 - 367, XP031021386, Retrieved from the Internet
VIKRAM ARKALGUD CHANDRASETTY ET AL.: "A Highly Flexible LDPC Decoder using Hierarchical Quasi-Cyclic Matrix with Layered Permutation", JOURNAL OF NETWORKS, vol. 7, no. 3, March 2012 (2012-03-01), pages 441 - 449, XP055624842, Retrieved from the Internet
MARJAN KARKOOTI ET AL.: "Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation", IEEE 17TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP'06), September 2006 (2006-09-01), pages 360 - 367, XP031021386, Retrieved from the Internet
Attorney, Agent or Firm:
YOON & LEE INTERNATIONAL PATENT & LAW FIRM (KR)
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