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Title:
APPARATUS AND METHOD FOR DC OFFSET COMPENSATION IN A DIRECT CONVERSION RECEIVER
Document Type and Number:
WIPO Patent Application WO2004021589
Kind Code:
A9
Abstract:
An apparatus for coarse compensation of a direct current (DC) offset in a direct to baseband receiver architecture utilizes a serial analog to digital converter (ADC), such as a Delta-Sigma converter, to convert the received signal to digital form. The output of the ADC is sampled for a predetermined number of samples and a counter coupled to the ADC is incremented each time the sample generated by the ADC is a logic one. The counter is not incremented if the sample from the ADC is a logic zero. After the predetermined number of samples is obtained, the counter value is indicative of the DC offset in the received signal. The counter value may be converted by a code converter to a correction value for easy operation of a digital to analog converter (DAC). If the number of samples from the ADC is a power of two, the code converted may be readily implemented by simply inverting the most significant bit (MSB) from the counter to thereby generate a twos complement version of the counter value. The correction value is coupled to the DAC to generate a compensation signal, which is provided to the received signal path in the form of a feedback signal to compensate for the DC offset.

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Inventors:
SCHLEGEL NIKOLAI
HOLENSTEIN CHRISTIAN
FILIPOVIC DANIEL
KASTURI NITIN
Application Number:
PCT/US2003/027016
Publication Date:
May 06, 2004
Filing Date:
August 28, 2003
Export Citation:
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Assignee:
QUALCOMM INC (US)
International Classes:
H03D3/00; H04B1/30; H04L25/06; (IPC1-7): H04B1/30; H04L25/06
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