The present invention relates to an apparatus for and method of digital signal processing-

In the specification, the following abbreviations are employed:-

DFT : Discrete Fourier Transform DSP : Digital Signal Processing

FDM : Frequency Division Multiplex

FIR : Finite Impulse Response

IDFT : Inverse Discrete Fourier Transform

An existing digital signal processing apparatus comprises a conventional critically sampled, uniform DFT filter bank design which features a two stage channel filtering process. A coarse filtering function is performed in a block processing stage combined with a DFT, which has the effect of sharing a single lowpass FIR prototype filter between all the channels. This lowpass prototype filter has double sided passband width and each transition band width equal to the channel or sub-band width. The total channel filtering function is completed by processing each channel separately with a second

^• lowpass sharpening filter with narrow transition

bands of width equal to the channel guard band. This process requires a bank of such identical filters, one per channel.

According to one aspect of the present invention, there is provided apparatus for digital signal processing comprising a demultiplexer having a FIR filter structure with a Hubert transform frequency response, a polyphase filter network disposed to accept the output of the filter structure and a DFT disposed to accept the output of the filter network.

According to another aspect of the present invention, there is provided apparatus for digital signal processing comprising a multiplexer having an IDFT, a polyphase filter network disposed to accept the output of the IDFT and a filter structure with a Hubert transform frequency response disposed to accept the output of the filter network.

Where the input to the demultiplexer is complex rather than real, an interpolate by 2 circuit is arranged before the FIR filter structure.

Where the output from the multiplexer is complex rather than real, a decimate by 2 circuit is disposed at the output side of the FIR filter structure.

According to a further aspect of the present invention there is provided a method of digital signal processing including the steps of preparing a form of analytic signal by means of a Hubert transform network and feeding this signal as input to a DFT filter bank demultiplexer.

According to a still further aspect of the present invention, there is provided a method of digital signal processing including the steps of feeding a signal to a DFT filter bank multiplexer and processing the output from the multiplexer by means of a Hubert transform network to create a form of analytic signal.

In a preferred embodiment of the invention, the principal processing stages which comprise the demultiplexer and multiplexer architectures are the following:

An N-tap FIR digital filter, with K-l zero valued samples inserted between each original coefficient, where. K is the DFT transform size and is the number of channels or sub-bands into which the FDM is resolved. The coefficients of this filter are those of a Class 3 lowpass Hubert transform design (N odd) for a sampling frequency of f _n /K Hz where f _Q Hz is

the FDM sampling frequency. The effect of the interpolated impulse response is to give an imaged frequency response across the sampled bandwidth from - f _Q /2 to f _Q /2 Hz. The transition bandwidth of the prototype class 3 Hubert transform design (and hence the length N) is determined by the channel guard band. The interpolated filter is obtained from the original implementation by replacing each delay with K delays.

A delay stage with K(N-1)/2.samples delay at the FDM sampling rate.

A polyphase filter network, with K branch filters, which features a decimation of 2K. The prototype filter for this polyphase branch network is the coarse lowpass filter design of the block-DFT stage.

A K-point, complex-complex, DFT/IDFT Processor.

In order that the invention may be more clearly understood, embodiments thereof will now be described, by way of example, with reference to the accompanying drawings, in which:-

Figure 1 shows a block circuit diagram of one form of demultiplexer architecture according to the

invention for a real FDM input,

Figure 2 shows a block circuit diagram of one form of multiplexer architectrue according to the invention for a real FDM output,

Figure 3 shows a block circuit diagram of one form of demultiplexer architecture for a complex FDM input, and

Figure 4 shows a block circuit diagram of one form of multiplexer architecture for a complex FD output.

Referring to Figure 1, demultiplexer architecture for a demultiplexer of a real FDM is shown. The real input is copied into two parallel paths 1 and 2. The lower path 1 is filtered in the interpolated FIR filter structure 3 which has an imaged Hubert transform frequency response. The upper path 2 comprises a delay stage 4 which serves to delay by the number of samples equal to the processing delay in the filter 3. The input FDM samples are real, and the signal is critically sampled at a rate f _Q - 2KB Hz, where B is the width of the channel or sub-band and K is the number of distinct, contiguous, equally spaced channels or sub-bands. The K channels occupy the frequency range

• 0 to f _n /2 Hz, with their complex conjugates in the range O to ^_ ₀ /2 Hz. K is arbitrary and depends on - the application.

The channels are arranged in an odd stacking scheme, with the positive frequency channels centred at frequencies f _k = (2k+l) f _Q /4K Hz, k = 0,...,K-1. The complex conjugates are centred at frequencies

-(2k+l)f ₀ /4K Hz.

The demultiplexer extracts the complex envelopes, critically sampled and centred at zero frequency, of the even index channels (k = 0,2,...) and the complex conjugates of the complex envelopes, critically sampled and centred at zero frequency, of the odd index channels k = 1,3,...

The demultiplexer features decimation by the factor 2K between the input FDM and the output channels. The upper and lower branch output signals at 5 and 6 are regarded as the real and imaginary parts, respectively, of a form of analytic signal representation of the input FDM, in which bands of width f _Q /2K Hz centred at frequencies +(2k+l)f _Q /4K Hz, with k odd, have zero signal energy (in practice the level of attenuation is determined by the specification on the Hubert transform prototype) . Similarly bands of width f _Q / K Hz and centred at

frequencies -(2k+l)f _Q /4K Hz, with k even also have zero signal energy.

The complex signal output from the front-end processing is passed into a polyphase filter network 7. Since the channel stacking is odd, it is necessary to use a generalised DFT with offset frequency origin. The branch outputs from network 7 are processed in a generalised DFT processor 8 to resolve the signal into its K channels. The polyphase branch filters and the DFT processor are run at the decimated sampling rate of f _Q /2K Hz, which is also the sampling rate of each of the K outputs.

Referring to Figure 2, the architecture for a multiplexer to create a real FDM output is shown.

The multiplexer architecture to generate a critically sampled real FDM from K critical sampled complex inputs is essentially the transpose of the demultiplexer shown in Figure 1.

It comprises a generalised IDFT 10 feeding a polyphase filter network 11 which in turn feeds a parallel arrangement of a delay stage 12 and a FIR filter structure 13 which has an imaged Hilber transform frequency response.

The complex signal at the output of the polyphase branch interpolator is processed in the Hubert transform structure 13. The real part of the signal is delayed in the delay stage 12, and the imaginary part is passed through the filter structure 13, with the imaged Hubert transform frequency response. The real and imaginary outputs are differenced to create the real output FDM at sampling frequency f _π Hz. The total interpolation factor is therefore ZK.

Referring to Figure 3, the demultiplexer architecture is similar to that of Figure 1 in that a parallel arrangement of a delay stage 20 and FIR Hubert transform structure 21 feed a polyphase filter network 22 which in turn feeds a DFT processor 23. In addition, however, an interpolate by 2 circuit 24 is disposed prior to the parallel arrangement of the delay stage 20 and the Hubert transform structure 21.

The input FDM samples are complex, and the signal is critically sampled at a rate f _Q = KB Hz, where B is the width of the channel or sub-band and K is the number of distinct, contiguous, equally spaced channels or sub-bands. ^' The K channels occupy the frequency range ~f _n /2 to f _Q /2 Hz. K is arbitrary and

depends on the application.

The channels are arranged in an even stacking scheme, with the k=0 channel centred at zero frequency. The total number of channels K must be odd. The demultiplexer extracts the complex envelopes, critically sampled and centred at zero frequency, of the K channels. The demultiplexer features decimation by the factor K between the input FDM and the output channels.

The interpolate by 2 circuit 24 interpolates the complex input by the factor 2 (by inserting a complex zero sample between each input sample) prior to processing in the front-end Hubert transform structure 21. The lowpass FIR Hubert transform prototype of length N is modulated by the complex exponential factor exp(-jnJ/2) = (-j) ,n=0, ... ,N-1. The output of the Hubert transform path is explicity multiplied by j and added to the upper path signal. The complex signal is then passed into the polyphase branch filter network 22. In this case, because even stacking is assumed, the real lowpass prototype filter can be used directly with a conventional DFT. he K-point DFT transform 23 completes the resolution of the signal into its K constituent channels.

Referring to Figure 4, the architecture for a

ultiplexer to create a complex FDM output is shown.

The multiplexer architecture to generate a critically sampled complex FDM from K critically sampled complex inputs is essentially the transpose ^* of the demultiplexer shown in Figure 3. It comprises an IDFT 30 feeding a polyphase filter network 31 which in turn feeds a parallel arrangement of a delay stage 32 and a FIR filter structure 33 which has an imaged Hubert transform frequency response. The output from that parallel arrangement passes to a decimate by 2 circuit 34 and then to the output.

The complex signal at the output of the polyphase filter network 31 is processed in the Hubert transform structure 33. One copy of the complex signal is delayed in the delay stage 32, and the other copy is passed through the filter structure 33 with the imaged Hubert transform frequency response. The filtered output is explicitly multiplied by j and added to the upper branch signal from the delay stage to create the complex ouptut which is then decimated by 2 to give the desired critically sampled FDM.

In the architecture of the above described embodiments, the use of the Hubert transform network

has two advantages. The first is that the Hubert transform network is used to generate a form of analytic signal representation of the FDM which eliminates the need for a bank of second sharpening filters, resulting in a simpler and more compact design. The second is that, as a consequence of the fact that the second sharpening filter is eliminated, it is possible to run the block filter and DFT stage at half the sampling rate of the conventional equivalent, resulting in a saving in computational complexity. The consequent reduction in multiplexing steps leads to a reduction in power consumptions which is very important in certain applications such as in satellites.

It will be appreciated that the above embodiments have been described by way of example only and that many variations are possible without departing from the scope of the invention.