APPARATUS AND METHOD FOR DRIVING A DIGITAL-TO-ANALOG CONVERTER, AND APPARATUSES AND METHODS FOR GENERATING A RADIO

FREQUENCY SIGNAU

Field

The present disclosure relates to Radio Frequency (RF) transmitters. In particular, examples relate to an apparatus and a method for driving a Digital-to-Analog Converter (DAC), and apparatuses and methods for generating a RF signal.

Background

Quadrature modulation and polar modulation both have a variety of advantages and disad vantages. For example, polar architecture exhibits reduced RF-DAC size requirements und superior RF-DAC power efficiency compared to quadrature modulation. On the other hand, quadrature (IQ) modulation enables less complex Digital-FrontEnd (DFE) design. While a transmitter benefits from the advantages of one specific modulation technique, the disad vantages of the modulation technique need to be accepted at the same time. Hence, there may be a desire for an improved modulation technique.

Brief description of the Figures

Some examples of apparatuses and/or methods will be described in the following by way of example only, and with reference to the accompanying figures, in which

Fig. 1 illustrates an example of an apparatus for driving a DAC;

Figs. 2 to 4 illustrate examples of constellation diagrams;

Fig. 5 illustrates another example of an apparatus for driving a DAC;

Fig. 6 illustrates a further example of an apparatus for driving a DAC; Fig. 7 illustrates an example of a transmitter comprising an apparatus for driving a DAC;

Fig. 8 illustrates an example of an approximation of a complex trajectory;

Fig. 9 illustrates an example of a quadrature signal;

Fig. 10 illustrates an example of a phase signal;

Fig. 11 illustrates an example of a relation between a power conversion efficiency and a pre determined value range for a phase shift value;

Fig. 12 illustrates an example of a relation between an average DAC cell utilization and a predetermined value range for a phase shift value;

Fig. 13 illustrates an example of a relation between a peak DAC cell utilization and a prede termined value range for a phase shift value;

Fig. 14 illustrates an example of a course of an in-phase component;

Figs. 15 and 17 illustrate an example of a course of a phase modification value;

Fig. 16 illustrates an example of a course of a quadrature component;

Fig. 18 illustrates another example of an apparatus for driving a DAC;

Fig. 19 illustrates a further example of an apparatus for driving a DAC;

Fig. 20 illustrates another example of an approximation of a complex trajectory;

Fig. 21 illustrates an exemplary comparison of power- spectral-densities;

Fig. 22 illustrates an example of a CORDIC micro rotation permutation tree;

Figs. 23 and 24 illustrate examples of constellation diagrams; Fig. 25 illustrates another example of an apparatus for driving a DAC;

Fig. 26 illustrates another example of an approximation of a complex trajectory;

Fig. 27 illustrates exemplary signal courses;

Fig. 28 illustrates an exemplary comparison of error vector magnitudes;

Fig. 29 illustrates an example of a mobile device comprising an apparatus for driving a DAC; Fig. 30 illustrates a flowchart of an example of a method for driving a DAC;

Fig. 31 illustrates an example of an apparatus for generating a RF signal;

Fig. 32 illustrates another example of an apparatus for generating a RF signal;

Fig. 33 illustrates a flowchart of an example of a method for generating a RF signal;

Fig. 34 illustrates a further example of an apparatus for generating a RF signal;

Figs. 35 to 37 illustrate exemplary phase changes in a modulator;

Fig. 38 illustrates an example of a mobile device comprising an apparatus for generating a RF signal;

Fig. 39 illustrates a flowchart of an example of a method for generating a RF signal;

Fig. 40 illustrates a flowchart of another example of a method for generating a RF signal; Fig. 41 illustrates an example of another apparatus for generating a RF signal;

Fig. 42 illustrates another example of a constellation diagram; Fig. 43 illustrates another example of an apparatus for generating a RF signal;

Fig. 44 illustrates an example of a processing circuit;

Fig. 45 illustrates another example of an approximation of a complex trajectory;

Fig. 46 illustrates an example of an amplitude signal;

Fig. 47 illustrates an example of a phase signal;

Fig. 48 illustrates examples of in-phase and quadrature signals;

Fig. 49 illustrates an example of a mobile device comprising an apparatus for generating a RF signal; and

Fig. 50 illustrates a flowchart of an example of a method for generating a RF signal.

Detailed Description

Various examples will now be described more fully with reference to the accompanying draw ings in which some examples are illustrated. In the figures, the thicknesses of lines, layers and/or regions may be exaggerated for clarity.

Accordingly, while further examples are capable of various modifications and alternative forms, some particular examples thereof are shown in the figures and will subsequently be described in detail. However, this detailed description does not limit further examples to the particular forms described. Further examples may cover all modifications, equivalents, and alternatives falling within the scope of the disclosure. Like numbers refer to like or similar elements throughout the description of the figures, which may be implemented identically or in modified form when compared to one another while providing for the same or a similar functionality.

It will be understood that when an element is referred to as being“connected” or“coupled” to another element, the elements may be directly connected or coupled or via one or more intervening elements. If two elements A and B are combined using an“or”, this is to be un derstood to disclose all possible combinations, i.e. only A, only B as well as A and B. An alternative wording for the same combinations is“at least one of A and B”. The same applies for combinations of more than 2 Elements.

The terminology used herein for the purpose of describing particular examples is not intended to be limiting for further examples. Whenever a singular form such as“a,”“an” and“the” is used and using only a single element is neither explicitly or implicitly defined as being man datory, further examples may also use plural elements to implement the same functionality. Likewise, when a functionality is subsequently described as being implemented using multi ple elements, further examples may implement the same functionality using a single element or processing entity. It will be further understood that the terms“comprises,”“comprising,” “includes” and/or“including,” when used, specify the presence of the stated features, integers, steps, operations, processes, acts, elements and/or components, but do not preclude the pres ence or addition of one or more other features, integers, steps, operations, processes, acts, elements, components and/or any group thereof.

Unless otherwise defined, all terms (including technical and scientific terms) are used herein in their ordinary meaning of the art to which the examples belong.

Fig. 1 illustrates an apparatus 100 for driving a DAC 130 based on a second complex-valued symbol succeeding a first complex-valued symbol. The apparatus 100 comprises a phase modulator 110 configured to shift a phase of an oscillation signal 111 for the DAC 130 by a phase shift value 113 based on a phase difference 112 between a phase of the second complex valued symbol and a phase value related to the first complex-valued symbol. The phase shift value 113 is limited to a predetermined value range. The apparatus 100 further comprises a processing circuit 120 configured to generate a control signal 121 for the DAC 130 indicative of an in-phase component and a quadrature component of the second complex-valued symbol. The in-phase component and the quadrature component of the second complex-valued symbol are based on the phase shift value 113.

The apparatus 100 may enable a hybrid modulation approach combining advantages of quad rature and polar modulation, while avoiding at least some of the drawbacks of both modula- tion techniques. In contrast to classic quadrature modulation, the phase of the oscillation sig nal for the DAC is modulated within a predetermined value (phase) range. In contrast to clas sic polar modulation, a phase modulated oscillation signal (with limited phase modulation) is used together with adapted in-phase and quadrature components instead of a single radius (amplitude) component.

Compared to classic polar modulation, the apparatus 100 may allow to control the DAC 130 such that the resulting RF signal exhibits reduced signal distortions (e.g. reduced Error Vector Magnitude, EVM). Moreover, required frequency modulation ranges may be reduced com pared to classic polar modulation. For example, if the phase modulator 110 uses Digitally Controlled Oscillators (DCOs) for generating the oscillation signal 111, the tuning range of the DCOs may be reduced compared to classic polar modulation, so that more simple DCO designs and a lower number of DCOs may be used. Also, design efforts and a power con sumption may be reduced compared to classic polar modulation since a lower sampling rate may be used and since no additional filtering before and after transformation from Cartesian to polar signal domain is required.

Compared to classic quadrature modulation, a power efficiency of the DAC 130 may be in creased since the reactive quadrature component is reduced due to the additional phase mod ulation (detailed explanation below in connection with Figs. 11 and 12). Also the maximum number of required DAC cells may be reduced up to the same number as for classic polar modulation (detailed explanation below in connection with Fig. 13).

The phase value related to the first complex-valued symbol may be based on accumulated phase shift values related to the first and further preceding complex-valued symbols. That is, the phase value related to the first complex-valued symbol may be the sum of the phase shift values calculated by apparatus 100 for the complex-valued symbols that precede the second complex-valued symbol. The accumulated phase shift values of the preceding complex-val ued symbols may, hence, represent the effective phase of the first complex-valued symbol as used by the apparatus 100 (e.g. the current phase of oscillation signal 111).

This may become more evident from Fig. 2. Fig. 2 illustrates a constellation diagram (com plex pointer diagram) 200. The abscissa denotes the in-phase component of a complex-valued symbol, whereas the ordinate denotes the quadrature component of the complex-valued sym bol.

A first pointer 210 indicates the position of the first complex-valued symbol C^^in the con stellation diagram 200. A second pointer 220 indicates the position of the second complex valued symbol C _n in the constellation diagram 200. The effective phase of the first complex valued symbol C _n-1 as used by apparatus 100 is <p _n-! , i.e. the phase value related to the first complex- valued symbol C _n-1 is f _h -i· The phase of the second complex- valued symbol C _n is f _h . That is, the phase difference between the phase of the second complex-valued symbol C _n and the phase value related to the first complex- valued symbol C _{n- 1} is Df _h|h-1 = f _h —

Yh—1·

In order to enable a limited phase modulation, the phase shift value Df _{H h} by which the os cillation signal 111 is phase shifted is limited to a predetermined value range. A limit of the predetermined value range is illustrated by means of line 230 in Fig. 2. Line 230 indicates a maximum (saturated) value Df _3AT ΐot the phase shift value Df _{H h} within the predetermined value range. In Fig. 2, the phase difference Df _h \ _h-ί is greater than the maximum value Df _3AT for the phase shift value Df _{H h} . Accordingly, the phase shift value Df _{H h} is limited to the maximum value Df _3AT , i.e. the value within the predetermined value range that is closest to the phase difference Df _h \ _h-ί . This may, e.g., be done by the processing circuit 120. If the phase difference Df _h \ _h-ί was smaller than the maximum value Df _3AT for the phase shift value Df _{H h} , no limitation (saturation) of the phase shift value Df _{H h} is required. For example, the processing circuit 120 may in this way generate, based on the phase difference Df _h|h-1 , a phase control signal for the phase modulator 110 indicative of the phase shift value Df _{H h} .

Fig. 3 illustrates the effect of shifting the phase of the oscillation signal 111 by means of constellation diagram 300. The initial phase of the oscillation signal 111 is equal to YH _{,P- I '} i.e. the phase value related to the first complex-valued symbol C _{n- 1} . By shifting the initial phase (pn _, n-i °f the oscillation signal 111 by Df _{H h} , the phase of the oscillation signal 111 for the second complex-valued symbol C _n is yp _,h = YH _,P-I + Df _{H h} , with Df _{H h} < Df _3AT . The phase shift of the oscillation signal 111 by Df _{H h} effectively corresponds to a rotation of the constellation diagram about its origin. As indicated in Fig. 3, the second complex-valued symbol C _n may, hence, be represented by adapted in-phase and quadrature components

An exemplary calculation of the in-phase and quadrature components I _{H n} and Q _{H n} is illus trated in Fig.4 by means of constellation diagram 400. By rotating the second complex-valued symbol C _n about the origin of a constellation diagram 400 opposite to f _{H h} , he· opposite to the combination of the phase shift value Df _{H h} and the phase value Y _{H,P- I} related to the first complex- valued symbol C _ri-1 , the in-phase and quadrature components I _{H n} and Q _{H n} may be calculated. That is, the initial in-phase and quadrature components of the second complex valued symbol C _n are transformed to a new reference system given by f _{H h} . The calculation of the in-phase component I _{H n} and the quadrature component Q _{H n} of the second complex valued symbol C _n by rotating the second complex-valued symbol C _n about the origin of the constellation diagram may, e.g., be done by the processing circuit 120 of apparatus 100.

It is evident from Fig. 2 to 4 that, if the phase difference Df _h \ _h-ί is smaller than the maximum value Df _3AT for the phase shift value Df _{H h} , the second complex- valued symbol C _n is rotated onto the abscissa. That is, the quadrature component Q _{H n} of the second complex-valued sym bol C _n is zero if the phase difference Df _h \ _h-ί is smaller than the maximum value Df _3AT for the phase shift value Df _{H h} . The apparatus 100, hence, effectively operates like a polar mod ulator if the phase difference is small.

It is to be noted that the predetermined valuable range for the phase shift value Df _{H h} , i.e. the maximum value Df _3AT , may be adjustable.

In other words, Figs. 2 to 4 may illustrate one specific example of the proposed hybrid mod ulation technique, namely combining phase modulation with an adjustable frequency modu lation limit and IQ modulation of the phase modulated RF carrier in order to compensate for the residual error. As described above in connection with Figs. 2 to 4, the combination of phase and IQ modulation to realize a transition from a complex pointer C _{n- 1} to C _n may in some examples be done in three steps:

a) saturation of a phase change Df _{H h} used for phase modulation to Df _3AT , if required phase change Df _h|h-1 is greater than Df _3AT b) residual transition from possible complex pointers being element of the straight line 230 through the origin (described by the saturated oscillation signal phase position f _{H h} ) to C _n via hybrid in-phase and quadrature components | / ^ | and |z? _{# ίi} |; and

c) calculation of hybrid in-phase and quadrature components I _{H n} and Q _{H n} by a rotation f _ROT.TI opposite to the saturated oscillation signal phase f _{H h} , he. transforming initial / _n and Q _n to the new reference system given by f _{H h} .

A more detailed example of an apparatus 500 for driving a DAC is illustrated in Fig. 5. The apparatus 500 comprises a processing circuit 510 that receives an initial in-phase component I _n and an initial quadrature component Q _n from a baseband DFE 540. The processing circuit 510 uses a polar Coordinate Rotation Digital Computer (CORDIC) algorithm 511 for calcu lating a phase f _h of the second complex-valued symbol based on the initial in-phase compo nent I _n and the initial quadrature component Q _n of the second complex-valued symbol. The polar CORDIC algorithm 511 may optionally further output the amplitude (radius) compo nent A _n of the second complex-valued symbol. However, the amplitude (radius) component A _n of the second complex-valued symbol may be neglected (i.e. not used).

By means of comparator 512, the processing circuit 510 compares the phase f _h of the second complex-valued symbol to the effective phase pn _,n -i used by the apparatus 500 for a preced ing first complex-valued symbol, i.e. a phase value related to the first complex-valued symbol. The comparator 512 outputs the phase difference Df _{b h} between the phase f _h of the second complex- valued symbol and the phase value pn _,n -i related to the first complex-valued sym bol.

The processing circuit 510 further comprises a saturator 513 which receives the phase differ ence Df _{b h} . The saturator 513 outputs a phase control signal for a phase modulator 520 that is indicative of a phase shift value Df _{H h} that is used by the modulator circuit 520 for shifting a current phase of an oscillation signal 521 for a DAC 530. If the phase difference Df _{b h} is within a predetermined value range (i.e. if the absolute value of the phase difference is smaller than a maximum value Df _3AT for the phase shift value Df _{H h} ), the phase shift value Df _H,h is equal to the phase difference Df _{b h} . If the predetermined value range does not com prise the phase difference Df _{b h} (i.e. if the absolute value of the phase difference is greater than the maximum value Df _5AT ), the phase shift value Df _{H h} is limited to the maxi mum value Df _5AT , i.e. the value within the predetermined value range that is closest to the phase difference Df _{b h} .

Further, the processing circuit 510 comprises a combiner 514 that combines the phase shift value Df _{H h} and the effective phase f _{H n} -i used by the apparatus 500 for the first complex valued symbol, i.e. a phase value related to the first complex-valued symbol. Accordingly, the combiner 514 outputs the effective phase yp _,h used by the apparatus 500 for the second complex-valued symbol, i.e. a phase value related to the second complex-valued symbol. The phase value pn _,n -i related to the first complex-valued symbol is provided by delaying the previously calculated effective phase pn _,n -i used by the apparatus 500 for the first complex valued symbol by means of delay element 515. Accordingly, the phase value yp _,h related to the second complex-valued symbol is delayed by delay element 515 for subsequent compar ison to a phase f _h+1 of a third complex- valued symbol that succeeds the second complex valued symbol in order to provide a phase shift value Df _{H h+1} for the third complex-valued symbol according to the above described scheme.

It is evident that a phase value related to a certain complex-valued symbol is the sum of the phase shift values calculated by apparatus 500 for the complex-valued symbols up to the cer tain complex-valued symbol. For example, the phase value pn _,n -i related to the first com plex-valued symbol is the sum of the phase shift values Df _{H 0} to Df _{H h-1} calculated by ap paratus 500 for the complex-valued symbols that precede the second complex-valued symbol. In other words, the phase value pn _,n -i related to the first complex-valued symbol is based on accumulated phase shift values related to the first and further preceding complex-valued sym bols.

It is evident from the above description that by shifting the current phase of the oscillation signal 521 based on the phase control signal indicative of the phase shift value Df _{H h} , the modulator circuit 520 supplies a phase modulated oscillation signal with limited phase mod ulation to the DAC 530. In order to be able to correctly generate the RF output signal RF _0Ut , the DAC 530 requires accordingly adapted in-phase and quadrature components of the second complex-valued symbol. The processing circuit 510 uses a rotation CORDIC algorithm 516 for calculating adapted in- phase and quadrature components of the second complex-valued symbol. The rotation CORDIC algorithm 516 receives the initial in-phase component I _n and the initial quadrature component Q _n of the second complex-valued symbol. Further, the rotation CORDIC algo rithm 516 receives the effective phase f _{H n} used by the apparatus 500 for the second complex valued symbol, i.e. the combination of the phase shift value Af _{H h} and the phase value YH _{,P- I} related to the first complex-valued symbol. The rotation CORDIC algorithm 516 rotates the second complex-valued symbol about the origin of the constellation diagram contrary to the effective phase f _{H n} (i.e. by a rotation Af _{K0T h} =—y _H,h in order to calculate the adapted in- phase component I _{H n} and the adapted quadrature component Q _{H n} of the second complex valued symbol.

For example, the processing circuit may calculate the in-phase component I _{H n} and the quad rature component Q _{H n} of the second complex- valued symbol based on an expression which is mathematically correspondent to

(1).

By using one or more control signals, the processing circuit 510 supplies the in-phase com ponent I _{H n} and the quadrature component Q _{H n} of the second complex-valued symbol to the DAC 530, so that the DAC 530 may activate a corresponding amount of DAC cells for the in-phase contribution to the RF output signal RF _0Ut , and a corresponding amount of DAC cells for the quadrature contribution to the RF output signal RF _0Ut .

In other words, the upper part of apparatus 500 may represent the phase path processing: The in-phase and quadrature signals 7 _n , Q _n are transformed to the phase and amplitude signals f _h , A _n by the polar CORDIC. However, only the phase signal f _h is used in the example illus trated in Fig. 5. The phase difference Af _{b h} between the required phase and the last effective hybrid phase (pn _, n-i is saturated if it exceeds ±Af _5AT . The saturated phase difference repre sents the phase change Af _{H h} of the proposed hybrid modulation technique. It may be accu mulated to generate the absolute, effective hybrid phase f _{H h} . The lower part of apparatus 500 may represent the I/Q path processing: A rotation CORDIC transforms the in-phase and quadrature signals I _n , Q _n to the hybrid components h.n, QH _,U according to the current absolute phase f _{H h} . This may, e.g., be done by the rotation CORDIC according to above expression (1).

As discussed above in connection with Figs. 2 to 4, Q _{H n} is zero if the phase change Af _{b h} is small enough (i.e. within the saturation limit ±Af _5AT ). The hybrid modulator illustrated in Fig. 5 is then effectively operating as polar modulator.

Another example of an apparatus 600 for driving a DAC is illustrated in Fig. 6. Compared to apparatus 500, the apparatus 600 illustrated in Fig. 6 exhibits some optional features in addi tion. In order to avoid any repetition, merely the differences between the apparatus 500 and the apparatus 600 are described in the following with respect to Fig. 6.

In apparatus 600, the processing of the phase difference Af _{b h} between the phase f _h of the second complex-valued symbol and the phase value (pn _, n-i related to the first complex- val ued symbol is split up. Therefore, the processing circuit 610 comprises an additional phase splitter 617 compared to processing circuit 510 illustrated in Fig. 5.

By means of phase splitter 617, the processing circuit 610 compares the phase difference Ay _b,h to a threshold value. If the absolute value of the phase difference Af _{b h} is greater than threshold value, the phase splitter 617 modifies the phase difference Af _{b h} by a phase modi fication value A(p _{LO n} in order to generate a modified phase difference Af _HEMci = Af _{b h} — Af _LO, n· The modified phase difference A(p _{REM n} is output by the phase splitter 617 to the saturator 513 and processed like the phase difference Af _{b h} in apparatus 500 in order to cal culate the phase shift value Af _{H h} .

Then, the effective phase value f _{H n} used by the apparatus 600 for a specific complex-valued symbol (i.e. the phase value related to a specific complex-valued symbol) is calculated by recombining the phase shift value Af _{H h} with the phase modification value A(p _{LO n} , and fur ther combining it with the phase value related to the preceding symbol as it is done in appa ratus 500 by combiner 514. The rotation CORDIC algorithm 516 again rotates the complex-valued symbol about the origin of the constellation diagram contrary to the effective phase f _{H n} (i.e. by a rotation f R _O T. _TI = -y _H,h ) i ⁿ order to calculate the in-phase component I _{H n} and the quadrature com ponent Q _{H n} of the complex- valued symbol. In other words, also rotating the complex-valued symbol about the origin of the constellation diagram is done by means of effective phase f _{H n} (the phase value related to the current complex-valued symbol), which is based on the signal indicative of the modification of the phase difference Af _{b h} by the phase modification value yio, -

The signal indicative of the modification of the phase difference Af _{b h} by the phase modifi cation value A(p _{W n} is not only supplied to the combiner 514, but also to a clock generation circuit that generates the in-phase and quadrature oscillation signals for the DAC 530 based on the oscillation signal 521 provided by phase modulator 520. As indicated in Fig. 6, the clock generation circuit may be part of the RF-DAC 530. For example, the clock generation circuit may generate, based on the oscillation signal 521, a plurality of second oscillation signals that are phase shifted by 90° with respect to each other. The clock generation circuit may further supply the two of the plurality of second oscillation signals to the DAC 530 as the in-phase and quadrature oscillation signals based on the signal indicative of the modifica tion of the phase difference Af _{b h} by the phase modification value Af _{10 h} . The selection of the in-phase and quadrature oscillation signals among the plurality of second oscillation sig nals may optionally also be based on further criteria (e.g. the signs of the in-phase component I _{H n} and the quadrature component Q _{H n} of the second complex-valued symbol).

That is, the phase difference Af _{b h} is split into a phase change Af _{10 h} acting on the phase of the divider of the oscillation signal 521 and a phase change A(p _{REM n} that is subject to the saturation. The phase difference Af _{b h} may, hence, be limited to half of the possible, instan taneous phase change granularity that may be realized by the phase switching of the oscilla tion signal 521 according to A(p _{REM n} .

In the following two exemplary phase splitting approaches will be presented. However, it is to be noted, that the proposed concept is not limited to these approaches. In general, any suitable combination of threshold value and phase modification value may be used. For example, the phase modification value Df _{EO h} may be ±p when the phase difference Df _{b h} exceeds the threshold value + The modified phase difference Df _{KEM h} is, hence, limited to ± Accordingly, if the phase difference Df _{b h} is greater than ± two of the plu rality of second oscillation signals are selected as the in-phase and quadrature oscillation sig- nals for the DAC 530 that are 180° phase shifted compared to the two of the plurality of second oscillation signals that are selected as the in-phase and quadrature oscillation signals for phase differences Df _{b h} smaller than ± . That is, the clock generation circuit switches between different pairs oscillation signal based on the indicated phase modification value Dyio _,h · An overview of the specific values of the phase modification value Df _{10 h} and the modified phase difference Df _{KEM h} for different phase differences Df _{b h} is given below in table 1.

Table 1

In an alternative example, the phase modification value Df _{EO h} may be ± when the phase difference Df _{b n} exceeds the threshold value ± The modified phase difference Df _{KEM h} is, hence, limited to ± Accordingly, if the phase difference Df _{b h} is greater than two of the plurality of second oscillation signals are selected as the in-phase and quadrature oscilla tion signals for the DAC 530 that are 90° phase shifted compared to the two of the plurality of second oscillation signals that are selected as the in-phase and quadrature oscillation signals for phase differences Df _{b h} smaller than + ^. If the phase difference Df _{b h} is greater than two of the plurality of second oscillation signals are selected as the in-phase and quad rature oscillation signals for the DAC 530 that are 180° phase shifted compared to the two of the plurality of second oscillation signals that are selected as the in-phase and quadrature oscillation signals for phase differences Df _{b h} smaller than ± An overview of the specific values of the phase modification value Df _{EO h} and the modified phase difference Df _{KEM h} for different phase differences Df _{b h} is given below in table 2.

Table 2 If A p _{W n} = 0 is selected for all Af _{b h} , the apparatus 600 operates like apparatus 500 since no phase splitting is used.

In other words, if an absolute value of the phase difference Af _{b h} exceeds a threshold value, the processing circuit may modify the phase difference Af _{b h} by phase modification value A p _{LO n} prior to further processing the phase difference, and generate a signal indicative of the modification of the phase difference Af _{b h} by the phase modification value Af _{10 h} . As indi cated above, the threshold value may be 90°, and the phase modification value may be 180°. Alternatively, the threshold value may be 45°, and the phase modification value may be 90°. Further, the threshold value may be 135°, and the phase modification value may be 180°. Also, a plurality of threshold values may be used together with a corresponding phase modi fication value.

An exemplary implementation of a transmitter 700 using an apparatus for driving a DAC according to the proposed architecture or according to one or more examples described herein is illustrated in Fig. 7.

The processing circuit 710 and the phase modulator 720 of the apparatus for driving a DAC are illustrated in the upper part of Fig. 7. The processing circuit 710 supplies a control signal for the DAC 730 that is indicative of the in-phase component I _{H n} and the quadrature compo nent Q _{H n} of the complex-valued symbol to a pre-distortion circuit 740. The pre-distortion circuit 740 pre-distorts (modifies) the control signal to correct for imperfections (e.g. nonlin- earities) of the processing components within the transmitter 700. Accordingly, the pre-dis tortion circuit 740 outputs pre-distorted in-phase component and quadrature components IDPD. _{U >} QDPD. _U °f the complex-valued symbol. The pre-distorted in-phase component and quadrature components / _{DPD n >} QDPD. _U °f the complex-valued symbol are then input to a sam ple rate converter (e.g. a Fractional Sample Rate Converter, FSRC) to change the sample rate of the control signal to the sample rate used by the transmitter for RF signal processing. The sample rate converted in-phase and quadrature components I _RF(t) , Q _{RF( )} °f the complex valued symbol are then input to a sign/magnitude conversion circuit 760 in order to determine the signs and the magnitudes (absolute values) of the in-phase component and quadrature components of the complex-valued symbol. Based on the signs of the in-phase component and quadrature components of the complex-valued symbol, the sign/magnitude conversion circuit 760 generates a first selection signal IQ_CSEL for a clock generation circuit 770.

The sign/magnitude conversion circuit 760 supplies the magnitude of the in-phase component and the magnitude of the quadrature component to the DAC 730. Based on the magnitudes of the in-phase and quadrature component |/ _FF(t) |, \Q _RF(t) | the DAC 730 ac tivates a corresponding amount of DAC cells for the in-phase contribution and the quadrature contribution to its RF output signal.

The processing circuit 710 further supplies a phase control signal to the phase modulator 720 that is indicative of the phase shift value Df _{H h} . The phase shift value Df _{H h} is calculated according to the proposed hybrid modulation technique or according to one or more examples described herein. The phase modulator 720 shifts the phase of oscillation signal clk _RF for the DAC 730 by the phase shift value Df _{H h} . As indicated in Fig. 7, the phase modulator 720 may, e.g., be based on a Digital Phase-Locked Loop (DPLL) or a Digital-to-Time Converter (DTC).

The oscillation signal clk _RF is supplied to clock generation circuit 770. The clock generation circuit 770 generates, based on the oscillation signal clk _RF , a plurality of second oscillation signals that are phase shifted by 90° with respect to each other. The clock generation circuit 770 further selects and supplies, based on the signs of the in-phase component and the quad rature component of the second complex-valued symbol that are indicated by the first selec tion signal IQ_CSEL, two of the plurality of second oscillation signals to the DAC 730 as in- phase and quadrature oscillation signals. The apparatus for driving a DAC used in transmitter 700 additionally supports phase splitting as described above in connection with Fig. 6. Therefore, the processing circuit 710 addition ally supplies a signal indicative of the modification of the phase difference Af _{b h} by the phase modification value A(p _{W n} to the phase modulator 720. The phase modulator 720 generates a second selection signal P_CSEL for the clock generation circuit 770 based on the phase mod ification value A(p _{W n} . Due to the second selection signal P_CSEL, the clock generation cir cuit 770 selects and supplies the two of the plurality of second oscillation signals to the DAC 730 as the in-phase and quadrature oscillation signals further based on the signal indicative of the modification of the phase difference Af _{b h} by the phase modification value Af _{10 h} .

It is to be noted that the selection of the in-phase and quadrature oscillation signals in trans mitter 700 is implemented slightly different compared to apparatus 600. While in apparatus 600, the signal indicative of the modification of the phase difference Af _{b h} by the phase mod ification value A(p _{W n} is directly supplied to the clock generation circuit, it is supplied to the phase modulator 720 in transmitter 700 which generates the second selection signal P_CSEL therefrom.

For implementing the proposed modulation technique, conventional polar or quadrature mod ulation transmitters may be used as a base since RF components like a two-point modulated RF-DPLL or DTC based phase modulator and a hybrid Capacitive-DAC (C-DAC) are used in conventional digital-polar and digital-IQ transmitter architectures. Adjustments with re spect to the proposed hybrid modulation architecture may be made in the in-phase and quad rature clock generation in order to support the instantaneous phase changes A(p _{W n} (e.g. real ized by selecting rising/falling clock edges and switching in-phase and quadrature clocks) given by the second selection signal P_CSEL. In order to achieve this, the second selection signal P_CSEL may be synchronized and gated with respect to the phase modulated RF clock (i.e. oscillation signal clk _RF ) based on the phase shift value Af _{H h} .

In order to consider the intermediate phase changes (i.e. the rotation of the orthonormal ref erence system) while interpolating the in-phase and quadrature components, the sample rate converter 750 may be controlled based on the phase shift value Af _{H h} . By using the proposed modulation technique, the transmitter 700 may benefit from the ad vantages of both polar and quadrature modulation. At the same time, the transmitter 700 may avoid at least some of the disadvantages of polar and quadrature modulation. This will become more evident from the following discussion of Figs. 8 to 13. Figs. 8 to 13 illustrate various parameters of a transmitter using the proposed modulation technique and phase splitting ac cording to above table 1.

Fig. 8 illustrates a constellation diagram 800. The abscissa denotes the in-phase component of a complex-valued symbol for classic quadrature modulation, whereas the ordinate denotes the quadrature component of the complex-valued symbol for classic quadrature modulation.

A complex trajectory 810 comprising a plurality of complex-valued symbols is illustrated in the constellation diagram 800. Further illustrated is the approximation of the complex-valued symbols of the complex trajectory 810 according to the proposed modulation technique. The complex-valued symbols are approximated by a respective pair of an adapted (hybrid) in- phase component 820 and an adapted (hybrid) quadrature component 830 calculated accord ing to the proposed modulation technique. It is evident from Fig. 8 that due to phase shifting the oscillation signal for DAC, the respective pairs of the adapted in-phase component 820 and the adapted quadrature component 830 are rotated with respect to the abscissa and the ordinate.

The course of the phase f _h of the complex trajectory 810 is illustrated in Fig. 9 by line 910. The effective (hybrid) phase f _{H n} used according to the proposed modulation technique (i.e. the accumulation of the phase shift values calculated for the complex valued symbols up to the current symbol) is illustrated in Fig. 9 by line 920.

Fig. 10 further illustrates the courses of the modified phase difference Df _{KEM h} and the phase shift value Df _{H h} . Further, the predetermined value range for the phase shift value Df _{H h} is illustrated by lines 1030. The lines 1030 indicate the maximum value Df _3AT of the phase shift value Df _{H h} .

It is evident from Fig. 10 that the hybrid phase change according to the proposed modulation technique, i.e. the phase shift value Df _{H h} , saturates to the maximum value Df _3AT if the mod- ified phase difference Df _{HEM h} exceeds the maximum value Df _3LT . Accordingly, the accu mulated phase yp _,h higs the phase f _h of the complex trajectory 810 as is evident from Fig. 9. The required residual trajectory movement for approximating the complex trajectory 810 transforms to a larger quadrature component 830 in Fig. 8. However, compared to classic quadrature modulation, the adapted quadrature component 830 may be much smaller than the conventional quadrature component so that the power conversion efficiency of the DAC may be higher for the proposed modulation technique.

Fig. 9 further illustrate the effect of the phase splitting. From sample 599 to sample 600, the phase difference Df _{b h} is modified by the phase modification value Df _{10 h} = p since the phase difference Df _{b h} exceeds the threshold value of as defined in table 1. Accordingly, the rather abrupt change of the phase f _h of the complex trajectory 810 at around sample 600 may be approximated within only a few samples by the proposed modulation technique.

In Fig. 11, the bars illustrate the power conversion efficiency given by the ratio of the recon structed complex signal power to the additive power of adapted (hybrid) in-phase and quad rature components for different predetermined value ranges for the phase shift value Df _{H h} , .i.e. for different maximum values (saturation values) Df _3AT of the phase shift value Df _{H h} . In Fig. 11, the saturation values Df _3AT of the phase shift value Df _{H h} are denoted as frequency saturation values D _3LT according to with f _s denoting the sampling frequency. The frequency saturation values D f _3AT denotes, hence, the maximum frequency change of the oscillation signal for the DAC corresponding to the maximum value Df _3AT for the phase shift of the oscillation signal.

As a reference, the power conversion efficiency for polar modulation is given by line 1110, and the power conversion efficiency for quadrature modulation is given by line 1120.

It is evident from Fig. 11 that the power conversion efficiency of the proposed modulation technique increases with increasing the maximum value Df _3AT of the phase shift value Df _{H h} . The power conversion efficiency may, already for small maximum values Df _3AT , be much higher than for classic quadrature modulation. The power conversion efficiency of the pro posed modulation technique may reach the power conversion efficiency of classic polar mod ulation. That is, with increasing saturation level, the power conversion efficiency shifts from the IQ only lower limit 1120 to the polar only upper limit 1110.

The bars in Fig. 12 further illustrate the average utilization of DAC cells by the proposed modulation technique for different predetermined value ranges for the for the phase shift value Df _{H h} , .i.e. for different maximum values (saturation values) Df _3AT of the phase shift value Df _{H h} . In Fig. 12, the saturation values Df _3AT of the phase shift value Df _{H h} are again denoted as frequency saturation values D _3LT . The part 1230 of a bar illustrates the average utilization of DAC cells for generating the in-phase contribution to the RF output signal of the DAC, whereas the part 1240 of a bar illustrates the average utilization of DAC cells for generating the quadrature contribution to the RF signal.

As a reference, the average DAC cell utilization for polar modulation is given by line 1210, and the average DAC cell utilization for quadrature modulation is given by line 1220.

It is evident from Fig. 12 that with increasing saturation level, the average DAC cell utilization shifts from an approx balanced in-phase/quadrature utilization to a utilization of almost only DAC cells for the in-phase contribution. The utilization of DAC cells for generating the quad rature contribution is minimized. That is, with increasing saturation level, the average DAC cell utilization shifts from the IQ only upper limit 1220 to the polar only lower limit 1210. Hence, less DAC cells are used on average due to the minimized quadrature contribution.

Similarly, the peak DAC cell utilization is reduced as illustrated in Fig. 13. The groups of bars in Fig. 13 illustrate the peak utilization of DAC cells by the proposed modulation tech nique for different predetermined value ranges for the for the phase shift value Df _{H h} , .i.e. for different maximum values (saturation values) Df _3AT of the phase shift value Df _{H h} . In Fig. 12, the saturation values Df _3AT of the phase shift value Df _{H h} are again denoted as frequency saturation values D f _SAT . Within each group of bars, the leftmost bar 1330 denotes the peak utilization of DAC cells for generating the in-phase contribution to the RF output signal of the DAC. The middle bar 1340 denotes the peak utilization of DAC cells for generating the quadrature contribution to the RF output signal of the DAC. The rightmost bar 1350 denotes the total peak utilization of DAC cells. As a reference, the total peak utilization of DAC cells for polar modulation is given by line 1310, and the total peak utilization of DAC cells for quadrature modulation is given by line 1320.

It is evident from Fig. 12 that with increasing saturation level, the peak DAC cell utilization for the quadrature contribution decreases, whereas the peak DAC cell utilization for the in- phase contribution remains substantially constant. That is, with increasing saturation level, total peak utilization of DAC cells shifts from the IQ only upper limit 1320 to the polar only lower limit 1310. Hence, a DAC with less cells may be used compared to classic quadrature modulation.

A phase modulator according to the proposed modulation technique may show a significantly reduced frequency modulation compared to pure polar modulation, whereas for pure IQ mod ulation an unmodulated RF-carrier is used. This may, e.g., be visualized by observing a mod ulated DCO of the phase modulator via inductive coupling using a sensing coil. Also the current consumption of a phase modulator according to the proposed modulation technique may be different compared to transmitters using pure polar and pure quadrature modulation. For example, if an output power of the transmitter is kept constant, the current consumed by a phase modulator according to the proposed modulation technique increases smoothly with increasing signal bandwidth, whereas for a transmitter that changes between using pure polar and pure quadrature modulation, the consumed current changes abruptly with increasing sig nal bandwidth.

In other words, a hybrid architecture was presented above in connection with Figs. 1 to 13 that combines aspects of IQ and phase modulation in order to reduce reactive quadrature com ponent utilization. As discussed, the required phase change between two complex samples may be saturated to a certain, adjustable value in order to reduce the maximum excitation of the frequency modulation signal. Further, appropriate in-phase and quadrature modulation signals may be determined by a rotational transformation that considers the instantaneous oscillation signal phase resulting from the saturated phase change. The saturated phase change may be accumulated and subtracted from the ideal phase to determine the required phase change for the next sample. With respect to a Radio Access Technology (RAT) dependent architectural usage of either digital-polar or digital-IQ architecture implemented in a common transmitter structure, the proposed hybrid modulation technique may be easily implemented by means of DFE and FSRC adjustments. Therefore, existing building blocks like a RF-DPLL phase modulator or a RF-DAC may be highly re-used.

As indicated in Fig. 7, sample rate conversion is used to up-sample the control signal indica tive of the hybrid in-phase and the quadrature component. However, the sample rate conver sion of a complex signal in conventional Cartesian in-phase/quadrature representation does not necessarily equal the same sample rate conversion of the complex signal in hybrid in phase/quadrature and phase representation if the signal components are processed individu ally. Therefore, the sample rate conversion of the complex signal in hybrid form as shown in Fig. 7 may result in additional in-band and out-of-band distortions (e.g. EVM degradation or increased spectral emission). With increasing signal bandwidth of the DAC output signal, the distortions may become more and more relevant.

In order to reduce the inherent interpolation errors of the hybrid signal, the hybrid phase switching signal (i.e. the phase modification value) may be recombined with the hybrid in- phase and quadrature signal components prior to the (fractional) sample rate conversion. For example, the hybrid in-phase and quadrate signals I _{H n} , Q _{H n} may be unfolded by the phase changes due to the phase switching of the oscillation signal. In this way, the phase switching information for the oscillation signal may be mapped to the hybrid in-phase/quadrature signal components. The phase unfolding prior to the (fractional) sample rate conversion may, hence, allow to significantly reduce the inherent interpolation error due to the sample rate conversion of the hybrid transmit modulation signal. That is, the resulting RF output signal may exhibit lower in-band distortions (e.g. lower EVM and in-band emission) and lower out-of-band dis tortion (e.g. close-in and far-off spectral emission). Compared to classic polar modulation, this may allow higher signal bandwidths for the resulting RF output signal while reducing the signal distortion. Alternatively, the DFE sample rate may be reduced for use cases in which signal distortion are acceptable to a certain degree in order to reduce the power consumption of the transmitter.

The effect of phase unfolding on the time series of the in-phase component I _{H n} and the quad rature component Q _{H n} is illustrated in Figs. 14 to 17. Fig. 14 illustrates the value of the in-phase component I _{H n} for a plurality of n consecutive samples. The line 1610 denotes the value of the in-phase component I _{H n} without phase un folding, whereas lines 1620 denotes the value of the in-phase component I _{H n} using phase unfolding.

Similarly, Fig. 16 illustrates the value of the quadrature component Q _{H n} for the plurality of samples. The line 1810 denotes the value of the quadrature component Q _//,n ^w ithout phase unfolding, whereas lines 1820 denotes the value of the quadrature component Q _{H n} using phase unfolding.

As a reference, Figs. 15 and 17 arranged below Figs. 14 and 16 illustrate the value of the phase modification value A p _{LO n} for the plurality of samples. Figs. 15 and 17 are identical.

It is evident from Figs. 14 and 16 that, if phase unfolding is used, the course of the in-phase component I _{H n} and the quadrature component Q _{H n} is smoother and exhibits less abrupt changes between adjacent samples in case of a phase switching event (i.e. A p _{W n} ¹ 0). That is, when the clock generation circuit selects a different pair from the plurality of second os cillation signals as in-phase and quadrature oscillation signals for the DAC due to the modi fication of the phase difference A p _{e n} by the phase modification value Af _{ί0 h} , a smoother course of the of the in-phase component I _{H n} and the quadrature component Q _{H n} is achieved. Abrupt direction changes of the course of the in-phase component I _{H n} and the quadrature component Q _{H n} (e.g. around sample 360 or between samples 373 and 379) may be avoided due to the phase unfolding. This may lead to a reduced error and therefore a reduced signal distortion with respect to the subsequent (fractional) sample rate conversion of the in-phase component I _{H n} and the quadrature component Q _{H n} .

Two possible implementations of the phase unfolding into an apparatus for driving a DAC according to the proposed hybrid modulation technique are illustrated in Figs. 18 and 19. Fig. 18 illustrates another example of an apparatus 2000 for driving a DAC. Compared to appa ratus 600 illustrated in Fig. 6, apparatus 2000 exhibits some optional features relating to phase unfolding. In order to avoid any repetition, merely the differences between the apparatus 2000 and the apparatus 600 are described in the following with respect to Fig. 18. In apparatus 600, the rotation of the complex-valued symbol about the origin of the constel lation diagram is based on the phase modification value A(p _{W n} since the rotation of the com plex-valued symbol is opposite to the effective phase value f _{H h=} Af _{b h} + Af _{10 h} + <r _{b ί1} _i. It is to be noted that the designations f _{5 h} , < s _, n- ₁ ^an d A(p _{S n} in Fig. 18 corresponds to f _{H h} , YH _,P — _I and Af _{H ΐ1} in Fig. 6.

In order to achieve the phase unfolding, the rotation of the complex-valued symbol about the origin of the constellation diagram is based on only the sum of the phase shift values A(p _{s 0} to Acps n calculated by apparatus 2000 for the complex-valued symbols up to the current com plex-valued symbol. In contrast to apparatus 600 illustrated in Fig. 6, the rotation of the com plex-valued symbol is not based on the accumulation of the phase modification value A<p _L0 . That is, the processing circuit 510 rotates the complex-valued symbol about the origin of the constellation diagram based on only the accumulated phase shift values related to the com plex-valued symbols up to the current complex-valued symbol.

Therefore, the phase shift value A(p _{S n} is combined with the accumulated phase shift values A(p _{s o} to Af _{5 h-1} by combiner 2018 of processing circuit 2010. A delay element 2019 of processing circuit 2010 is provided to delay the combination (Pspu.n °f the phase shift value Acps n with the accumulation of the phase shift values A(p _{s o} to Af _{5 h-1} , so that the next phase shift value A p _{5 n+1} may again be accumulated with the phase shift values accumulated so far.

The accumulation (Pspu.n °f the phase shift values is received by the rotation CORDIC algo rithm 2016 of processing circuit 2010, so that the rotation of the complex-valued symbol about the origin of the constellation diagram is opposite to the accumulation (pspu.m i- ^e · the rotation is based on yrot _,h ^=— Yeru _,h -

Since only the saturated hybrid phase part A(p _s is accumulated for generating the rotational phase signal (Pspu.n that acts on the hybrid IQ path, the hybrid in-phase and quadrature com ponents I _{H n} , Q _{H n} are inherently recombined with the phase information given by the phase switching signal A(p _{LO n} for the clock generation circuit (not illustrated).

The phase unfolding in apparatus 2000, hence, occurs prior to the rotation CORDIC algorithm 2016. An alternative implementation of the phase unfolding is illustrated in Fig. 19. Fig. 19 illus trates another example of an apparatus 2100 for driving a DAC. Compared to apparatus 600 illustrated in Fig. 6, apparatus 2100 exhibits some optional features relating to the phase un folding. In order to avoid any repetition, merely the differences between the apparatus 2000 and the apparatus 600 are described in the following with respect to Fig. 19.

The processing circuit 2110 calculates (determines) the phase shift values Af _{H h} , the phase modification value A p _{W n} and the effective phase value cp _{S n} for a complex- valued symbol in the same way as the processing circuit 610 of apparatus 600. It is to be noted that the designation p _{S n} in Fig. 19 corresponds to Fig. 6. For the sake of clarity, merely cal culation element 2150 is illustrated which calculates and outputs these values. It is to be noted that the calculation element 2150 may, e.g., comprise the blocks or functionalities illustrated in the upper part of Fig. 6 for calculating these values.

Also the rotation of the complex-valued symbol about the origin of the constellation diagram is done like in apparatus 600. That is, the rotation of the complex-valued symbol is based on the phase modification value A p _{LO n} .

In order to implement the phase unfolding, the processing circuit 2110 comprises a phase unfolder 2160 which receives the in-phase and quadrature components I _{H n} , Q _{H n} output by the rotation CORDIC algorithm 516.

By means of the phase unfolder 2160, the processing circuit 2110 negates the value of at least one of the in-phase component I _{H n} and the quadrature component Q _{H n} of the complex-valued symbol and/or swaps the values of the in-phase component I _{H n} and the quadrature component Q _{H n} of the complex-valued symbol based on a remainder of a Euclidian division of the phase modification value A p _{W n} by 360° (i.e. 2p). The modified in-phase and quadrature compo nents I _{H n} , Q _{H n} of the complex-valued symbol are then provided to the DAC 530 via one or more control signals. For example, the modification of the in-phase and quadrature compo nents I _{H n} , Q _{H n} of the complex-valued symbol by the phase unfolder 2160 may be done ac cording to below table 3.

Table 3

The effect of the phase unfolding will become more evident from the following discussion of Figs. 20 and 21.

Fig. 20 illustrates a constellation diagram 2200. The abscissa denotes the in-phase component of a complex-valued symbol, whereas the ordinate denotes the quadrature component of the complex-valued symbol.

Points 2210 illustrate a sequence of complex-valued symbols. The line 2220 denotes the cor responding complex trajectory using classic quadrature modulation as a reference. Line 2230 denotes the resulting complex trajectory using the proposed hybrid modulation technique without phase unfolding as discussed above. Line 2240 denotes the resulting complex trajec- tory using the proposed hybrid modulation technique with phase unfolding as discussed above.

It is evident from Fig. 20 that, if phase unfolding is used, the resulting complex trajectory deviates less from the complex trajectory for classic quadrature modulation. That is, the amount of signal distortion is reduced if phase unfolding is used.

This is further evident from Fig. 21 which illustrates the corresponding Power-Spectral-Den- sity (PSD) plot 2300. Line 2310 denotes the corresponding PSD for classic quadrature mod ulation as a reference. Line 2320 denotes the resulting PSD for the proposed hybrid modula- tion technique without phase unfolding as discussed above. Line 2330 denotes the resulting PSD for the proposed hybrid modulation technique with phase unfolding as discussed above. It is evident that, if phase unfolding is used, the amount of spectral emission is significantly reduced. Accordingly, phase unfolding may allow to reduce in-band as well as out-of-band distortions.

In the examples above, CORDIC algorithms were used by processing circuits for calculating the phase of a complex-valued symbol and for rotating the complex-valued symbol. However, due to their imperfections also CORDIC algorithms contribute to a certain degree to signal errors and, hence, cause CORDIC related signal distortions. The error contribution of a CORDIC algorithm may, e.g., depend on the number of used iterations and the used word length. Using a high number of iterations and great word lengths may, however, negatively affect a power efficiency, a chip-area consumption as well as a latency of the processing cir cuits. Hence, it may be desired to use only a short word length and a small number of iterations for the CORDIC algorithm.

The effect of the used number of iterations on the output of the CORDIC algorithm is illus trated in Fig. 22 which illustrates a CORDIC micro rotation permutation tree. It is evident from Fig. 22 that a rotation CORDIC algorithm (e.g. CORDIC algorithm 516 illustrated in Figs. 5, 6 and 19) can rotate a complex-valued symbol only by a discrete set of phase values. The set of phase value and, hence, the granularity of the phase rotation depends on the number of used iterations. The more iterations used, the finer the granularity of the phase rotation.

The effect of the limited granularity on the proposed modulation technique is illustrated in Figs. 23 and 24. Fig. 23 illustrates a similar situation like above Fig. 4. However, in the con stellation diagram 2500 of Fig. 23, a residual phase error of the rotation CORDIC algorithm used for rotating the complex-valued symbol based on the phase shift value is considered.

If the complex-valued symbol C _n was ideally rotated about the origin of the constellation diagram 2500 by the CORDIC algorithm (i.e. without error), the ideal in-phase and quadrature components / _n and Q _{H n} were calculated. However, since the CORDIC algorithm can only rotate the complex-valued symbol C _n by a discrete set of phase values, the in-phase and quad rature components I _{H n} and Q _{H n} are calculated. It is evident from Fig. 23 that a rotation (phase) error p _CE,n describing the discrepancy be tween the ideal in-phase and quadrature components / _n and Q _{H n} and the actually calculated in-phase and quadrature components I _{H n} and Q _{H n} is present in the rotational transformation.

However, the rotation error p _CE,n is output by the CORDIC algorithm and is, hence, known. As illustrated in Fig. 24, the known rotation error p _CE,n ^ma y be compensated by the phase of the oscillation signal for the DAC. The processing circuit outputs the phase shift value A p _{S n} to the phase modulator which does not consider the residual phase error of the CORDIC al gorithm. Therefore, the rotation error p _CE,n ^ma y be used as correction for the phase shift value Af _{3 h} , so that the corrected phase shift value Af _{H h} = A p _{S n} — pc _E,n> which is supplied to the phase modulator, takes into account the residual phase error of the CORDIC algorithm. By using this correction, the discrepancy due to the non-ideal rotation between the ideal in- phase and quadrature components / _n and Q _{H n} and the actually calculated in-phase and quad rature components I _{H n} and Q _{H n} may be compensated.

In other words, the errors of the rotation CORDIC algorithm due to the limited number of iterations may be cancelled in the phase modulation path controlling the phase modulator and, hence, the phase of the oscillation for the DAC. Accordingly, errors arising in the polar CORDIC algorithm for calculating the phases of the complex-valued symbols may be can celled by the rotation CORDIC algorithm. In this way, the number of CORDIC iterations in both CORDIC algorithms may be reduced (significantly) without introducing errors in the final modulated RF signal that is output by the DAC.

Accordingly, this error cancellation technique may allow CORDIC design of lower complex ity since the CORDIC errors are mutually cancelled. That is, the used CORDIC algorithms may have a (significantly) reduced number of iterations and micro rotations, respectively. This may allow to reduce, in a transmitter, the DFE latency, the DFE power consumption, the required chip-area of the DFE and full CORDIC error cancellation.

An implementation of the CORDIC error cancellation is illustrated in Fig. 25. Fig. 25 illus trates another example of an apparatus 2700 for driving a DAC. Compared to apparatus 500 illustrated in Fig. 5, apparatus 2700 exhibits some optional features relating to CORDIC error cancellation. In order to avoid any repetition, merely the differences between the apparatus 2700 and the apparatus 500 are described in the following with respect to Fig. 25. It is to be noted that Fig. 25 does not illustrate blocks or elements related to the phase splitting and phase unfolding techniques described above. However, it is to be noted that the CORDIC error can cellation may also be used together with at least one of the phase splitting technique and the phase unfolding technique.

The processing circuit 2710 calculates (determines) the phase shift values Df _{5 h-M} and the effective phase value (ps _,n-M f° ^{r a} complex-valued symbol in the same way as the processing circuit 510 of apparatus 500.

Also the rotation of the complex-valued symbol about the origin of the constellation diagram is done like in apparatus 500. That is, the rotation of the complex-valued symbol is based on the effective phase value f _{5 ,h-M} ·

In order to account for the processing time required for calculating a phase f _h-M of a com plex-valued symbol using the polar CORDIC algorithm 511, the processing circuit 2710 com prises a delay element 2770 for delaying the complex-valued symbol (/ _n and Q _n ) prior to in putting it into the rotation CORDIC algorithm 516 based on the processing time of the polar CORDIC algorithm 511. In the example of Fig. 25, it is assumed that calculating the phase f _h-M °f ^a complex-valued symbol using the polar CORDIC algorithm 511 takes M samples so that the delay element 2770 delays the complex-valued symbol by M samples.

As said above, the rotation CORDIC algorithm 516 outputs the rotation error <PRM _O,TI -(M+R) that arises due to using a predetermined number of iterations for rotating the complex-valued symbol about the origin.

Based on the rotation error signal output by the CORDIC algorithm 516, the processing circuit 2710 generates an according phase correction value A p _{C£ n-(M+R)} .

By means of combiner 2780, the processing circuit 2710 combines the phase shift value and the phase correction value. In order to account for the processing time required for rotating the complex-valued symbol about the origin of the constellation diagram by the rotation CORDIC algorithm 516, the processing circuit 2710 comprises another delay element for delaying the phase shift value prior to supplying it to combiner 2780 based on the processing time of the rotation CORDIC algorithm 516. In the example of Fig. 25, it is assumed that rotating the complex-valued symbol using the rotation CORDIC algorithm 516 takes R sam ples so that the delay element delays the phase shift value A p _{S n-M} by R samples.

The combiner 2780, hence, outputs the modified phase shift value Af _{H h-(M+} ^ = A p _{S n-(M+R)} + A p _{CR n-(M+R)} to the phase modulator 520. Therefore, the phase modulator 520 further shifts the phase of the oscillation signal 521 for the DAC 530 based on the phase correction value A p _{CR n-(M+R)} .

As illustrated in Fig. 25, the processing circuit 2710 comprises a differentiator 2790 to gen erate the phase correction (i.e. frequency modulation) value by differentiating the rotation error <p _RM0,n -( _M+R) ·

The effect of the proposed CORDIC error cancellation is evident from Fig. 26. Fig. 26 illus trates a constellation diagram 2800. The abscissa denotes the in-phase component of a com plex-valued symbol, whereas the ordinate denotes the quadrature component of the complex valued symbol.

The line 2810 denotes the complex trajectory of the complex-valued symbols input to an ap paratus for driving a DAC according to the proposed technique as reference. Line 2820 de notes the resulting complex trajectory using the proposed hybrid modulation technique with out CORDIC error cancellation as discussed above. Line 2830 denotes the resulting complex trajectory using the proposed hybrid modulation technique with CORDIC error cancellation as discussed above.

It is evident from Fig. 26 that, if CORDIC error cancellation is used, the resulting complex trajectory deviates less from the complex trajectory of the input complex-valued symbols. The complex trajectory 2830 substantially overlaps the reference trajectory 2810. That is, the amount of signal distortion is reduced if CORDIC error cancellation is used.

Fig.27 further illustrates an overview of the signal courses of the various phase control signals for the phase modulator. Line 2910 denotes the course of the phase shift value A p _s . Further, the predetermined value range for the for the phase shift value A p _s is illustrated by lines 2940. The lines 2940 indicate the maximum value Af _3AT of the phase shift value A<p _s . Line 2920 denotes the course of the phase correction value Ap _CE . Finally, line 2930 denotes the modified phase shift value Af _H , i.e. the combination of the phase shift value A p _s and the phase cor rection value A<p _CE as received by the phase modulator.

It is evident from Fig. 27 that the phase shift value A p _s remains within the limits given by the maximum value Af _5LT . However, the phase correction value A<p _CE may increase the modified phase shift value Af _H to more than the maximum value Af _3AT when it is subtracted from the phase shift value A p _s . That is, the phase (or frequency) modulation range of the phase mod ulator is slightly increased by the CORDIC error cancellation.

The effect of limiting the number of CORDIC iterations on in-band distortions as well as the effect of the proposed CORDIC error cancellation is illustrated in Fig. 28. Line 3010 illus trates the peak EVM of the RF output signal of the DAC, which is measure for the in-band distortions, if CORDIC error cancellation is not used. Lines 3020 illustrates the peak EVM if CORDIC error cancellation is used. Further, line 3030 illustrates the Root-Mean-Square (RMS) EVM if CORDIC error cancellation is not used, whereas line 3040 illustrates the RMS EVM if CORDIC error cancellation is used.

It is evident from Fig. 28 that the EVM (i.e. the in-band distortions) increases for less CORDIC iterations if CORDIC error cancellation is not used. However, if CORDIC error cancellation is used, no EVM degradation is observed.

Generally speaking, some of the above examples relate to a means for driving a DAC based on a second complex-valued symbol succeeding a first complex-valued symbol. The means comprises a means for shifting a phase of an oscillation signal for the DAC by a phase shift value based on a phase difference between a phase of the second complex-valued symbol and a phase value related to the first complex-valued symbol. The phase shift value is limited to a predetermined value range. The means further comprises a means for generating a control signal for the DAC indicative of an in-phase component and a quadrature component of the second complex-valued symbol, wherein the in-phase component and the quadrature compo nent of the second complex-valued symbol are based on the phase shift value.

As discussed above, the phase value related to the first complex-valued symbol may be based on accumulated phase shift values related to the first and further preceding complex-valued symbols. The means for driving a DAC may be implemented by an apparatus for driving a DAC de scribed above (e.g. Figs. 1, 5, 6, 19 or 25). The means for shifting a phase of an oscillation signal may be implemented by a phase modulator described above (e.g. Figs. 1, 5, 6, 19 or 25). The means for generating a control signal may be implemented by a processing circuit described above (e.g. Figs. 1, 5, 6, 19 or 25).

An example of an implementation using an apparatus for driving a DAC according to one or more aspects of the proposed architecture or one or more examples described above is illus trated in Fig. 29. Fig. 29 schematically illustrates an example of a mobile device 3200 (e.g. mobile phone, smartphone, tablet-computer, or laptop) comprising an apparatus 3210 for driv ing a DAC according to an example described herein.

For example, a transmitter 3230 may comprise the apparatus 3210 for driving a DAC. The transmitter 3230 may additionally comprise the DAC 3220 that generates a RF transmit signal based on the control signal and the oscillation signal provided by the apparatus 3210.

At least one antenna element 3240 of the mobile device 3200 may be coupled to the transmit ter 3230.

To this end, a mobile device may be provided enabling the superior power efficiency of dig ital-polar architecture in combination with the low in-band signal distortion of digital-IQ ar chitecture.

The proposed hybrid modulation technique is not limited to mobile devices. The hybrid mod ulation technique may be used in any electronic device for generating RF transmit signals.

An example of a method 3300 for driving a DAC based on a second complex-valued symbol succeeding a first complex-valued symbol is illustrated by means of a flowchart in Fig. 30. The method 3300 comprises shifting 3302 a phase of an oscillation signal for the DAC by a phase shift value based on a phase difference between a phase of the second complex-valued symbol and a phase value related to the first complex-valued symbol. The phase shift value is limited to a predetermined value range. Further, the method 3300 comprises generating 3304 a control signal for the DAC indicative of an in-phase component and a quadrature component of the second complex-valued symbol. The in-phase component and the quadra ture component of the second complex-valued symbol are based on the phase shift value.

More details and aspects of the method are mentioned in connection with the proposed tech nique or one or more examples described above (e.g. Figs. 1 - 29). The method may comprise one or more additional optional features corresponding to one or more aspects of the proposed technique or one or more examples described above.

Another modulation technique is presented in the following with reference to Figs. 31 to 40.

Fig. 31 illustrates an apparatus 3400 for generating a RF signal 3401. The apparatus 3400 comprises a modulator circuit 3410 configured to generate the RF signal 3401 based on an input signal 3402. The input signal 3402 contains information related to the RF signal 101. For example, the input signal 3402 may be a baseband signal or may be a signal that is related to a baseband signal. Further, the apparatus 3400 comprises a control circuit 3420 for control ling the modulator circuit 3410.

The control circuit 3420 comprises electronic circuitry to control the modulator circuit 3410 to generate the RF signal 3401 using polar modulation if the input signal 3402 exhibits a first characteristic. If the input signal 3402 exhibits a different second characteristic, the electronic circuitry of the control circuit 3420 controls the modulator circuit 3410 to generate the RF signal using quadrature modulation. For controlling the modulator circuit 3420, the control circuit 3410 comprises an output 3421 for supplying a control signal 3422 to the modulator circuit 3410, wherein the control signal 3422 indicates the desired modulation method, i.e. the modulation method that has been determined by the control circuit 3420 based on the input signal 3402.

The modulator circuit 3410 comprises electronic circuitry to generate the RF signal 3401 us ing polar modulation in a first mode of operation, and to generate the RF signal 3401 using quadrature modulation in a second mode of operation. The modulator 3410 comprises an in put 3411 for receiving the control signal 3422 which is indicative of the desired mode of operation. Further, the control circuit 3420 de-activates part of the electronic circuitry of the modulator circuit 3410 if the input signal transits from the second characteristic to the first characteristic, i.e. if the modulator circuit 3420 switches from quadrature modulation to polar modulation.

The first and second characteristics may be characteristics of the input signal 3402 itself, or desired characteristics of the resulting RF signal 3401 since the RF signal 3401 is based on the input signal 3402, i.e., the first and second characteristics may be desired characteristics of the resulting RF signal 3401 which are related to an information of the input signal 3402. For example, the first characteristic may indicates that, for a sample of the input signal 3402, the RF signal 3401 exhibits a first instantaneous frequency having a frequency deviation from a desired carrier frequency of the RF signal 3401 that is smaller than a threshold value. Ac cordingly, the second characteristic may indicate that, for a sample of the input signal 3402, the RF signal 3401 exhibits a second instantaneous frequency having a frequency deviation from a desired carrier frequency of the RF signal 3401 that is greater than a threshold value. The threshold value may, e.g., correspond to a maximum phase change supported by the mod ulator circuit 3410 for generating the RF signal by polar modulation.

As indicated above, the second characteristic may in some examples be the negation of the first characteristic.

The apparatus 3400 comprising the modulator circuit 3410, which is capable of polar and quadrature modulation, may allow to generate the RF signal 3401 using the modulation tech nique that is most advantageous. Accordingly, a signal quality of the resulting RF signal 3401 may be improved compared to conventional transmitter architectures supporting either polar or quadrature modulation. Moreover, the hardware requirements for further components of the apparatus 3400 may be relaxed. For example, a frequency range of a DCO providing an oscillation signal for the modulator circuit 3410 for RF signal generation may be smaller compared to a conventional transmitter capable of only polar modulation. Accordingly, also an EVM of the resulting RF signal may be lowered compared to a polar transmitter. Compared to a transmitter capable of only quadrature modulation, an overall efficiency of the apparatus 3400 may be increased since the apparatus 3400 may generate the RF signal 3401 using polar modulation in some case - polar modulation being more efficient than quadrature modulation. Moreover, since unused electronic circuitry of the modulator circuit 3410 is de-activated when the modulator circuit 3410 switches to polar modulation, the energy efficiency of the apparatus 3400 may be further increased.

A more detailed view of an apparatus 3500 for generating a RF signal according to the pro posed architecture is illustrated in Fig. 32. Complex-valued symbols are provided as input signal by a DFE 3590 to modulator circuit 3510. By default, the signal is transmitted in polar mode. Polar coordinates, i.e. amplitude (radius) and phase, are calculated by vector (polar) CORDIC 3511. The phase is differentiated by differentiator 3512 to calculate the instantane ous frequency. If the instantaneous frequency is too high, its value is limited by saturator 3513 to the threshold value and the saturator 3513 generates a phase error.

In other words, the input signal comprises information on an in-phase component and a quad rature component of a sample, wherein the modulator circuit 3510 comprises a processing circuit for calculating a phase of the sample based on the in-phase component and the quad rature component, and for calculating an instantaneous frequency of the radio frequency sig nal for the sample based on the phase of the sample. The processing circuit further generates a signal indicative of a frequency deviation of the instantaneous frequency of the RF signal for the sample to a desired carrier frequency of the RF signal, wherein, if the frequency devi ation is greater than a threshold value, the processing circuit generates the signal indicative of the frequency deviation such that the indicated frequency deviation is limited to the threshold value.

An oscillation generator 3514 of the modulator circuit 3510 generates a reference oscillation signal for the DAC 3530 based on the signal indicative of the frequency deviation. A delay element 3517 delays the supply of the signal indicative of the frequency deviation to the os cillation generator 3514.

Also, the processing circuit (by means of saturator 3513) calculates a phase error related to the difference between the frequency deviation and the threshold value.

In other words, the input signal exhibits a first characteristic if the deviation of the instanta neous frequency of the radio frequency signal for the sample is smaller than a threshold value, i.e. if the phase error is zero. If the deviation of the instantaneous frequency of the radio fre quency signal for the sample is greater than the threshold value, i.e. if the phase error is non zero, the input signal exhibits a second first characteristic.

From the phase error, the control circuit 3520 recognizes to change from polar to IQ modula tion and to switch on all circuitry necessary for IQ modulation. That is, the control circuit 3520 controls the modulator 3510 to generate the RF signal by polar modulation or quadrature modulation based on the phase error. Further, the control circuit 3520 activates part of the circuitry of the modulator circuit 3510 if the input signal transits from the first characteristic to the second characteristic (changeover from small deviation to great deviation of instanta neous frequency).

However, after some samples, the phase error degrades to zero. This means for the control circuit 3520 that the data can again be transferred via efficient polar mode. Accordingly, pre viously activated circuitry necessary for IQ modulation is switched off again to save current.

While the phase error is non-zero, a number of least significant bits of the phase error are fed back to the input of saturator 3513 and combined with the signal indicative of the instantane ous frequency. That is, prior to generating the signal indicative of the frequency deviation, the processing circuit combines the signal indicative of the instantaneous frequency of the radio frequency signal for the sample with a number of least significant bits of the phase error for a preceding sample by means of combiner 3519.

A number of most significant bits (e.g. two) are used to control the phase shifter 3515. Phase shifter 3515 receives in-phase and quadrature components from rotation circuit 3516 and phase shifts them by 90° or 180° (i.e. multiples of 90°) based on the number of most signifi cant bits.

Rotation circuit 3516 calculates second in-phase and quadrature components based on the in- phase component and the quadrature component of the sample, and based on the combination of the phase of the sample provided by the vector CORDIC algorithm 3511 and the number of least significant bits of the phase error (indicated by combiner 3518 in Fig. 32). Further, the control circuit 3520 controls, based on the number of most significant bits of the phase error, the oscillation generator 3514 to generate from the reference oscillation signal a single oscillation signal, or a pair of oscillation signals which are phase shifted by 90° with respect to each other for the DAC 3530. That is, the oscillation generator 3514 generates a single oscillation signal if polar modulation is used, and a pair of 90° phase shifted oscillation signals if quadrature modulation is used.

Accordingly, if the input signal transits from the first characteristic to the second characteristic (i.e. change from small deviation to great deviation of instantaneous frequency), the control circuit 3520 doubles a divider value used by a frequency divider of the oscillation generator 3514 for generating the phase shifted oscillation signals for the DAC 3530 in IQ mode based on the reference oscillation signal. To the contrary, if the input signal transits from the second characteristic to the first characteristic (i.e. change from great deviation to small deviation of instantaneous frequency), the control circuit is configured to halve a divider value used by the frequency divider for generating the single oscillation for the DAC 3530 in polar mode signal based on the reference oscillation signal.

Depending on the used modulation mode, some components of the DAC 3530 and its supply may be activated or de-activated. For example, if the input signal transits from the second characteristic to the first characteristic (i.e. change from great deviation to small deviation of instantaneous frequency), the control circuit 3520 may de-activate at least one of a control circuit for the DAC 3530 such as a column or a row decoder for DAC cells that are only used for the quadrature contribution in IQ mode. Also a corresponding IQ control signal and its corresponding DAC signal path may be de-activated. Since only one oscillation signal is used in polar mode, a distribution circuit for distributing the quadrature oscillation signal to the DAC 3530 may be de-activated. As said before, also the rotation circuit 3516 and the phase shifter 3515 may be de-activated when the modulator circuit 3510 switches to polar mode.

As indicated above, if the input signal transits from the first characteristic to the second char acteristic (i.e. change from small deviation to great deviation of instantaneous frequency), the control circuit 3520 controls the modulation circuit 3510 to switch from polar to quadrature modulation. Accordingly, the corresponding blocks and circuits of modulation circuit 3510 necessary for IQ modulation may be activated by control circuit 3520 (indicated by the switches in Fig. 32). If the delay 3517 after the saturator 3513 is slightly increased, the IQ correction may already start before the phase jump (i.e. the transition from the first to the second characteristic) oc curs. The delay may be determined by the control circuit 3510 based on the input signal.

Moreover, the apparatus 3500 may comprise a (fractional) sample rate converter for up-sam pling like in a conventional polar transmitter. The sample rate converter may use the fre quency deviation that is limited to the threshold value (i.e. saturated Af output by saturator 3513) for determining the instantaneous frequency and, hence, the required sampling rate. The saturated Af automatically generates the shifted carrier frequency needed in IQ mode.

A summary of the above operation of apparatus 3500 is given in Fig. 33, which illustrates an exemplary flowchart of operating apparatus 3500.

As described above, the control circuit 3520 initially controls modulator circuit 3510 to gen erate the RF signal using polar modulation. If the phase error output by saturator 3513 is zero, the modulator circuit 3510 is controlled to continue polar modulation. If the phase error is non-zero, quadrature modulation is prepared by activating (switching on) the circuitry of the modulator circuit 3510 that is required for quadrature modulation. As long as the phase error is non-zero, the control circuit 3520 controls modulator circuit 3510 to generate the RF signal using quadrature modulation. When the phase error returns to zero, polar modulation is pre pared by de-activating (switching off) the circuitry of the modulator circuit 3510 that is only required for quadrature modulation. The control circuit 3520 again controls modulator circuit 3510 to generate the RF signal using polar modulation.

Usually, cellular transmit signals are of low bandwidth where polar modulation is most effec tive. Since in this mode all IQ circuitry is switched off (e.g. 2 ^nd oscillation signal distribution, row and column decoder of 2 ^nd DAC or for part of a DAC, mixer in front of DAC), a high power efficiency may be achieved.

An implementation for (effectively) coping with big phase jumps by switching between polar and quadrature modulation is presented in Fig. 34, which illustrates an apparatus 3700 for generating a RF signal 3701. The apparatus 3700 comprises a modulator circuit 3720 configured to generate the RF signal 3701 based on a plurality of samples of an input signal 3702. The modulator 3720 is controlled by a control circuit 3710, which supplies a control signal 3711 to the modulator circuit 3720. The control circuit 3710 controls the modulator circuit 3720 to generate the RF signal 3701 by polar modulation for a first and a third sequence of the samples. The control circuit 3710 further controls the modulator circuit 3720 to generate the RF signal by quadrature modula tion for a second sequence of the samples that directly succeeds the first sequence of the samples. The third sequence of the samples directly succeeds the second sequence of the sam ples.

The control circuit 3710 is configured to control the modulator circuit 3720 to generate the RF signal with a first carrier frequency for at least one sample of the second sequence, and to generate the RF signal with a second carrier frequency for at least one other sample of the second sequence.

For example, the first carrier frequency may correspond to a maximum phase change sup ported by the modulator circuit 3720 for generating the RF signal by polar modulation.

The second carrier frequency may be based on a phase difference between a phase difference between the last sample of the first sequence of the samples and the first sample of the third sequence of the samples, i.e. the phase change covered by the second sequence of samples, and the summed phase change for the samples of the second sequence of the samples trans mitted with the first carrier frequency. That is, the second carrier frequency may be based on the phase difference between the last sample of the second sequence of the samples transmit ted with the first carrier frequency and the first sample of the third sequence of the samples.

The effect of using two carrier frequencies during quadrature modulation will become more evident from Figs. 35 to 37. Fig. 35 illustrates the course of the phase of a complex trajectory 3810 over time. At time stamp t ₀ the signal trajectory 3810 is smooth enough to be transmitted in efficient polar mode. At time stamp t ₂ the trajectory of the input signal makes near the origin a big phase jump from 20° to 150°. Around this time, the signal is transmitted in IQ mode since this phase jump is so big that the phase part of the polar circuitry of the modulator circuit needs some samples to follow up. This is indicated by line 3820 in Fig. 35. The phase of the polar is altered with a constant phase offset (e.g. the maximum supported phase change) which is equivalent to a constant carrier frequency offset during catch up. For example at the very last correction sample 3830, the remaining phase offset to the input signal may be dif ferent from the constant phase offset (e.g. be smaller than the maximum supported phase change). Accordingly a different phase offset is used for this last sample which corresponds to another carrier frequency. At time stamp t ₃ the phase part of the polar circuitry of the modulator circuit has catched up the original signal trajectory 3810 and the modulator is switched back from IQ mode to polar mode. At later time stamp t ₄ the signal is again trans mitted in polar mode (until the next phase jump that is too big for transmission in polar mode occurs). In particular, the phase jump of 130° is catched up by 14 steps of each 9° and one final step of 4° phase change (increment) of the phase part of the polar circuitry of the modu lator circuit. Here the maximum phase offset (change) supported by the modulator circuit is assumed to be 9°.

It is evident from Fig. 35 that the samples up to time stamp t ₂ correspond to the first sequence of samples, whereas the samples from time stamp t ₂ to time stamp t ₄ correspond to the second sequence of samples and the samples from time stamp t ₄ on correspond to the third sequence of samples. By using two different carrier frequencies, the phase part circuitry of the modu lator circuit may be changed by the maximum supported phase change and only the last sam ple of the second sequence of samples needs to be transmitted using a smaller phase change. Accordingly, the number of samples transmitted using quadrature modulation may be mini mized, so that the more efficient polar mode may be used for a greater amount of samples.

Fig. 36 illustrates a further technique for catching up the phase jump. In Fig. 36, a phase jump of 90° is achieved by changing from the in-phase DAC to the quadrature DAC for polar mod ulation. Hence, only 40° need to be catched up by the polar phase path. This may be done by only 4 steps of each 9° and one remaining step of 4°. Hence, less IQ correction steps are required. That is, the second sequence of samples is reduced here.

In order to achieve the 90° phase jump, the modulator circuit 3720 may use a first oscillation signal for generating the RF signal 3701 for the first sequence of the samples, and use a second oscillation signal for generating the RF signal 3701 for the third sequence of the samples. In this respect, the first oscillation signal is used for generating the in-phase or a quadrature contribution to the RF signal for the second sequence of the samples, and the second oscilla tion signal is used for generating the other one of the in-phase or the quadrature contribution to the RF signal for the second sequence of the samples. That is, two different oscillation signals that are phase shifted by 90° are used for polar modulation for the first and third se quences of samples. In other words, the DAC used for generating the in-phase or the quadra ture contribution to the RF signal for the second sequence of the samples may be used for polar modulation for the first sequence of samples, and the DAC used for generating the other one of the in-phase or a quadrature contribution to the RF signal for the second sequence of the samples may be used for polar modulation for the third sequence of samples.

Fig. 37 illustrates a scenario in which the correction starts already before the phase jump at time stamp t ₂ , so that the correction may be finished earlier. Accordingly, correction is done during smallest possible radius values.

The apparatus 3500 illustrated in Fig. 32 may be an implementation of an apparatus for gen erating a RF signal as described in connection with Figs. 34 to 37. In particular, the start of the correction as illustrated in Fig. 37 may be achieved by increasing the delay of delay ele ment 3517.

Generally speaking, some of the above examples presented in connection with Figs. 31 to 37 relate to a means for generating a RF signal based on an input signal using a modulator circuit. The means comprises a means for controlling the modulator circuit to generate the RF signal by polar modulation if the input signal exhibits a first characteristic. Further, the means com prises a means for controlling the modulator to generate the RF signal by quadrature modula tion if the input signal exhibits a second characteristic. Additionally, the means comprises a means for de-activating part of the circuitry of the modulator circuit if the input signal transits from the second characteristic to the first characteristic.

As discussed above, the second characteristic may indicate that, for a sample of the input signal, the radio frequency signal exhibits a second instantaneous frequency having a fre quency deviation from a desired carrier frequency of the radio frequency signal that is greater than a threshold value.

The means for generating a RF signal may be implemented by an apparatus for generating a RF signal described above (e.g. Figs. 31, 32 or 34). The means for controlling the modulator to generate the RF signal by quadrature modulation, the means for controlling the modulator circuit to generate the RF signal by polar modulation and the means for de-activating part of the circuitry of the modulator circuit may be implemented by a control circuit described above (e.g. Figs. 31, 32 or 34).

Some examples further relate to another means for generating a RF signal. The means com prises a means for generating the RF signal based on a plurality of samples using a modulator circuit. Further, the means comprises a means for controlling the modulator circuit to generate the RF signal by polar modulation for a first and a third sequence of the samples. The means additionally comprises a means for controlling the modulator circuit to generate the RF signal by quadrature modulation for a second sequence of the samples directly succeeding the first sequence of the samples, the third sequence of the samples directly succeeding the second sequence of the samples. Moreover, the means comprises a means for controlling the modu lator circuit to generate the RF signal with a first carrier frequency for at least one sample of the second sequence. The means also comprises a means for controlling the modulator circuit to generate the RF signal with a second carrier frequency for at least one other sample of the second sequence.

As discussed above, the first carrier frequency may correspond to a maximum phase change supported by the modulator for generating the RF signal by polar modulation.

The means for generating a RF signal may be implemented by an apparatus for generating a RF signal described above (e.g. Figs. 31, 32 or 34). The means for controlling the modulator to generate the RF signal by quadrature modulation, the means for controlling the modulator circuit to generate the RF signal by polar modulation, the means for controlling the modulator circuit to generate the radio frequency signal with a first carrier frequency and the means for controlling the modulator circuit to generate the radio frequency signal with a second carrier frequency may be implemented by a control circuit described above (e.g. Figs. 31, 32 or 34).

An example of an implementation using an apparatus for generating a RF signal according to one or more aspects of the proposed architecture or one or more examples described above is illustrated in Fig. 38. Fig. 38 schematically illustrates an example of a mobile device 4100 (e.g. mobile phone, smartphone, tablet-computer, or laptop) comprising an apparatus 4110 for generating a RF signal according to an example described herein. For example, a transmitter 4120 may comprise the apparatus 4110 for generating a RF signal. At least one antenna element 4130 of the mobile device 4100 may be coupled to the transmit ter 3220.

To this end, a mobile device may be provided enabling low power and high bandwidth signal transmission.

The proposed RF signal generation technique is not limited to mobile devices. The RF signal generation technique may be used in any electronic device for generating RF transmit signals.

An example of a method 4200 for generating a RF signal based on an input signal using a modulator circuit is illustrated by means of a flowchart in Fig. 39. The method 4200 com prises controlling 4202 the modulator circuit to generate the RF signal by polar modulation if the input signal exhibits a first characteristic. If the input signal exhibits a second character istic, the method 4200 comprises controlling 4204 the modulator circuit to generate the RF signal by quadrature modulation. The method 4200 further comprises de-activating 4206 part of the circuitry of the modulator circuit if the input signal transits from the second character istic to the first characteristic.

More details and aspects of the method are mentioned in connection with the proposed tech nique or one or more examples described above (e.g. Figs. 31 - 37). The method may comprise one or more additional optional features corresponding to one or more aspects of the proposed technique or one or more examples described above.

An example of another method 4300 for generating a RF signal is illustrated by means of a flowchart in Fig. 40. The method 4300 comprises generating 4302 the RF signal based on a plurality of samples using a modulator circuit. Further, the method 4300 comprises control ling 4304 the modulator circuit to generate the RF signal by polar modulation for a first and a third sequence of the samples. The method 4300 additionally comprises controlling 4306 the modulator circuit to generate the RF signal by quadrature modulation for a second se quence of the samples directly succeeding the first sequence of the samples. The third se quence of the samples directly succeeds the second sequence of the samples. In addition, the method 4300 comprises controlling 4308 the modulator circuit to generate the RF signal with a first carrier frequency for at least one sample of the second sequence, and controlling 4310 the modulator circuit to generate the RF signal with a second carrier frequency for at least one other sample of the second sequence.

More details and aspects of the method are mentioned in connection with the proposed tech nique or one or more examples described above (e.g. Figs. 31 - 37). The method may comprise one or more additional optional features corresponding to one or more aspects of the proposed technique or one or more examples described above.

Another modulation technique is presented in the following with reference to Figs. 41 to 50.

Fig. 41 illustrates apparatus 4400 for generating a RF signal 4421. The apparatus 4400 com prises a modulator circuit 4410 configured to generate a first contribution 4410 to the RF signal 4421 by polar modulation. Further, modulator circuit 4410 is configured to (simulta neously/concurrently) generate a second contribution 4412 to the RF signal 4421 by quadra ture modulation 4421. The apparatus 4400 additionally comprises a signal combiner 4420 configured to combine the first contribution 4411 to the RF signal 4421 and the second con tribution 4412 to the RF signal 4421. The signal combiner 4420 outputs the RF signal 4421.

Apparatus 4400 may enable a combined modulation approach combining advantages of quad rature and polar modulation, while avoiding at least some of the drawbacks of both modula tion techniques.

For example, the modulator circuit 4410 may comprise a first DAC (not illustrated) config ured to generate the first contribution 4411 to the RF signal 4421.

Further, the modulator circuit 4410 may comprise a phase modulator (not illustrated) config ured to shift a phase of a first oscillation signal for the first DAC by a phase shift value based on a phase difference between a phase of a second complex-valued symbol and a phase value related to a first complex-valued symbol. The second complex-valued symbol succeeds the first complex-valued symbol. Furthermore, the phase shift value is limited to a predetermined value range.

The modulator circuit 4410 may additionally comprise a processing circuit (not illustrated) configured to generate a first control signal for the first DAC indicative of an amplitude (e.g. minimum distance to the origin) of an orthogonal projection of the second complex-valued symbol onto a radially extending line in the constellation diagram that indicates the sum of the phase shift value and the phase value related to the first complex-valued symbol

The phase value related to the first complex-valued symbol may be based on accumulated phase shift values related to the first and further preceding complex-valued symbols. That is, the phase value related to the first complex-valued symbol may be the sum of the phase shift values calculated by apparatus 4400 for the complex-valued symbols that precede the second complex-valued symbol. The accumulated phase shift values of the preceding complex-val ued symbols may, hence, represent the effective phase used by the modulator circuit 4410 for generating the first contribution 4411 to the RF signal 4421 based on the first complex-valued symbol (i.e. the current phase of the oscillation signal used for generating the first contribution 4411 to the RF signal 4421 based on the first complex- valued symbol).

The modulator circuit may further comprise a second DAC configured to generate the second contribution 4412 to the RF signal 4421. The phase modulator may be further configured to generate a pair of orthogonal second oscillation signals with constant phase for the second DAC. Further, the processing circuit may be configured to generate a second control signal for the second DAC indicative of an in-phase component and a quadrature component. The in-phase component and the quadrature component are based on a difference between the second complex-valued symbol and the orthogonal projection of the second complex-valued symbol onto the radially extending line.

This may become more evident from Fig. 42. Fig. 42 illustrates a constellation diagram (com plex pointer diagram) 4500. The abscissa denotes the in-phase component of a complex-val ued symbol, whereas the ordinate denotes the quadrature component of the complex-valued symbol.

A first pointer 4510 indicates the position of the first complex-valued symbol C^^in the con stellation diagram 4500. A second pointer 4520 indicates the position of the second complex valued symbol C _n in the constellation diagram 4500.

The effective phase of the first complex-valued symbol C _n-1 as used by apparatus 4400 is F _h-ΐ i.e. the phase value related to the first complex-valued symbol C _{n- 1} is F _h _i· The phase of the second complex- valued symbol C _n is F _h . That is, the phase difference between the phase of the second complex-valued symbol C _n and the phase value related to the first com plex-valued symbol

In order to enable a limited phase modulation, the phase shift value DF _{5aί h} by which the oscillation signal is phase shifted is limited to a predetermined value range. In other words, the phase shift value DF _{5aί n} is limited to a maximum (saturated) value within the predeter mined value range if the phase difference DF _h|h-1 is greater than the maximum value. In Fig. 42, the phase difference Df _h|h-1 is greater than the maximum value for the phase shift value AF sa _{t ,} n- Accordingly, the phase shift value DF _{5aί n} is limited to the maximum value, i.e. the value within the predetermined value range that is closest to the phase difference DF _h|h-1 . This may, e.g., be done by the processing circuit of modulator circuit 4410. If the phase dif ference DF _h|h-1 was smaller than the maximum value for the phase shift value DF _{5aί n} , no limitation (saturation) of the phase shift value DF _{5aί h} would be required. For example, the processing circuit may generate, based on the phase difference DF _h|h-1 , a phase control sig nal for the phase modulator indicative of the phase shift value DF _{5aί n} .

It is to be noted that the predetermined valuable range for the phase shift value DF _{5aί n} , i.e. the maximum value of DF _{5aί n} may be adjustable.

Fig. 42 further illustrates the effect of shifting the phase of the first oscillation signal. The initial phase of the first oscillation signal is equal to F _h _i, i.e. the phase value related to the first complex-valued symbol C _n-1 . By shifting the initial phase F _h-! of the oscillation signal by DF _{5aί n} , the phase of the first oscillation signal for the second complex-valued symbol C _n

The amplitude A _Sat used for polar modulation is determined by orthogonally projecting the second complex-valued symbol C _n onto the radially extending line 4530 in the constellation diagram 4500. It is evident from Fig. 42 that line 4530 indicates (represents) the sum of the phase shift value DF _{5aί h} and the effective phase F _h-! of the first complex-valued symbol C _{n- 1} as used by apparatus 4400, i.e. the phase value related to the first complex-valued sym bol C _n-x . Accordingly, the imaginary complex-valued symbol C _Aux with amplitude A _Sat and phase F _5aί represents the first contribution 4411 to the RF signal 4421.

The difference between the imaginary complex-valued symbol C _Aux and the second complex valued symbol C _n is compensated for by quadrature modulation, i.e. the second contribution 4412 to the RF signal 4421.

Therefore, an in-phase component I _Aux and a quadrature component Q _Aux are calculated based on the difference between the second complex-valued symbol C _n and the orthogonal projection of the second complex-valued symbol C _n onto the radially extending line 4530, which is represented by imaginary complex- valued symbol C _Aux .

The basic concept of this modulation approach is similar to that described in connection with Figs. 1 to 30. A saturated phase change is achieved through phase modulation with a corre sponding hybrid in-phase component (here: the polar amplitude A _Sat , i.e. the orthogonal pro jection of the second complex-valued symbol C _n onto the radially extending line 4530). How ever, the residual phase change is not done through a quadrature component relative to the phase-modulated in-phase component (i.e. the polar amplitude) but through (auxiliary) in- phase and quadrate components I _Aux and Q _Aux without phase modulation (since the second oscillation signals exhibit constant phase). As described above, the addition of the polar am plitude and the auxiliary in-phase and quadrate components may be done using two DACs (e.g. RF-DACs) in parallel.

In summarizing the above, Fig. 42 illustrates an example for realizing a phase change from a complex vector C _{n- 1} to a complex vector C _n using the following steps:

1) If the phase change exceeds a maximum value (as illustrated in Fig. 42), the phase change is saturated to this maximum value.

2) The amplitude and the phase of the resulting saturated vector (amplitude A _Sat and phase F _5aί ) arc realized through polar modulation. As described above, the amplitude A _Sat is ob tained from the normal projection the complex vector C _n onto the line corresponding to the saturated phase F _5aί (e.g. using a rotation CORDIC algorithm).

3) The residual phase change is realized through quadrature modulation using the auxiliary in-phase and quadrature components I _Aux and Q _Aux . Steps 1) and 2) are similar to the modulation approach described in connections with Figs. 1 to 30, but step 3) is different: No quadrature component is generated relative to the phase modulated amplitude A _Sat .

In essence, Fig. 42 illustrates an example, in which polar modulation and quadrature modula tion are done in parallel in order to generate two contributions for a RF signal. As described above, the resulting vectors (representing the contributions to the RF signal) may be added in (RF-)DACs.

While some basic principles for generating a RF signal according to the present technique were described above in connection with Figs. 41 and 42, a more detailed example of an apparatus for generating a RF signal according to the proposed technique is described in the following in connection with Figs 43 to 48.

Fig. 43 illustrates an example 4600 for generating an RF signal 4601.

Apparatus 4600 comprises a first (main) DAC 4610 and a second (auxiliary) DAC 4620. The first DAC 4610 and the second DAC 4620 may be implemented as individual DACs or as, e.g., separate arrays of a single DAC (e.g. as a small and a large capacitive array of a RF- DAC).

Furthermore, apparatus 4600 comprises a phase modulator implemented as DTC 4630. DTC

4630 receives a reference oscillation signal from an oscillation-generation circuit such as DPLL 4640. The reference oscillation signal is unmodulated and exhibits a frequency which is a (fractional or integer) multiple of the desired carrier frequency of the RF signal 4601 (i.e. fw. _re f = N * f _TX with N being an integer or a fractional number). As indicated in Fig. 43, the reference oscillation signal may be routed to the DTC 4630 through a Local Oscillator PAth (LOPA) 4650.

DTC 4630 comprises a Multi-Modulus Divider (MMD) 4631 and a phase interpolator 4632 (e.g. a digitally controlled edge interpolator) for coarse and fine phase modulation. MMD

4631 generates a first oscillation signal for the first DAC 4610 with reduced frequency from the reference oscillation signal. Phase interpolator 4632 shifts the phase of the first oscillation signal for the first DAC 4610 by the phase shift value DF _{5aί n} to the saturated phase <t> _5at . In the example of Fig. 43, it is illustrated that the phase control signal 4633 for DTC 4630 indi cates the absolute phase F _5aί (which indirectly indicates the phase shift value DF _{5aί h} ). In other examples, the phase control signal 4633 may alternatively indicate the phase shift value AF sa _{t ,} n- The phase shift value DF _{5aί h} as well as the saturated phase F _5aί are determined (calculated) by a processing circuit of apparatus 4600 as described below in connection with Fig. 44. The phase shifted first oscillation signal 4634 is supplied to the first DAC 4610.

Further, MMD 4631 generates a pair of orthogonal second oscillation signals 4635, 4636 with constant phase (i.e. unmodulated second oscillation signals) for the second DAC 4620. The frequency of the pair of orthogonal second oscillation signals 4635, 4636 is equal to the fre quency of the phase shifted first oscillation signal 4634.

The first DAC 4610 further receives a first control signal 4611 indicative of the amplitude A sa _t °f the orthogonal projection of the second complex-valued symbol C _n onto the radially extending line in the constellation diagram that indicates the sum of the phase shift value AF sa _, n and the effective phase F _h-! of the first complex-valued symbol C _n-1 as used by apparatus 4600, i.e. the phase value related to the first complex-valued symbol C _n-1 .

The second DAC 4620 receives a second control signal 4621 indicative of the in-phase com ponent I _Aux and the quadrature component Q _Aux . The in-phase component I _Aux and the quad rature component Q _Aux are based on a difference between the second complex-valued symbol C _n and the orthogonal projection of the second complex-valued symbol onto the radially ex tending line.

The first control signal 4611 as well as the second control signal 4621 are determined (calcu lated) by the processing circuit of apparatus 4600 as described below in connection with Fig. 44.

Accordingly, the first DAC 4610 generates a first contribution to the RF signal 4601, which is based on polar modulation. The second DAC 4620 generates a second contribution to the RF signal 4602, which is based on quadrature modulation.

The proposed modulation technique may allow to limit phase jumps at DTC 4630. This is favorable since big phase jumps at the DTC may cause impairments on the oscillation signals output by the DTC. In particular, the impairments may be dynamic nonlinearities caused by, e.g., MMD switching effects or charge sharing in the phase interpolator (e.g. when imple mented as digitally controlled edge interpolator). The limited phase jumps at the DTC 4630 may, hence, prevent modulation distortion.

In other words, the main (RF-)DAC 4610 is controlled by the saturated polar amplitude A _Sat and receives the phase-modulated oscillation signal from the DTC 4630. The phase F _5aί ap plied to the DTC 4630 has limited phase jumps to prevent modulation distortion (e.g. reduced MMD switching). The auxiliary (RF-)DAC 4620 is controlled by I _Aux and Q _Aux and receives the unmodulated oscillation signals 4635 and 4636, which are in quadrature.

Fig. 44 illustrates an exemplary implementation of a processing circuit 4700 for apparatus 4600, which is based on CORDIC algorithms. For the sake of clarity, a constellation diagram is illustrated in the left part of Fig. 44. The constellation diagram illustrates the relation be tween the individual quantities processed or calculated by processing circuit 4700.

A digital front-end 4790 provides the second complex-valued symbol C _n in quadrature repre sentation, i.e. by its in-phase component I _n and its quadrature component Q _n . Processing cir cuit 4700 uses a vector CORDIC algorithm 4710 to determine (calculate) the phase F _h of the second complex-valued symbol C _n . Then, a subtractor 4720 is used to determine the phase difference between the phase F _h of the second complex-valued symbol C _n and the effective phase _5M,h -i °f the first complex-valued symbol C _n-· , as used by DTC 4630, i.e. the phase value related to the first complex-valued symbol C _n-1 .

The processing circuit 4700 further comprises a saturator 4730 which receives the phase dif ference. The saturator 4730 outputs the phase shift value DF _{5aί n} for shifting the current phase of the first oscillation signal. The phase shift value DF _{5aί n} is limited to a maximum value. In other words, the phase F _h of the second complex-valued symbol C _n runs through a saturation loop which limits phase jumps to a maximum phase shift value DF _{5aί n} .

By means of adder 4740, the phase shift value DF _{5aί n} is added to the effective phase F^ _,h -i of the first complex-valued symbol C _n-1 as used by DTC 4630, i.e. the phase value related to the first complex-valued symbol C _ri-1 , in order to output the saturated phase F _{5aί n} for the second complex-valued symbol C _n . The saturated phase F _{5aί n} is supplied (fed) to the DTC 4630. As described above, processing circuit 4700 may alternatively also supply (feed) the phase shift value DF _{5aί n} to the DTC 4630.

A first rotation CORDIC algorithm 4750 is used by processing circuit 4700 to determine (cal culate) the polar amplitude A _{Sat n} for the second complex-valued symbol C _n based on the in- phase component I _n and the quadrature component Q _n of the second complex-valued symbol C _n as well as the saturated phase F _{5aί n} . This is done by orthogonally projecting the second complex-valued symbol C _n onto the radially extending line that indicates (represents) the sat urated phase F _{5aί n} . The polar amplitude A _{Sat n} is supplied to the first DAC 4610 via the first control signal.

A second rotation CORDIC algorithm 4760 is used by processing circuit 4700 to determine (calculate) the in-phase component l _Sat, n and the quadrature component Qsa _t .n °f the orthog onal projection of the second complex-valued symbol C _n onto the radially extending line. These components are subtracted from the in-phase component I _n and the quadrature compo nent Q _n of the second complex-valued symbol C _n by means of subtractors 4770 and 4780 in order to generate the in-phase component I _{Aux n} and a quadrature component Q _Au x _, n for the second DAC 4620. The in-phase component I _Aux and a quadrature component Q _Aux are sup plied to the second DAC 4620 via the second control signal.

It is to be noted that, when the phase changes between succeeding complex-valued symbols in the constellation diagram do not saturate, the saturated phase F _{5aί n} º F _h so that l _Sat, n = I _n and Qsa _t .n = Qn- That is, I _Aux º Q _Aux,n º 0. In other words, apparatus 4600 acts like a polar modulator (the second contribution to the RF signal 4601 is zero).

Optionally, one or more (fractional) sample rate converters may be coupled between the pro cessing circuit 4700 (the digital front-end) and the analog blocks (i.e. DTC 4630 and DACs 4610 and 4620) for signal interpolation.

By using the proposed modulation technique, the apparatus 4600 may benefit from the ad vantages of both polar and quadrature modulation. At the same time, the apparatus 4600 may avoid at least some of the disadvantages of polar and quadrature modulation. This will become more evident from the following discussion of Figs. 45 to 48. Figs. 45 to 48 illustrate various parameters of an apparatus using the proposed modulation technique. Fig. 45 illustrates a constellation diagram 4800. The abscissa denotes the in-phase component of a complex-valued symbol, whereas the ordinate denotes the quadrature component of the complex-valued symbol.

A complex trajectory 4810 comprising a plurality of complex-valued symbols is illustrated in the constellation diagram 4800. Lines 4820 illustrate the approximation of the complex tra jectory 4810 via ideal polar amplitudes. Further illustrated is the approximation of the com plex-valued symbols of the complex trajectory 4810 according to the proposed modulation technique.

The complex trajectory 4810 exhibits large phase jumps between the individual complex valued symbols. These phase jumps are saturated to the maximum according to the proposed modulation technique. Accordingly, the complex-valued symbols are approximated by corre sponding saturated polar amplitudes 4830 and a respective pair of in-phase and quadrature components 4840, 4850, if required.

The course of the ideal polar amplitudes 4820 is illustrated in Fig. 46 by line 4910. Further, the course of the saturated polar amplitudes 4830 is illustrated in Fig. 46 by line 4920.

Fig. 47 further illustrates the courses of the phase change DF of complex trajectory 4810 (represented by line 5010) and the saturated phase change DF _5aί (represented by line 5020). Further, the predetermined value range for the phase shift value DF _5aί is illustrated by lines 5030. The lines 5030 indicate the maximum value DF _{5aί Max} of the phase shift value.

It is evident from Fig. 47 that the saturated phase change according to the proposed modula tion technique, i.e. the phase shift value DF _5aί , saturates to the maximum value DF sa _{t, M} ax if the phase change DF of complex trajectory 4810 exceeds the maximum value DF _{5aί Ma} . Accordingly, the effective polar phase lags the phase of the complex trajectory 4810 as is evident from Fig. 47. The required residual trajectory movement for approximating the com plex trajectory 4810 is achieved by the pair of in-phase and quadrature components 4840, 4850 as illustrated in Fig. 45. The courses of the in-phase component 4840 (represented by line 5110) and the quadrature component 4850 (represented by line 5120) for approximating the complex trajectory 4810 in Fig. 45 is illustrated in Fig. 48. It is evident from Fig. 48 that the amplitudes of the in-phase component and/or the quadrature component increase when the phase shift value DF _5aί sat urates to the maximum value DF _{5aί Max} in Fig. 47.

Generally speaking, some of the above examples presented in connection with Figs. 41 to 48 relate to a means for generating a RF signal. The means comprises a means for generating a first contribution to the RF signal by polar modulation, and a means for generating a second contribution to the RF signal by quadrature modulation. The means further comprises a means for combining the first contribution to the RF signal and the second contribution to the RF signal.

As described above, a second complex-valued symbol may succeed a first complex-valued symbol in a constellation diagram. Accordingly, the means for generating the first contribu tion to the RF signal may comprise a means for generating the first contribution to the RF signal using a first DAC. Further, the means for generating the first contribution to the RF signal may comprise a means for shifting a phase of a first oscillation signal for the first DAC by a phase shift value based on a phase difference between a phase of the second complex valued symbol and a phase value related to the first complex-valued symbol, wherein the phase shift value is limited to a predetermined value range. Further, the means for generating the first contribution to the RF signal may comprise a means for generating a first control signal for the first DAC indicative of an amplitude of an orthogonal projection of the second complex-valued symbol onto a radially extending line in the constellation diagram that indi cates the sum of the phase shift value and the phase value related to the first complex-valued symbol.

The means for generating the second contribution to the RF signal may comprise a means for generating the second contribution to the RF signal using a second DAC. Further, the means for generating the second contribution to the RF signal may comprise a means for generating a pair of orthogonal second oscillation signals with constant phase for the second DAC. The means for generating the second contribution to the RF signal may additionally comprise a means for generating a second control signal for the second DAC indicative of an in-phase component and a quadrature component, wherein the in-phase component and the quadrature component are based on a difference between the second complex-valued symbol and the orthogonal projection of the second complex-valued symbol onto the radially extending line.

The means for generating a RF signal may be implemented by an apparatus for generating a RF signal described above (e.g. Figs. 41, 43 and 44). The means for generating the first con tribution to the RF signal and the means for generating the second contribution to the RF signal may be implemented by a modulator circuit described above (e.g. Figs. 41, 43 and 44). The means for combining the first contribution to the RF signal and the second contribution to the RF signal may be implemented by a signal combiner described above (e.g. Figs. 41, 43 and 44). The means for shifting a phase of a first oscillation signal and the means for gener ating a pair of orthogonal second oscillation signals may be implemented by a phase modula tor described above (e.g. Figs. 41, 43 and 44). The means for generating a first control signal and the means for generating a second control signal may be implemented by a processing circuit described above (e.g. Figs. 41, 43 and 44). The means for generating the first contri bution to the RF signal using a first DAC may be implemented by a DAC described above (e.g. Figs. 41, 43 and 44). The means for generating the second contribution to the RF signal using a second DAC may be implemented by a DAC described above (e.g. Figs. 41, 43 and 44).

An example of an implementation using an apparatus for generating a RF signal according to one or more aspects of the proposed architecture or one or more examples described above is illustrated in Fig. 49. Fig. 49 schematically illustrates an example of a mobile device 5200 (e.g. mobile phone, smartphone, tablet-computer, or laptop) comprising an apparatus 5210 for generating a RF signal according to an example described herein.

For example, a transmitter 5230 may comprise the apparatus 5210 for generating the RF sig nal. The transmitter 5230 may additionally comprise a power amplifier 5220 for amplifying the RF signal.

At least one antenna element 5240 of the mobile device 5200 may be coupled to the transmit ter 5230. To this end, a mobile device may be provided enabling the superior power efficiency of dig ital-polar architecture in combination with the low in-band signal distortion of digital-IQ ar chitecture.

The proposed RF signal generation technique is not limited to mobile devices. The RF signal generation technique may be used in any electronic device for generating RF transmit signals.

An example of a method 5300 for generating a RF signal is illustrated by means of a flowchart in Fig. 50. Method 5300 comprises generating 5302 a first contribution to the RF signal by polar modulation. Further, method 5300 comprises generating 5304 a second contribution to the RF signal by quadrature modulation. Method 5300 additionally comprises combining 5306 the first contribution to the RF signal and the second contribution to the RF signal.

More details and aspects of the method are mentioned in connection with the proposed tech nique or one or more examples described above (e.g. Figs. 41 - 49). The method may comprise one or more additional optional features corresponding to one or more aspects of the proposed technique or one or more examples described above.

Wireless communication circuits using apparatuses and transmitters according to the pro posed techniques or one or more of the examples described above may be configured to op erate according to one of the 3 ^rd Generation Partnership Project (3 GPP)- standardized mobile communication networks or systems. The mobile or wireless communication system may correspond to, for example, a Long-Term Evolution (LTE), an LTE- Advanced (LTE-A), High Speed Packet Access (HSPA), a Universal Mobile Telecommunication System (UMTS) or a UMTS Terrestrial Radio Access Network (UTRAN), an evolved-UTRAN (e-UTRAN), a Global System for Mobile communication (GSM) or Enhanced Data rates for GSM Evolution (EDGE) network, a GSM/EDGE Radio Access Network (GERAN). Alternatively, the wire less communication circuits may be configured to operate according to mobile communica tion networks with different standards, for example, a Worldwide Inter-operability for Micro- wave Access (WIMAX) network IEEE 802.16 or Wireless Local Area Network (WLAN) IEEE 802.11, generally an Orthogonal Frequency Division Multiple Access (OFDMA) net work, a Time Division Multiple Access (TDMA) network, a Code Division Multiple Access (CDMA) network, a Wideband-CDMA (WCDMA) network, a Frequency Division Multiple Access (FDMA) network, a Spatial Division Multiple Access (SDMA) network, etc. The examples as described herein may be summarized as follows:

Example 1 is an apparatus for driving a digital-to-analog converter based on a second com plex-valued symbol succeeding a first complex-valued symbol, the apparatus comprising: a phase modulator configured to shift a phase of an oscillation signal for the digital-to-analog converter by a phase shift value based on a phase difference between a phase of the second complex-valued symbol and a phase value related to the first complex-valued symbol, wherein the phase shift value is limited to a predetermined value range; and a processing circuit configured to generate a control signal for the digital-to-analog converter indicative of an in-phase component and a quadrature component of the second complex-valued symbol, wherein the in-phase component and the quadrature component of the second complex-valued symbol are based on the phase shift value.

In example 2, the phase value related to the first complex-valued symbol in the apparatus of example 1 is based on accumulated phase shift values related to the first and further preceding complex- valued symbols.

In example 3, the processing circuit in the apparatus of example 1 or example 2 is configured to generate, based on the phase difference, a phase control signal for the phase modulator indicative of the phase shift value, wherein the processing circuit is configured to limit the phase shift value to a value within the predetermined value range that is closest to the phase difference if the predetermined value range does not comprise the phase difference.

In example 4, the processing circuit in the apparatus of any of examples 1 to 3 is configured to calculate the in-phase component and the quadrature component of the second complex valued symbol by rotating the second complex-valued symbol about an origin of a constella tion diagram based on the phase shift value.

In example 5, the processing circuit in the apparatus of example 4 is further configured to rotate the second complex-valued symbol about the origin of the constellation diagram based on the phase value related to the first complex-valued symbol. In example 6, the processing circuit in the apparatus of example 5 is further configured to calculate the in-phase component and the quadrature component of the second complex-val ued symbol based on an expression which is mathematically correspondent to

with / ₂ denoting the in-phase component of the second complex-valued symbol, Q ₂ denoting the quadrature component of the second complex-valued symbol, I _{in 2} denoting an initial in- phase component of the second complex-valued symbol, Q _{in 2} denoting an initial quadrature component of the second complex-valued symbol, and f denoting the sum of the phase shift value and the phase value related to the first complex-valued symbol.

In example, if an absolute value of the phase difference exceeds a threshold value, the pro cessing circuit in the apparatus of any of examples 3 to 6 is configured to modify the phase difference by a phase modification value prior to further processing the phase difference, and to generate a signal indicative of the modification of the phase difference by the phase modi fication value.

In example 8, the threshold value is 90° in the apparatus of example 7, wherein the phase modification value is 180°.

In example 9, the threshold value is 45° in the apparatus of example 7, wherein the phase modification value is 90°.

In example 10, the threshold value is 135° in the apparatus of example 7, wherein the phase modification value is 180°.

In example 11, the apparatus of any of examples 1 to 10 further comprises a clock generation circuit configured to: generate, based on the oscillation signal, a plurality of second oscillation signals that are phase shifted by 90° with respect to each other; and supply, based on signs of the in-phase component and the quadrature component of the second complex-valued symbol, two of the plurality of second oscillation signals to the digital-to-analog converter as in-phase and quadrature oscillation signals. In example 12, the apparatus of any of examples 7 to 10 further comprises a clock generation circuit configured to: generate, based on the oscillation signal, a plurality of second oscillation signals that are phase shifted by 90° with respect to each other; and supply, based on signs of the in-phase component and the quadrature component of the second complex-valued symbol and based on the signal indicative of the modification of the phase difference by the phase modification value, two of the plurality of second oscillation signals to the digital-to-analog converter as in-phase and quadrature oscillation signals.

In example 13, the processing circuit in the apparatus of any of examples 7 to 12 is further configured to rotate the second complex-valued symbol about the origin of the constellation diagram based on the signal indicative of the modification of the phase difference by the phase modification value.

In example 14, the processing circuit in the apparatus of example 13 is further configured to negate a value of at least one of the in-phase component and the quadrature component of the second complex-valued symbol and/or swap the values of the in-phase component and the quadrature component of the second complex-valued symbol based on a remainder of a Eu clidian division of the phase modification value by 360°.

In example 15, the processing circuit in the apparatus of any of examples 7 to 12 is further configured to rotate the second complex-valued symbol about the origin of the constellation diagram based on only the accumulated phase shift values related to the second, the first and further preceding complex-valued symbols.

In example 16, the processing circuit in the apparatus of example 5 is further configured to rotate the second complex-valued symbol about the origin of the constellation diagram using a coordinate rotation digital computer algorithm.

In example 17, the processing circuit in the apparatus of example 16 is configured to generate a phase correction value based on an error signal output by the coordinate rotation digital computer algorithm that is indicative of a rotation error of the coordinate rotation digital com puter algorithm, wherein the phase modulator is further configured to shift the phase of the oscillation signal for the digital-to-analog converter based on the phase correction value. In example 18, the processing circuit in the apparatus of example 17 is configured to generate the phase correction value by differentiating the rotation error.

In example 19, the processing circuit in the apparatus of example 18 is configured to combine the phase shift value and the phase correction value.

In example 20, the processing circuit in the apparatus of example 19 is configured to delay, based on a processing time required for rotating the second complex-valued symbol about the origin of the constellation diagram by the coordinate rotation digital computer algorithm, the phase shift value prior to combining it with the phase correction value.

In example 21, the processing circuit in the apparatus of any of examples 16 to 20 is config ured to delay the second complex-valued symbol prior to inputting it into the coordinate ro tation digital computer algorithm based on a processing time required for calculating a phase of the second complex-valued symbol using another coordinate rotation digital computer al gorithm.

Example 22 is a transmitter comprising an apparatus for driving a digital-to-analog converter according to any of examples 1 to 21.

In example 23, the transmitter of example 22 further comprises a digital-to-analog converter configured to generate a radio frequency transmit signal based on the control signal and the oscillation signal.

Example 24 is a mobile device comprising a transmitter according to example 22 or example 23.

In example 25, the mobile device of example 24 further comprises an antenna coupled to the transmitter.

Example 26 is a method for driving a digital-to-analog converter based on a second complex valued symbol succeeding a first complex- valued symbol, the method comprising: shifting a phase of an oscillation signal for the digital-to-analog converter by a phase shift value based on a phase difference between a phase of the second complex-valued symbol and a phase value related to the first complex-valued symbol, wherein the phase shift value is limited to a predetermined value range; and generating a control signal for the digital-to-analog converter indicative of an in-phase component and a quadrature component of the second complex valued symbol, wherein the in-phase component and the quadrature component of the second complex-valued symbol are based on the phase shift value.

In example 27, the phase value related to the first complex-valued symbol in the method of example 26 is based on accumulated phase shift values related to the first and further preced ing complex-valued symbols.

In example 28, the oscillation signal in the method of example 26 or example 27 is generated using a phase modulator, wherein the method further comprises: generating, based on the phase difference, a phase control signal for the phase modulator indicative of the phase shift value; and limiting the phase shift value to a value within the predetermined value range that is closest to the phase difference if the predetermined value range does not comprise the phase difference.

In example 29, the method of any of examples 26 to 28 further comprises calculating the in- phase component and the quadrature component of the second complex-valued symbol by rotating the second complex-valued symbol about an origin of a constellation diagram based on the phase shift value.

In example 30, rotating the second complex-valued symbol about the origin of the constella tion diagram in the method of example 29 is further based on the phase value related to the first complex-valued symbol.

In example 31, calculating the in-phase component and the quadrature component of the sec ond complex-valued symbol in the method of example 30 is based on an expression which is mathematically correspondent to

with / ₂ denoting the in-phase component of the second complex-valued symbol, Q ₂ denoting the quadrature component of the second complex-valued symbol, I _{in 2} denoting an initial in- phase component of the second complex-valued symbol, Q _{in 2} denoting an initial quadrature component of the second complex-valued symbol, and f denoting the sum of the phase shift value and the phase value related to the first complex-valued symbol.

In example 32, if an absolute value of the phase difference exceeds a threshold value, the method of any of examples 28 to 31 further comprises: modifying the phase difference by a phase modification value prior to further processing the phase difference; and generating a signal indicative of the modification of the phase difference by the phase modification value.

In example 33, the threshold value is 90° in the method of example 32, wherein the phase modification value is 180°.

In example 34, the threshold value is 45° in the method of example 32, wherein the phase modification value is 90°.

In example 35, the threshold value is 135° in the method of example 32, wherein the phase modification value is 180°.

In example 36, the method of any of examples 26 to 35 further comprises: generating, based on the oscillation signal, a plurality of second oscillation signals that are phase shifted by 90° with respect to each other; and supplying, based on signs of the in-phase component and the quadrature component of the second complex-valued symbol, two of the plurality of second oscillation signals to the digital-to-analog converter as in-phase and quadrature oscillation signals.

In example 37, the method of example 36 and any of examples 32 to 35 further comprises: generating, based on the oscillation signal, a plurality of second oscillation signals that are phase shifted by 90° with respect to each other; and supplying, based on signs of the in-phase component and the quadrature component of the second complex-valued symbol and based on the signal indicative of the modification of the phase difference by the phase modification value, two of the plurality of second oscillation signals to the digital-to-analog converter as in-phase and quadrature oscillation signals. In example 38, rotating the second complex- valued symbol about the origin of the constella tion diagram in the method of any of examples 32 to 37 is further based on the signal indica tive of the modification of the phase difference by the phase modification value.

In example 39, based on a remainder of a Euclidian division of the phase modification value by 360°, the method of example 38 further comprises: negating a value of at least one of the in-phase component and the quadrature component of the second complex-valued symbol; and/or swapping the values of the in-phase component and the quadrature component of the second complex-valued symbol.

In example 40, rotating the second complex-valued symbol about the origin of the constella tion diagram in the method of example 29 and any of examples 32 to 37 is further based on only the accumulated phase shift values related to the second, the first and further preceding complex- valued symbols.

In example 41, a coordinate rotation digital computer algorithm is used for rotating the second complex-valued symbol about the origin of the constellation diagram in the method of exam ple 30.

In example 42, the method of example 42 further comprises generating a phase correction value based on an error signal output by the coordinate rotation digital computer algorithm that is indicative of a rotation error of the coordinate rotation digital computer algorithm, wherein shifting the phase of the oscillation signal for the digital-to-analog converter is further based on the phase correction value.

In example 43, generating the phase correction value in the method of example 43 comprises differentiating the rotation error.

In example 44, the method of example 43 further comprises combining the phase shift value and the phase correction value. In example 45, the method of example 44further comprises delaying, based on a processing time required for rotating the second complex-valued symbol about the origin of the constel lation diagram by the coordinate rotation digital computer algorithm, the phase shift value prior to combining it with the phase correction value.

In example 46, the method of any of examples 41 to 45 further comprises delaying the second complex-valued symbol prior to inputting it into the coordinate rotation digital computer al gorithm based on a processing time required for calculating a phase of the second complex valued symbol using another coordinate rotation digital computer algorithm.

Example 47 is a non-transitory computer readable medium having stored thereon a program having a program code for performing the method of any of examples 25 to 46, when the program is executed on a computer or processor.

Example 48 is a computer program having a program code configured to perform the method of any of examples 25 to 46, when the computer program is executed on a computer or pro cessor.

Example 49 is a means for driving a digital-to-analog converter based on a second complex valued symbol succeeding a first complex- valued symbol, the means comprising: a means for shifting a phase of an oscillation signal for the digital-to-analog converter by a phase shift value based on a phase difference between a phase of the second complex-valued symbol and a phase value related to the first complex-valued symbol, wherein the phase shift value is limited to a predetermined value range; and a means for generating a control signal for the digital-to-analog converter indicative of an in-phase component and a quadrature component of the second complex-valued symbol, wherein the in-phase component and the quadrature component of the second complex-valued symbol are based on the phase shift value.

In example 50, the phase value related to the first complex-valued symbol in the means of example 49 is based on accumulated phase shift values related to the first and further preced ing complex-valued symbols. Example 51 is an apparatus for generating a radio frequency signal, comprising: a modulator circuit configured to generate the radio frequency signal based on an input signal; and a con trol circuit configured to control the modulator circuit to generate the radio frequency signal by polar modulation if the input signal exhibits a first characteristic, and to control the mod ulator circuit to generate the radio frequency signal by quadrature modulation if the input signal exhibits a second characteristic, wherein, if the input signal transits from the second characteristic to the first characteristic, the control circuit is configured to de-activate part of the circuitry of the modulator circuit.

In example 52, the first characteristic in the apparatus of example 51 indicates that, for a sample of the input signal, the radio frequency signal exhibits a first instantaneous frequency having a frequency deviation from a desired carrier frequency of the radio frequency signal that is smaller than a threshold value.

In example 53, the second characteristic in the apparatus of example 51 or example 52 indi cates that, for a sample of the input signal, the radio frequency signal exhibits a second in stantaneous frequency having a frequency deviation from a desired carrier frequency of the radio frequency signal that is greater than a threshold value.

In example 54, if the input signal transits from the second characteristic to the first character istic, the control circuit in the apparatus of example 52 or example 53 is configured to de activate at least one of: another control circuit for a digital-to-analog converter; a control sig nal and its corresponding digital-to-analog converter signal path; a distribution circuit for dis tributing an oscillation signal to the digital-to-analog converter; and a rotation circuit for cal culating second in-phase and quadrature components based on an in-phase component and a quadrature component of the sample, and based on a combination of a phase of the sample and a phase error related to the difference between the frequency deviation and the threshold value.

In example 55, if the input signal transits from the second characteristic to the first character istic, the control circuit in the apparatus of any of examples 51 to 54 is configured to halve a divider value used by a frequency divider of the modulator circuit for generating an oscillation signal based on a reference oscillation signal. In example 56, if the input signal transits from the first characteristic to the second character istic, the control circuit in the apparatus of any of examples 51 to 55 is configured to activate the part of the circuitry of the modulator circuit.

In example 57, if the input signal transits from the first characteristic to the second character istic, the control circuit in the apparatus of any of examples 51 to 56 is configured to double a divider value used by a frequency divider of the modulator circuit for generating phase shifted oscillation signals for a digital-to-analog converter based on a reference oscillation signal.

In example 58, the input signal in the apparatus of any of examples 51 to 57 comprises infor mation on an in-phase component and a quadrature component of a sample, wherein the mod ulator circuit comprises a processing circuit configured to calculate a phase of the sample based on the in-phase component and the quadrature component, and wherein the processing circuit is configured to calculate an instantaneous frequency of the radio frequency signal for the sample based on the phase of the sample.

In example 59, the processing circuit in the apparatus of example 58 is configured to generate a signal indicative of a frequency deviation of the instantaneous frequency of the radio fre quency signal for the sample to a desired carrier frequency of the radio frequency signal, wherein, if the frequency deviation is greater than a threshold value, the processing circuit is configured to generate the signal indicative of the frequency deviation such that the indicated frequency deviation is limited to the threshold value.

In example 60, an oscillation generator of the modulator in the apparatus of example 59 is configured to generate a reference oscillation signal based on the signal indicative of the fre quency deviation.

In example 61, the processing circuit in the apparatus of example 59 or example 60 is config ured to calculate a phase error related to the difference between the frequency deviation and the threshold value.

In example 62, prior to generating the signal indicative of the frequency deviation, the pro cessing circuit in the apparatus of example 61 is configured to combine a signal indicative of the instantaneous frequency of the radio frequency signal for the sample with a number of least significant bits of a phase error for a preceding sample.

In example 63, the control circuit in the apparatus of example 61 or example 62 is configured to control the modulator to generate the radio frequency signal by polar modulation or quad rature modulation based on the phase error.

In example 64, the control circuit in the apparatus of any of examples 61 to 63 is configured to control, based on a number of most significant bits of the phase error, the oscillation gen erator to generate from the reference oscillation signal a single oscillation signal, or a pair of oscillation signals which are phase shifted by 90° with respect to each other for a digital-to- analog converter.

In example 65, the control circuit in the apparatus of any of examples 61 to 64 is configured to control, based on a number of most significant bits of the phase error, the modulator circuit to shift a phase of the in-phase component and/or the quadrature component of the sample by a 90° or a multiple thereof.

In example 66, the apparatus of any of examples 60 to 65 further comprises a delay element configured to delay the supply of the signal indicative of the frequency deviation to the oscil lation generator.

Example 67 is an apparatus for generating a radio frequency signal, comprising: a modulator circuit configured to generate the radio frequency signal based on a plurality of samples; and a control circuit configured to control the modulator circuit to generate the radio frequency signal by polar modulation for a first and a third sequence of the samples, and to generate the radio frequency signal by quadrature modulation for a second sequence of the samples di rectly succeeding the first sequence of the samples, the third sequence of the samples directly succeeding the second sequence of the samples, wherein the control circuit is configured to control the modulator circuit to generate the radio frequency signal with a first carrier fre quency for at least one sample of the second sequence, and to generate the radio frequency signal with a second carrier frequency for at least one other sample of the second sequence. In example 68, the first carrier frequency in the apparatus of example 67 corresponds to a maximum phase change supported by the modulator circuit for generating the radio frequency signal by polar modulation.

In example 69, the second carrier frequency in the apparatus of example 68 is based on a phase difference between a phase difference between the last sample of the first sequence of the samples and the first sample of the third sequence of the samples, and the summed phase change for the samples of the second sequence of the samples transmitted with the first carrier frequency.

In example 70, the modulator circuit in the apparatus of any of examples 67 to 69 is configured to use a first oscillation signal for generating the radio frequency signal for the first sequence of the samples, and to use a second oscillation signal for generating the radio frequency signal for the third sequence of the samples, wherein the first oscillation signal is used for generating an in-phase or a quadrature contribution to the radio frequency signal for the second sequence of the samples, and wherein the second oscillation signal is used for generating the other one of the in-phase or the quadrature contribution to the radio frequency signal for the second sequence of the samples.

Example 71 is a transmitter comprising an apparatus for generating a radio frequency signal according to any of example 51 to 66, or the apparatus for generating a radio frequency signal according to any of example 67 to 70.

Example 72 is a mobile device comprising a transmitter according to example 71.

In example 73, the mobile device of example 72 further comprises an antenna coupled to the transmitter.

Example 74 is a method for generating a radio frequency signal based on an input signal using a modulator circuit, comprising: controlling the modulator circuit to generate the radio fre quency signal by polar modulation if the input signal exhibits a first characteristic; controlling the modulator circuit to generate the radio frequency signal by quadrature modulation if the input signal exhibits a second characteristic; and, if the input signal transits from the second characteristic to the first characteristic, de-activating part of the circuitry of the modulator circuit.

In example 75, the first characteristic in the method of example 74 indicates that, for a sample of the input signal, the radio frequency signal exhibits a first instantaneous frequency having a frequency deviation from a desired carrier frequency of the radio frequency signal that is smaller than a threshold value.

In example 76, the second characteristic in the method of example 74 or example 75 indicates that, for a sample of the input signal, the radio frequency signal exhibits a second instantane ous frequency having a frequency deviation from a desired carrier frequency of the radio frequency signal that is greater than a threshold value.

In example 77, wherein de-activating part of the circuitry of the modulator circuit in the method of example 75 or example 76 comprises de-activating at least one of: another control circuit for a digital-to-analog converter; a control signal and its corresponding digital-to-ana- log converter signal path; a distribution circuit for distributing an oscillation signal to the digital-to-analog converter; and a rotation circuit for calculating second in-phase and quadra ture components based on an in-phase component and a quadrature component of the sample, and based on a combination of a phase of the sample and a phase error related to the difference between the frequency deviation and the threshold value.

In example 78, if the input signal transits from the second characteristic to the first character istic, the method of any of examples 74 to 77 further comprises halving a divider value used by a frequency divider of the modulator circuit for generating phase shifted oscillation signals based on a reference oscillation signal.

In example 79, if the input signal transits from the first characteristic to the second character istic, the method of any of examples 74 to 78 further comprises activating the part of the circuitry of the modulator circuit.

In example 80, if the input signal transits from the first characteristic to the second character istic, the method of any of examples 74 to 79 further comprises doubling a divider value used by a frequency divider of the modulator circuit for generating an oscillation signal for a digi- tal-to-analog converter based on a reference oscillation signal.

In example 81, the input signal in the method of any of examples 74 to 80 comprises infor mation on an in-phase component and a quadrature component of a sample, wherein the method further comprises calculating a phase of the sample based on the in-phase component and the quadrature component, and wherein the method further comprises calculating an in stantaneous frequency of the radio frequency signal for the sample based on the phase of the sample.

In example 82, the method of example 81 further comprises generating a signal indicative of a frequency deviation of the instantaneous frequency of the radio frequency signal for the sample to a desired carrier frequency of the radio frequency signal, wherein, if the frequency deviation is greater than a threshold value, the method further comprises generating the signal indicative of the frequency deviation such that the indicated frequency deviation is limited to the threshold value.

In example 83, the method of example 82 further comprises generating, using a oscillation generator, a reference oscillation signal based on the signal indicative of the frequency devi ation.

In example 84, the method of example 82 or example 83 further comprises calculating a phase error related to the difference between the frequency deviation and the threshold value.

In example 85, prior to generating the signal indicative of the frequency deviation, the method of example 84 comprises combining a signal indicative of the instantaneous frequency of the radio frequency signal for the sample with a number of least significant bits of a phase error for a preceding sample.

In example 86, the method of example 84 or example 85 further comprises controlling the modulator to generate the radio frequency signal by polar modulation or quadrature modula tion based on the phase error. In example 87, the method of any of examples 84 to 86 further comprises controlling, based on a number of most significant bits of the phase error, the oscillation generator to generate from the reference oscillation signal a single oscillation signal, or a pair of oscillation signals which are phase shifted by 90° with respect to each other for a digital-to-analog converter.

In example 88, the method of any of examples 84 to 87 further comprises controlling, based on a number of most significant bits of the phase error, the modulator circuit to shift a phase of the in-phase component and/or the quadrature component of the sample by a 90° or a mul tiple thereof.

In example 89, the method of any of examples 83 to 88 further comprises delaying the supply of the signal indicative of the frequency deviation to the oscillation generator.

Example 90 is a method for generating a radio frequency signal, comprising: generating the radio frequency signal based on a plurality of samples using a modulator circuit; controlling the modulator circuit to generate the radio frequency signal by polar modulation for a first and a third sequence of the samples; controlling the modulator circuit to generate the radio frequency signal by quadrature modulation for a second sequence of the samples directly suc ceeding the first sequence of the samples, the third sequence of the samples directly succeed ing the second sequence of the samples; controlling the modulator circuit to generate the radio frequency signal with a first carrier frequency for at least one sample of the second sequence; and controlling the modulator circuit to generate the radio frequency signal with a second carrier frequency for at least one other sample of the second sequence.

In example 91, the first carrier frequency in the method of example 90 corresponds to a max imum phase change supported by the modulator circuit for generating the radio frequency signal by polar modulation.

In example 92, the second carrier frequency in the method of example 91 is based on a phase difference between a phase difference between the last sample of the first sequence of the samples and the first sample of the third sequence of the samples, and the summed phase change for the samples of the second sequence of the samples transmitted with the first carrier frequency. In example 93, the modulator circuit in the method of any of examples 90 to 92 uses a first oscillation signal for generating the radio frequency signal for the first sequence of the sam ples, and a second oscillation signal for generating the radio frequency signal for the third sequence of the samples, wherein the first oscillation signal is used for generating an in-phase or a quadrature contribution to the radio frequency signal for the second sequence of the sam ples, and wherein the second oscillation signal is used for generating the other one of the in- phase or the quadrature contribution to the radio frequency signal for the second sequence of the samples.

Example 94 is a non-transitory computer readable medium having stored thereon a program having a program code for performing the method of any of examples 74 to 89 or the method any of examples 90 to 93, when the program is executed on a computer or processor.

Example 95 is a computer program having a program code configured to perform the method of any of examples 74 to 89 or the method any of examples 90 to 93, when the computer program is executed on a computer or processor.

Example 96 is a means for generating a radio frequency signal based on an input signal using a modulator circuit, comprising: a means for controlling the modulator circuit to generate the radio frequency signal by polar modulation if the input signal exhibits a first characteristic; a means for controlling the modulator to generate the radio frequency signal by quadrature modulation if the input signal exhibits a second characteristic; and a means for de-activating part of the circuitry of the modulator circuit if the input signal transits from the second char acteristic to the first characteristic.

In example 97, the second characteristic in the means of example 96 indicates that a sample of the input signal exhibits a second instantaneous frequency having a frequency deviation from a desired carrier frequency of the radio frequency signal that is greater than a threshold value.

Example 98 is a means for generating a radio frequency signal, comprising: a means for gen erating the radio frequency signal based on a plurality of samples using a modulator circuit; a means for controlling the modulator circuit to generate the radio frequency signal by polar modulation for a first and a third sequence of the samples; a means for controlling the modu lator circuit to generate the radio frequency signal by quadrature modulation for a second sequence of the samples directly succeeding the first sequence of the samples, the third se quence of the samples directly succeeding the second sequence of the samples; a means for controlling the modulator circuit to generate the radio frequency signal with a first carrier frequency for at least one sample of the second sequence; and a means for controlling the modulator circuit to generate the radio frequency signal with a second carrier frequency for at least one other sample of the second sequence.

In example 99, the first carrier frequency in the means of example 98 corresponds to a maxi mum phase change supported by the modulator circuit for generating the radio frequency signal by polar modulation.

Example 100 is an apparatus for generating a radio frequency signal, comprising: a modulator circuit configured to generate a first contribution to the radio frequency signal by polar mod ulation and to generate a second contribution to the radio frequency signal by quadrature modulation; and a signal combiner configured to combine the first contribution to the radio frequency signal and the second contribution to the radio frequency signal.

In example 101, a second complex- valued symbol succeeds a first complex- valued symbol, and wherein the modulator circuit in the apparatus of example 100 comprises: a first digital- to-analog converter configured to generate the first contribution to the radio frequency signal; a phase modulator configured to shift a phase of a first oscillation signal for the first digital- to-analog converter by a phase shift value based on a phase difference between a phase of the second complex-valued symbol and a phase value related to the first complex-valued symbol, wherein the phase shift value is limited to a predetermined value range; and a processing circuit configured to generate a first control signal for the first digital-to-analog converter indicative of an amplitude of an orthogonal projection of the second complex-valued symbol onto a radially extending line in the constellation diagram that indicates the sum of the phase shift value and the phase value related to the first complex-valued symbol.

In example 102, the phase value related to the first complex-valued symbol in the apparatus of example 101 is based on accumulated phase shift values related to the first and further preceding complex-valued symbols. In example 103, the processing circuit in the apparatus of example 101 or example 102 is configured to generate, based on the phase difference, a phase control signal for the phase modulator indicative of the phase shift value, wherein the processing circuit is configured to limit the phase shift value to a value within the predetermined value range that is closest to the phase difference if the predetermined value range does not comprise the phase difference.

In example 104, the modulator circuit in the apparatus of any of examples 101 to 103 further comprises a second digital-to-analog converter configured to generate the second contribution to the radio frequency signal, wherein the phase modulator is further configured to generate a pair of orthogonal second oscillation signals with constant phase for the second digital-to- analog converter, and wherein the processing circuit is further configured to generate a second control signal for the second digital-to-analog converter indicative of an in-phase component and a quadrature component, the in-phase component and the quadrature component being based on a difference between the second complex-valued symbol and the orthogonal projec tion of the second complex-valued symbol onto the radially extending line.

In example 105, the processing circuit in the apparatus of example 104 is further configured to calculate at least one of the phase shift value, the in-phase component, the quadrature com ponent and the orthogonal projection of the second complex-valued symbol onto the radially extending line using a coordinate rotation digital computer algorithm.

In example 106, the phase modulator in the apparatus of any of examples 101 to 105 is a digital-to-time converter.

In example 107, the digital-to-time converter in the apparatus of example 106 is configured to generate the first oscillation signal based on a reference oscillation signal, the reference oscillation signal having a higher frequency than the first oscillation signal.

Example 108 is a transmitter comprising an apparatus for generating a radio frequency signal according to any of examples 100 to 107.

In example 109, the transmitter of example 108 further comprises a power amplifier config ured to amplify the radio frequency signal. Example 110 is a mobile device comprising a transmitter according to example 108 or exam ple 109.

In example 111, the mobile device of example 110 further comprises an antenna coupled to the transmitter.

Example 112 is a method for generating a radio frequency signal, comprising: generating a first contribution to the radio frequency signal by polar modulation; generating a second con tribution to the radio frequency signal by quadrature modulation; and combining the first con tribution to the radio frequency signal and the second contribution to the radio frequency signal.

In example 113, a second complex- valued symbol succeeds a first complex- valued symbol, wherein generating the first contribution to the radio frequency signal in the method of exam ple 112 comprises: generating the first contribution to the radio frequency signal using a first digital-to-analog converter; shifting a phase of a first oscillation signal for the first digital-to- analog converter by a phase shift value based on a phase difference between a phase of the second complex-valued symbol and a phase value related to the first complex-valued symbol, wherein the phase shift value is limited to a predetermined value range; and generating a first control signal for the first digital-to-analog converter indicative of an amplitude of an orthog onal projection of the second complex-valued symbol onto a radially extending line in the constellation diagram that indicates the sum of the phase shift value and the phase value re lated to the first complex-valued symbol.

In example 114, wherein the phase value related to the first complex-valued symbol in the method of example 113 is based on accumulated phase shift values related to the first and further preceding complex-valued symbols.

In example 115, the oscillation signal is generated using a phase modulator, wherein generat ing a first contribution to the radio frequency signal in the method of example 113 or example 114 comprises: generating, based on the phase difference, a phase control signal for the phase modulator indicative of the phase shift value; and limiting the phase shift value to a value within the predetermined value range that is closest to the phase difference if the predeter mined value range does not comprise the phase difference.

In example 116, generating the second contribution to the radio frequency signal in the method of any of examples 113 to 115 comprises: generating the second contribution to the radio frequency signal using a second digital-to-analog converter; generating a pair of orthog onal second oscillation signals with constant phase for the second digital-to-analog converter; and generating a second control signal for the second digital-to-analog converter indicative of an in-phase component and a quadrature component, the in-phase component and the quad rature component being based on a difference between the second complex-valued symbol and the orthogonal projection of the second complex-valued symbol onto the radially extend ing line.

In example 117, at least one of the phase shift value, the in-phase component, the quadrature component and the orthogonal projection of the second complex-valued symbol onto the ra dially extending line is calculated in the method of example 116 using a coordinate rotation digital computer algorithm.

In example 118, the phase modulator in the method of any of examples 113 to 117 is a digital- to-time converter.

In example 119, the method of example 118 further comprises generating, using the digital- to-time converter, the first oscillation signal based on a reference oscillation signal, the refer ence oscillation signal having a higher frequency than the first oscillation signal.

Example 120 is a means for generating a radio frequency signal, comprising: a means for generating a first contribution to the radio frequency signal by polar modulation; a means for generating a second contribution to the radio frequency signal by quadrature modulation; and a means for combining the first contribution to the radio frequency signal and the second contribution to the radio frequency signal.

In example 121, a second complex-valued symbol succeeds a first complex- valued symbol in a constellation diagram, and wherein the means for generating the first contribution to the radio frequency signal in the means of example 120 comprises: a means for generating the first contribution to the radio frequency signal using a first digital-to-analog converter; a means for shifting a phase of a first oscillation signal for the first digital-to-analog converter by a phase shift value based on a phase difference between a phase of the second complex valued symbol and a phase value related to the first complex-valued symbol, wherein the phase shift value is limited to a predetermined value range; and a means for generating a first control signal for the first digital-to-analog converter indicative of an amplitude of an orthog onal projection of the second complex-valued symbol onto a radially extending line in the constellation diagram that indicates the sum of the phase shift value and the phase value re lated to the first complex-valued symbol.

In example 122, the means for generating the second contribution to the radio frequency sig nal in the means of example 121 comprises: a means for generating the second contribution to the radio frequency signal using a second digital-to-analog converter; a means for generat ing a pair of orthogonal second oscillation signals with constant phase for the second digital- to-analog converter; and a means for generating a second control signal for the second digital- to-analog converter indicative of an in-phase component and a quadrature component, the in- phase component and the quadrature component being based on a difference between the second complex-valued symbol and the orthogonal projection of the second complex-valued symbol onto the radially extending line.

The aspects and features mentioned and described together with one or more of the previously detailed examples and figures, may as well be combined with one or more of the other exam ples in order to replace a like feature of the other example or in order to additionally introduce the feature to the other example.

Examples may further be or relate to a computer program having a program code for perform ing one or more of the above methods, when the computer program is executed on a computer or processor. Steps, operations or processes of various above-described methods may be per formed by programmed computers or processors. Examples may also cover program storage devices such as non-transitory computer readable media or digital data storage media, which are machine, processor or computer readable and encode machine-executable, processor-ex ecutable or computer-executable programs of instructions. The instructions perform or cause performing some or all of the acts of the above-described methods. The program storage de vices may comprise or be, for instance, digital memories, magnetic storage media such as magnetic disks and magnetic tapes, hard drives, or optically readable digital data storage me dia. Further examples may also cover computers, processors or control units programmed to perform the acts of the above-described methods or (field) programmable logic arrays ((F)PLAs) or (field) programmable gate arrays ((F)PGAs), programmed to perform the acts of the above-described methods.

The description and drawings merely illustrate the principles of the disclosure. Furthermore, all examples recited herein are principally intended expressly to be only for pedagogical pur poses to aid the reader in understanding the principles of the disclosure and the concepts con tributed by the inventor(s) to furthering the art. All statements herein reciting principles, as pects, and examples of the disclosure, as well as specific examples thereof, are intended to encompass equivalents thereof.

A functional block denoted as“means for ...” performing a certain function may refer to a circuit that is configured to perform a certain function. Hence, a“means for s.th.” may be implemented as a“means configured to or suited for s.th.”, such as a device or a circuit con figured to or suited for the respective task.

Functions of various elements shown in the figures, including any functional blocks labeled as“means”,“means for providing a sensor signal”,“means for generating a transmit signal.”, etc., may be implemented in the form of dedicated hardware, such as“a signal provider”,“a signal processing unit”,“a processor”,“a controller”, etc. as well as hardware capable of ex ecuting software in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which or all of which may be shared. How ever, the term“processor” or“controller” is by far not limited to hardware exclusively capable of executing software, but may include digital signal processor (DSP) hardware, network pro cessor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read only memory (ROM) for storing software, random access memory (RAM), and non volatile storage. Other hardware, conventional and/or custom, may also be included.

A block diagram may, for instance, illustrate a high-level circuit diagram implementing the principles of the disclosure. Similarly, a flow chart, a flow diagram, a state transition diagram, a pseudo code, and the like may represent various processes, operations or steps, which may, for instance, be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown. Meth ods disclosed in the specification or in the claims may be implemented by a device having means for performing each of the respective acts of these methods.

It is to be understood that the disclosure of multiple acts, processes, operations, steps or func tions disclosed in the specification or claims may not be construed as to be within the specific order, unless explicitly or implicitly stated otherwise, for instance for technical reasons. Therefore, the disclosure of multiple acts or functions will not limit these to a particular order unless such acts or functions are not interchangeable for technical reasons. Furthermore, in some examples a single act, function, process, operation or step may include or may be broken into multiple sub-acts, -functions, -processes, -operations or -steps, respectively. Such sub acts may be included and part of the disclosure of this single act unless explicitly excluded. Furthermore, the following claims are hereby incorporated into the detailed description, where each claim may stand on its own as a separate example. While each claim may stand on its own as a separate example, it is to be noted that - although a dependent claim may refer in the claims to a specific combination with one or more other claims - other examples may also include a combination of the dependent claim with the subject matter of each other de- pendent or independent claim. Such combinations are explicitly proposed herein unless it is stated that a specific combination is not intended. Furthermore, it is intended to include also features of a claim to any other independent claim even if this claim is not directly made dependent to the independent claim.