BACKGROUND OF THE INVENTION The performance characteristics of an integrated circuit (IC) depend heavily upon the materials used to form the IC. Traditionally, IC manufacturers use aluminum (Al) for the interconnect wiring between devices on the ICs. The current trend in integrated circuit design is toward smaller, more densely populated geometries, which push the limits of Al-based IC chips.

This trend creates a need for materials that increase interconnect performance.

Copper (Cu) interconnects exhibit superior characteristics compared to Al interconnects. For example, Cu provides reduced interconnect propagation delays, reduced cross talk, and higher interconnect current densities. The lower resistivity and superior electromigration of Cu also allow for a reduction in

metal stack height that results in shorter RC delays.

Copper, in combination with low-k dielectrics, further allows for a reduction in the number of metallization layers resulting in reduced chip manufacturing costs.

Therefore, Cu wiring in IC designs is an attractive alternative to conventional Al-based metallization.

The manufacture of Cu-based ICs, then, is desirable in order to take advantage of the superior characteristics of Cu interconnects. The method for building an IC involves deposition or growth of various layers in conjunction with etching patterns that include the designs of gates and interconnects upon a wafer. The manufacturer uses one of various deposition techniques to deposit a material layer, in this case Cu, upon the wafer and within the etched profile comprising trenches and holes. Lastly, the manufacturer removes the excess Cu, leaving the inlaid Cu interconnect metal lines and via plugs in place. Because of the peculiarities of Cu, such as dry etch difficulties, the preferred method of removing the excess Cu is chemical-mechanical polishing (CMP).

The deposition technique is in important part of this process. The result of the deposition should be a uniform material layer over the top of the wafer. This result is mandated in part by CMP, because CMP is more effective with a higher grade of uniformity.

One conventional deposition technique for Cu is metal-organic chemical-vapor deposition (MOCVD). MOCVD provides excellent seed layer conformality and gap fill characteristics and is compatible with single or dual damascene processing. Additionally, the low thermal

budget of MOCVD (e. g., less than about 250° Celsius for Cu and less than about 400° Celsius for barrier deposition) ensures compatibility with low-k dielectric materials, which are susceptible to degradation at high temperatures. Such advantages make MOCVD Cu the deposition method of choice for formation of inlaid lines and plugs in fine structures with large aspect ratios, such as in 0.18 Hm and smaller features, and features with an aspect ratio of five or more.

MOCVD presents difficulties, however, with respect to larger geometries. MOCVD can fail to adequately distribute large grains, leading to inferior electromigration characteristics with larger scale features. MOCVD is also a relatively slow deposition process, with an deposition rate of approximately 2000 A/min.

Electroplating provides a process for Cu deposition that addresses some disadvantages of MOCVD.

Electroplated Cu provides smooth and preferentially textured films with a uniform distribution of large grains. These features result in superior electromigration characteristics. Additionally, deposition rates for electroplated Cu are typically greater than 4,000 Å/min. These higher deposition rates lead to an ability to manufacture more ICs in a given period, which leads to a higher equipment throughput and productivity.

Electroplating deposits a material by passing current through a wafer to an anode made of the material.

The anode receives the current and releases material to the wafer through an electrolyte. Most wafers, however,

comprise an insulating material such as Si020r a low-k dielectric material, meaning that current will not pass through the wafer. This leads to the requirement of a seed layer. The seed layer comprises a conductive material that will pass the current and will receive the material from the anode.

Therefore, a conventional Cu electroplating process first places an electrically conductive seed layer on the wafer using MOCVD or physical-vapor deposition (PVD).

Probes electrically couple to the wafer such that the wafer acts as a cathode during the electroplating process. The anode formed from the material maintains a positive charge relative to the wafer, and an electrolyte solution between the anode and the cathode completes the electrical circuit. As power applies to the cathode, electrons move from the cathode to the anode.

Conversely, as the anode accepts electrons, the material, in this case Cu, moves from the anode and is deposited upon the cathode (or the wafer surface).

The conventional electroplating process presents several difficulties. First, it is difficult to control the uniformity of the deposited material layer. The seed layer and the electroplated layer will typically exhibit different uniformity, because of the different processes used to deposit them. Therefore, it is advantageous to deposit a thin seed layer, through PVD or MOCVD, in order to deposit more material through electroplating. A thin seed layer, however, leads to difficulties because it may fail to carry current to the center of the wafer due to ohmic losses. This, in turn leads to a non-uniform

deposition during electroplating, favoring the outside of the wafer over the center of the wafer.

Another problem occurs with conventional processes as the probes become hot. The probes heat the seed layer below the probes, which can prematurely end the electroplating process. Once again, a thin seed layer makes this problem more likely to occur, as a thin seed layer is more prone to melt and/or to ball up (resulting in no copper seed layer under the probes).

Yet another problem is that the conventional electroplating process creates non-uniformity of the deposited material layer around the area of the probes.

When the process positions the probes inside the electrolyte solution, the resulting deposited material layer is typically thicker around the area of the probes.

This leads to difficulties because CMP may not be able to entirely remove the excess material without causing significant dishing. Conversely, when the process positions the probes outside of the electrolyte solution, the deposited material layer is thinner around the area of the probes. This is problematic because it can lead to a premature termination of the electroplating process.

Another problem is that the need for a slower process to deposit the seed layer reduces the potential throughput of the electroplating process. A thicker seed layer leads to a slower overall process, because a thicker seed layer takes longer to deposit using MOCVD, PVD, or some other deposition process.

SUMMARY OF THE INVENTION

Therefore, a need has arisen for an apparatus and method for electroplating a uniform material layer upon a wafer.

There is also a need for a device and method that electroplates a uniform material layer upon a wafer with a thin seed layer.

There is further a need for a device and method that improves the uniformity of a material layer deposited through the electroplating process.

In accordance with the present invention, a method and apparatus for electroplating a material onto a wafer are disclosed that reduce a minimum required seed layer thickness by varying a current during electroplating.

According to one aspect of the present invention, an apparatus comprises a wafer support for maintaining a wafer within an electrolyte solution during electroplating. A probe, proximate the wafer support, receives an electrical current and is operable to electrically couple to the wafer. An anode is proximate the wafer support. An anode source is electrically coupled to the anode. The anode source provides an electrical potential o the anode such that the anode is positively charged relative to the wafer. A current controller varies an electrical current flowing through the wafer as the material is deposited upon the wafer.

According to another aspect of the present invention, a method for depositing a material onto a wafer comprises electroplating a material onto a wafer.

The wafer has an inner portion and an outer portion. The electroplated material forms a material layer on the wafer. The method further comprises varying, during the

electroplating step, an inner current flowing through the inner portion of the wafer and an outer current flowing through the outer portion of the wafer as a thickness of the material layer changes.

It is a technical advantage of the present invention that it varies current flow during electroplating. This allows for the use of a thinner seed layer and increases the uniformity of the material deposited through electroplating.

It is an additional technical advantage of the present invention that it changes the positions of the probes on the wafer. This reduces local thinning and overheating of the seed layer caused by the positioning of the probes. This, in turn, allows for a greater stability during the electroplating process and reduces the possibility of a premature termination of the electroplating process. Changing the positions of the probes further reduces the localized non-uniformity caused by static probe positions during electroplating.

The ability to form a uniform Cu layer on a wafer increases the viability of electroplating as an IC manufacturing process. The inherent advantages of Cu can then be combined with the greater throughput advantages of electroplating to form a superior semiconductor chip compared to conventional devices, and to manufacture this superior IC at a lower cost. The present invention enables the use of a thinner seed layer, meaning that the superior electroplating process deposits a larger portion of the material layer.

Other technical advantages should be apparent to one of ordinary skill in the art in view of the specification, claims, and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS A more complete understanding of the present invention and advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features, and wherein: FIGURE 1 is a side view of one embodiment of an electroplating cell having ballast resistors and a segmented anode; FIGURE 2 is a top view of one embodiment of a segmented anode; FIGURE 3 is a top view of one embodiment of an electroplating cell having multiple probes; FIGURE 4 is a profile view of one embodiment of an enhanced seed layer according to the present invention; FIGURE 5 is a diagram of one embodiment of a two zone showerhead for MOCVD deposition of a seed layer according to the present invention; FIGURE 6 is a profile view of one embodiment of a wafer with an enhanced profile formed through PVD; and FIGURE 7A is a profile view of a wafer having a high-aspect-ratio feature and seed layer deposited by a conventional process; and FIGURE 7B is a profile view of a wafer having a high-aspect-ratio feature and non-conformal seed layer deposited in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION The present invention involves the deposition of a material layer on a wafer for the manufacture of integrated circuits. One objective is to obtain a "uniform"layer, meaning a homogenous layer across a substrate. Another objective is a"conformal"layer meaning the layer tracks the contours and surface topography of the wafer.

The present invention modifies various parameters involved in conventional electroplating processes to increase the effectiveness of electroplating by increasing the uniformity of the material layer deposited during electroplating.

Electroplating Current As mentioned above, one problem with conventional electroplating processes is the need for a separate deposition process to place a thin seed layer upon the wafer. Since there are two processes involved, the uniformity of the eventual deposited material suffers.

Therefore, it is advantageous to deposit as thin a seed layer as possible. A seed layer that is too thin (e. g., less than 200A), however, is unable to carry enough current to complete deposition by electroplating, because it fails to carry current from the point of probe contact without significant ohmic drop. For example, if the probe contacts the wafer at an outer circumference, a seed layer that is too thin will fail to carry sufficient current to the center of the wafer due to excessive ohmic drop.

The present invention addresses this problem by controlling the current of the electroplating circuit.

In one embodiment, the invention places a greater current in the center of the wafer and lesser current at the edges of the wafer. Additionally, as material deposits upon the wafer through electroplating, and is thus able to carry more current, the present invention increases the current. This feature increases the speed of the electroplating process.

One embodiment of the present invention controls the current flowing during electroplating by controlling the electroplating resistance. Electroplating resistance is the resistance of the electroplating circuit, wherein the electroplating circuit comprises: a cathode comprising the wafer, an anode comprising the material to be deposited, and an electrolyte solution between the anode and the cathode. The present invention increases the electroplating resistance relative to the sheet resistance of the seed layer. This increase in resistance leads to a decrease in the current flow. This lower current flow enables a thinner seed layer to viably propagate electroplating current flow, and yields greater thickness uniformity in the material layer deposited during electroplating.

A seed layer preferably exhibits at least two characteristics. First, the seed layer should be conformal and continuous over the wafer and within the surface feature being filled. Second, the conductance of the seed layer should minimize the potential drop across the wafer during electroplating. The latter requirement dictates the minimum allowable thickness of the seed

layer. Analytically, the current and voltage distribution across the wafer during electroplating is expressed as: dJ J V -=--+ dr r p dV = JR du where J is the linear current density (A/m) as a function of radius, V is the surface potential, Rs is the sheet resistance of the seed layer, and Pe is the specific resistivity of the electroplating solution (i. e. pg= nr02R3). The typical resistance of an electroplating solution (Re) is 0.5 Q. The wafer radius is denoted by ro. These equations can be combined into a differential equation for J: <BR> <BR> <BR> <BR> <BR> <BR> <BR> d#J dJ<BR> <BR> r# -(1+ßr#)J=0r dr# dr R zrneRv2 The following boundary conditions apply:

[(##(r#)+#####)]##=V#V(r#)= n For a uniform sheet resistance, these equations solve analytically using a series solution, and the dominant leading edge terms give: The initial electroplating non-uniformity (o) can be described in terms of the maximum and minimum surface potential across the wafer: Thus, for a typical electroplating resistance (Re = 0.5 Q), the maximum sheet resistance should be less than approximately 0.6 Q/square for an electroplating non- uniformity of less than 5% on an 8"wafer. This translates to a copper seed layer thickness of o approximately 500 A. If the seed layer is thinner than this approximate minimum, electroplating may not occur uniformly in the center of the wafer. In practice, the

minimum seed layer thickness may have to be even greater to account for non-uniformities of the seed layer, and the partial etch back that occurs at the initiation of the electroplating process.

The expression for non-uniformity shows that to the first order, non-uniformity is independent of the applied voltage. Thus, decreasing the electroplating rate by decreasing the applied voltage does not affect the electroplating non-uniformity to the first order.

The expression further shows that the electroplating uniformity improves if the electroplating resistance (Re) of the seed layer is increased relative to the sheet resistance (Rs) of the seed layer. This is due to decreased current flow.

FIGURE 1 is a side view of one embodiment of an electroplating cell having a segmented anode and ballast resistors. An electroplating cell, indicated generally at 10, includes a frame 14. An anode support 18 is coupled to frame 14, and a segmented anode 36 is coupled to anode support plate 18. Segmented anode 36 is electrically coupled to anode source 23. In the embodiment of FIGURE 1, anode source 23 is simply an electrical ground, and segmented anode 36 comprises a copper segmented anode. Segmented anode 36 comprises a plurality of anode sections each coupled to anode source 23. Cell 10 further includes a current control device to vary the electrical current flowing during electroplating. In the embodiment of FIGURE 1, the current control device comprises ballast resistors 38 coupled between segmented anode 36 and anode source 23.

Ballast resistors 38 comprise passive and/or active electrical devices.

A wafer support 22 is coupled to frame 14 proximate segmented anode 36. A wafer 40 is coupled to wafer support within cell 10. A plurality of probes 24 are coupled to wafer support plate 22 and electrically coupled to wafer 40. Probes 24 receive an electrical charge from a cathode source 25.

Frame 14 provides an entrance passage 28 and an exit passage 32 for allowing fresh electrolyte to enter, and spent electrolyte to exit cell 10, respectively. An electrical isolator 29 provides high resistance between cell 10 and an electrolyte reservoir. A distributor plate 30, comprising a plurality of passages 31, is coupled to frame 14 between anode support 18 and wafer support 22.

In operation, cell 10 deposits copper from segmented anode 36 to wafer 40 during an electroplating process.

Probes 24 electrically connect cathode source 25 to wafer 40 such that wafer 40 acts as the cathode during electroplating. Anode source 23 electrically couples to segmented anode 36 and maintains a potential difference such that segmented anode is positively charged with respect to wafer 40. For example, anode source 23 could be an electrical ground. Fresh electrolyte completes the circuit, and enters cell 10 through entrance passage 28.

Spent electrolyte exits cell 10 through exit passage 32.

Cathode source 40 applies an electrical potential to wafer 40 and current flows between wafer 40 and segmented anode 36. Segmented anode 36 receives the current flow, and in turn releases copper. The seed layer on wafer 40

in turn attracts the released copper, resulting in copper deposition.

Ballast resistors 38 increase the electroplating resistance relative to the sheet layer resistance of the seed layer on wafer 40. Each section of segmented anode 36 acts as a separate circuit, each circuit comprised of cathode source 25, wafer 40 and accompanying seed layer, a section of segmented anode 36, a ballast resistor 38, and anode source 23. Each of these circuits have the same voltage. The invention varies the resistance of ballast resistors 38 and thus varies the flow of current through each of these separate circuits.

Ballast resistors 38 vary the resistance in the circuits in two ways. First, ballast resistors 38 in the center sections of segmented anode 38 have a lower resistance than ballast resistors 38 in the outer sections of segmented anode 38. Therefor, more current flows through an inner portion of wafer 40, allowing for electroplating to occur even at the center of wafer 40 with a thin seed layer. Ballast resistors 38 can operate thus, for example, during an initial stage of electroplating when the seed layer is thin. Secondly, ballast resistors 38 decrease in resistance during electroplating. As electroplated Cu deposits upon wafer 40, wafer 40 is operable to handle more current and increase the amount of deposited Cu.

Distributor plate 30 includes passages 31 optimized for a uniform flow of electrolyte and potential distribution across wafer 40.

In one embodiment, probes 24 comprise a plurality of sets of probes. The sets of probes retract and extend

such that one of the sets of probes contacts wafer 40 at a given time. The sets of probes cyclically extend and retract, such that the set of probes providing electrical current to wafer 40 alternates. Such an embodiment is advantageous in that it reduces the local heating under the respective probes 24. Additionally, such an embodiment can further reduce the non-uniformity of the deposited material layer, as described in more detail with respect to FIGURE 3, below.

Another embodiment includes the use of electrically insulating surfaces. Surface of frame 14, a surface of wafer support plate 22, and a surface of distributor plate 30 comprises an electrically insulating surface.

This allows the use of separate power supplies for anode source 23 and cathode source 25. Sufficient resistance of electrical isolator 29 enables such an embodiment.

The embodiment of FIGURE 1 describes an apparatus for electroplating using ballast resistors. The ballast resistors vary the current in the system by varying the electroplating resistance relative to the sheet resistance of the seed layer on the wafer. An alternate method alters the concentration of the electrolyte during electroplating. This method is difficult because it affects the electroplating chemistry, and thus the quality of the material deposited. Additionally, fine control of the electrolyte concentration is difficult.

This factor, among others, makes altering the concentration more difficult than the use of a ballast resistor.

FIGURE 2 is a top view of one embodiment of a segmented anode 36. Segmented anode 36 comprises a

plurality of anode sections 41. As shown in FIGURE 1, ballast resistors 38 couple between anode sections 41 and anode source 23. Anode sections 41 toward the center of segmented anode 36 are proximate to the center of the wafer, and anode sections 41 toward the outer portions of segmented anode 36 are proximate an outer region of the wafer. The ballast resistors coupled to the inner sections have a lower resistance than the ballast resistors coupled to the outer sections. This increases the current flow to the center of the wafer, allowing electroplating on a wafer with a thinner seed layer.

This accomplishes a reduction of the minimum seed layer thickness.

Probe Position The present invention modifies the probe position, which is another parameter of the electroplating process.

The modification further increases the uniformity of the material layer deposited during electroplating.

A disadvantage of conventional systems used for electroplating arises from the position of probes on the wafer. The first problem with probe position is that the probes become hot. This, in turn, locally heats the seed layer, which can negatively affect the electroplating process.

Another disadvantage of conventional probe placement involves localized non-uniformity that results from the probes. Two conventional probe configurations include: (1) a series of four to six probes arranged around the periphery of the wafer, but within the electroplating solution and (2) a series of four to six probes arranged

around the periphery of the wafer, but outside the electroplating solution. Both of these configurations lead to problems with localized non-uniformity of the material deposited during the electroplating process.

When a system places the probes within the electroplating solution, electroplated Cu deposits thicker in the vicinity of the probes. This non- uniformity leads to problems during CMP, because typical CMP over-polish is limited to 30% to minimize dishing.

Therefore, a localized non-uniformity of 10-15% (lo) will result in incomplete metal removal in the area of the non-uniformity. Typical planarization lengths for CMP are approximately 100 ßm. CMP cannot accommodate non- uniformity over much longer length scales such as those around wafer probes.

When a system places the probes outside the electroplating solution, the deposited material layer is thinner in the area of the probes. This can lead to a "vanishing copper effect"if the seed layer is too thin.

In the vanishing copper effect, the Cu in the vicinity of the probe gradually disappears and eventually vanishes, prematurely terminating the electroplating process. The mechanism for this failure is that thermally accelerated electromigration induced flow causes the Cu to recede in a circular pattern away from the probe. Even if current densities are below the EM limit for Cu at room temperature, the Cu film in the vicinity of the probes gets extremely hot, leading to premature failure. When the Cu layer is no longer continuous in the vicinity of the probe, the electroplating current gradually decreases, and the Cu layer recedes. Eventually, the

system reaches a quasi steady state when the thermally accelerated electromigration lifetime becomes much longer than typical electroplating times. Additionally, for a typical electroplating current, the electroplating rate is very low, prematurely terminating the electroplating process.

A simulation of the aforementioned effects follows.

The current density at a probe (Js), in MA/cm2 can be described as: where current in the probe I = 2 A; probe diameter d = 1 mm; a seed layer thickness t = 500 A.

This current density is unlikely to result in failure of the Cu at room temperature. However, localized heating causes the surface temperature to rise much higher than room temperature. The surface temperature is estimated by assuming that the entire heat dissipation in the vicinity of the probes is lost via conduction through the probes.

The approximate resistance of this region (R), in ohms, is computed as: with a vanishing Cu diameter D = 6 mm, and a sheet resistance of the seed layer Rs = 0.5 ohms/square.

Next, the power dissipation (P), in Watts, in the region is: P = I2R = 0.909 W The thermal resistance of the probe is: where the length of probe lp = 5 x 10-3 m and the thermal conductivity of probe is k = 10 W/mK.

The temperature rise of the surface is then: AT= P-Rt = 578.978 K The localized surface temperature is high which results in EM failure of the seed Cu in the vicinity of the probe, leading to the vanishing Cu effect. We can now estimate the electromigration lifetime of the Cu for this current density and surface temperature.

The surface temperature is: Tus = 273 + AT = 851.978 (K) Ten years is a typical electromigration lifetime for Cu at a current density of 1 MA/cm2 and an interconnect operating temperature of 150° C. Using this typical lifetime, the lifetime at higher a current density and operating temperature is estimated from Black's equation, assuming an activation energy of 1 eV. First, the operating temperature of the interconnect is: Tx= 273+150 = 423 (k) the seed layer lifetime (min) is:

where the interconnect lifetime lic= 10 years; the baseline current density Jo = 1 MA/cm2; the activation energy for electromigration Ea = 1 eV; the electron charge ec = 1.602-10-19 C; Boltzman's Constant kB = 1.381 x 10-23 J/K, and the current density exponent for Black's equation n = 2.

This expression indicates that the electromigration lifetime is comparable to the duration of the electroplating, resulting in the vanishing Cu effect.

The present invention reduces localized heating and localized non-uniformity that result from the placement of the probes. The present invention accomplishes this advantage by cycling the probes'position on the wafer.

Specifically, the present invention includes a method for depositing a material onto a wafer comprising electroplating the material onto the wafer. The method then changes the position of points of contacts of the probes with respect to the wafer. One embodiment rotates the wafer with respect to a probe during electroplating.

A further embodiment uses a plurality of sets of probes

during electroplating step, wherein each of the sets of probes is operable to electrically couple to the wafer.

During electroplating, one set of the plurality of probes is retracted. Subsequently, the one set is extended to electrically couple to the wafer, and another set is retracted. In such a way, the method cycles the position of the probes with respect to the wafer during electroplating. Such a method leads to advantages such as reduced local heating of the seed layer, and improving the non-uniformity that results from the position of the probes with respect to the seed layer.

FIGURE 3 is a top view of one embodiment of an electroplating cell having multiple probes. Wafer 63 includes a Cu seed layer covering a top surface of wafer 63. Electroplating cell 60 includes a first set of probes 64 and a second set of probes 68. The sets of probes 64 and 68 are coupled to and provide an electrical charge to wafer 63 during an electroplating process.

Wafer 63 and its accompanying Cu seed layer form a cathode during the electroplating process.

In the embodiment of FIGURE 3, sets of probes 64 and 68 retract and extend such that only one of the sets of probes 64 or 68 is electrically coupled to wafer 63 at a given time during electroplating. For example, during a portion of the electroplating process, set of probes 64 will retract, while set of probes 68 remain electrically coupled to wafer 63. Set of probes 68 then retract and set of probes 64 extend such that set of probes 64 electrically couples to wafer 63. The invention of FIGURE 2 thus cycles the position of probes on wafer 63 during electroplating, which reduces local overheating of

the seed layer. In addition, such the embodiment reduces the non-uniformity of the electroplated Cu resulting from the position of the probes.

In one alternate embodiment to FIGURE 3, set of probes 64 is removed. Gear 73 is engages wafer support (22 of FIGURE 1). In operation, during electroplating, gear 73 rotates wafer support. Wafer 60 thus rotates such that set of probes 68 contacts wafer 60 at different positions during the electroplating.

A further alternative embodiment to the embodiment represented in FIGURE 3 includes a reservoir containing an electrically insulating fluid. The reservoir and accompanying fluid cool sets of probes 64 and 68 in order to maintain a surface temperature on wafer 60 below 150° Celsius.

Seed Layer Profile The present invention further modifies the surface uniformity profile of the seed layer placed upon the wafer. As discussed above, non-uniformity occurs around the areas of the probes. Therefore, the present invention modifies the seed layer profile in those areas, resulting in a more uniform material layer formed by the electroplating process.

Further shown in the embodiment of FIGURE 3 is an embodiment using an enhanced seed layer profile. A band 72 of the seed layer is positioned on wafer 60 below sets of probes 64 and 68. Seed layer band 72 is thicker than the seed layer on other portions of wafer 60. One embodiment of such a profile is a step change in thickness along a perimeter bounded by the probes.

FIGURE 4 is a profile view of one embodiment of an enhanced seed layer according to the present invention.

Wafer 78 includes seed layer 80. Probes 82 electrically couple to seed layer 80. Seed layer 80 has a profile that is thicker in the area of probes 82, as denoted by band 72 (see also FIGURE 3).

In operation, probes 82 provide electrical power such that wafer 60 acts as a cathode during the electroplating process. The process results in the deposition of material layer 84, which due to the profile of seed layer 82, is uniform.

The thicker seed layer at the edge of wafer 78 allows probes 82 to make mechanical contact with the surface of wafer 78 without breaking or damaging seed layer 80. Additionally, seed layer bands 72 can reduce the EM stress at an edge of wafer 78.

In one embodiment of the present invention, several of the above-referenced embodiments combine. For example, the embodiment uses a wafer with an enhanced seed layer profile in an electroplating cell that includes ballast resistors. The embodiment further retracts and extends the probes to cycle the area of wafer 78 that is in contact with probes 82. Such an embodiment enables electroplating on wafers with seed layers of 100 to 200 angstroms thickness without the problems of poor or non-repeatable contact.

Deposition of the Enhanced Seed Layer Profile Manufacturers can use PVD or MOCVD to form the seed layer prior to electroplating. However, MOCVD is a preferable method for deposition of the seed layer. As

stated above, electroplating requires a continuous seed layer the surface of the wafer and within the features of the wafer. PVD based approaches (either collimated PVD or ionized PVD) typically include a step coverage of 20 to 30 percent for an aspect ratio of around five. PVD has a limited process latitude of PVD because step coverage is less than 10% on any surfaces upon which the features are re-entrant (barrel shaped).

As geometries scale down and metal line/via overlaps reduce, it can be important to maintain a vertical edge profile for single or dual damascene structures.

Maintaining a perfectly vertical sidewall is difficult as the trench/via size decreases. It is, therefore, not uncommon for wafers to include features on one portion of the wafer that are vertical or sloped outward, while features on another part of the wafer are re-entrant. In such a scenario, PVD approaches tend to fail entirely because the seed layer may no longer be continuous in the re-entrant features. A discontinuous seed layer along the sidewall during electroplating results in Cu deposition at the bottom and top of the trench or via with no material in between. This in turn leads to catastrophic failure of the lead or plug.

In contrast, conformality of the MOCVD Cu ensures a uniform seed layer thickness in re-entrant features.

Thus, the use of MOCVD may avoid a catastrophic failure of the lead plug. MOCVD extends the process capability of electroplating by making it possible to fill much more aggressive features than would be possible with a PVD Cu seed layer.

One embodiment of the present invention creates the enhanced seed layer profile using MOCVD. FIGURE 5 is a diagram of one embodiment of a two zone showerhead for MOCVD deposition of a seed layer according to the present invention. A showerhead 104 includes two baffle attachments 100 and 101. Showerhead 104 includes an inner zone 106 and an outer zone 108. A wafer 110 is positioned to receive reactive gases from showerhead 100 for deposition of the desired seed layer.

In operation, showerhead 104 deposits the desired seed layer by flowing reactive gases through inner zone 106 and outer zone 108. Baffle 100 provides gasses to inner zone 106, and baffle 101 provides gasses to outer zone 108. After a desired thickness has been deposited, wafer 110 is positioned closer showerhead 100. Baffle 100 then provides inert gas to inner zone 106, and baffle 101 provides reactive gas to outer zone 108. This arrangement allows the deposition of a thicker seed layer at the periphery of wafer 110.

Another embodiment uses PVD for deposition of an enhanced seed layer. FIGURE 6 is a profile view of one embodiment of a wafer with an enhanced profile formed through PVD. Wafer 120 is the object upon which the seed layer is deposited. An initial seed layer 122 forms, through PVD, onto wafer 120. A mask 124 masks a central portion of wafer 120. An additional seed material band 126 is deposited over the area of the wafer that is not masked, which corresponds to the eventual position of the probes.

A further embodiment uses electroplating to build an enhanced seed layer. Initially, a uniform seed layer

covers the wafer. Then, electroplating deposits the enhanced seed layer profile. Referencing FIGURE 1, probes 24 provide a negative electric charge to wafer 40.

As discussed above, if probes 24 are within electrolyte solution, the area around probes 24 will become thicker.

Thus, the enhanced profile is built. The wafer with the enhanced profile can then be used in an electroplating process with the probes outside of an electrolyte solution--which takes advantage of the enhanced profile.

Alternatively one set of probes may be used to preferentially build up the seed layer at the edge, and another set for the bulk fill. Many options are available depending on electroplating tool design.

Electroplating High-aspect-ratio Features As discussed above, electroplating can require a fairly thick seed layer for adequate electroplating uniformity. However, for conformal deposition, increasing the field thickness also increases the thickness of the deposited layer inside a feature of the wafer. FIGURE 7A is a profile view of a wafer having a high-aspect-ratio feature and a seed layer deposited by a conventional deposition process. A wafer 130 includes a trench 132. Trench 132 includes a width 134 of 0.25 ßm and a depth 136 of 1 ßm. A seed layer 140 is deposited upon wafer 130.

A conventional deposition process may constrain seed layer 140 to a thickness of 1000 A for adequate uniformity. A conventional 90% conformality leaves only o approximately 700 A wide opening in the trench 132 for subsequent electroplating. This translates to an

effective aspect ratio of approximately 14, which is very difficult to fill with an electroplating process.

Additionally, as shown in FIGURE 7A, conventional deposition processes with a conventional conformality may create a seed layer having an overhang, thereby decreasing further the effective width of trench 132 available for electroplating.

Therefor, for certain feature sizes, it is desirable to have a conformality of less than 100% to ease subsequent electroplating. FIGURE 7B is a profile view of a wafer having a high-aspect-ratio feature and non- conformal seed layer deposited in accordance with the present invention. Similar to FIGURE 7A, wafer 130 includes trench 132, having a width 134 and depth 136.

However, seed layer 144 of FIGURE 7B exhibits a non- conformal profile. In the embodiment of FIGURE 7B, the profile is thinner along the sides of trench 132. This decreases the effective aspect ratio of trench 132, and allows for more effective electroplating.

Lowering the conformality of seed layer 140 can be achieved in several ways. One such method comprises first depositing a Cu seed layer using PVD.

Subsequently, a thin Cu seed layer is deposited using MOCVD, such that the effective conformality is 30-70%.

Another method of reducing conformality comprises first depositing a thin Cu seed layer using MOCVD.

Subsequently, a subsequent Cu seed layer is deposited using PVD such that the effective conformality is 30- 70%.

An additional method of reducing conformality comprises first depositing a thin Cu seed layer using

MOCVD. The first thin layer can comprise a high conformality to achieve good nucleation, adhesion and low surface roughness. This first layer is followed by a lower conformality MOCVD Cu seed layer. The lower conformality seed layer can be obtained either by decreasing the precursor concentration (i. e. decreasing precursor flow, increasing carrier flow or both) or by increasing the deposition temperature. Of these two options, the former option is preferred since it does not degrade surface roughness and does not require cycling of chuck temperature.

Although the present invention has been described in detail, it should be understood that various changes, substitutions and alterations can be made thereto without departing from the spirit and scope of the invention as defined by the appended claims.