APPARATUS FOR AND METHOD OF PROVIDING HIGH PRECISION DELAYS IN A LITHOGRAPHY SYSTEM

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority of US application 62/740,191 which was filed on October 2, 2018 and US application 62/736,738 which was filed on September 26, 2018, the contents of each of which are hereby incorporated by reference, in their entireties.

FIELD

[0002] The present disclosed subject matter relates to control of laser-generated light sources such as are used for integrated circuit photolithographic manufacturing processes.

BACKGROUND

[0003] One system for generating laser radiation at frequencies useful for semiconductor photolithography (deep-ultraviolet (DUV) wavelengths) involves use of a Master Oscillator Power Amplifier (MOPA) dual-gas-discharge-chamber configuration. Managing the relative timing of the pulse (firing) in the master oscillator (MO) portion of the MOPA with respect to the pulse (firing) in the power amplifier (PA) portion of the MOPA is required for laser dose stability. Similar master oscillator seed providing laser systems with other amplifier configurations such as a power oscillator (“PO”) can also be used. For purposes of brevity, however, except where expressly indicated otherwise, the term MOPA or the terms MO and PA separately shall be interpreted to mean any such multi-chamber laser system, e.g., a two chamber laser system, e.g., including an oscillator seed pulse generating portion optimizing a beam parameter quality followed by amplification of the seed pulse by an amplifier portion receiving the seed pulse of whatever variety, examples of which being noted above, that serves the amplification function and is tuned for this amplification process, leaving, more or less intact the particular beam quality parameter(s) optimized in the master oscillator section.

[0004] Extreme ultraviolet (“EUV”) light, e.g., electromagnetic radiation having wavelengths of around 50 nm or less (also sometimes referred to as soft x-rays), and including light at a wavelength of about 13.5 nm, is used in photolithography processes to produce extremely small features on substrates such as silicon wafers. Here and elsewhere herein the term“light” is used even though it is understood that the radiation described using that term may not in the visible part of the spectrum. Methods for generating EUV light include converting a target material from a liquid state into a plasma state. The target material preferably includes at least one element, e.g., xenon, lithium or tin, with one or more emission lines in the EUV range. In one such method, often termed laser produced plasma (“LPP”), the required plasma can be produced by using a laser beam to irradiate a target material having the required line-emitting element. Managing the relative timing of pulses in an EUV system is also required for dose stability.

[0005] It is desirable provide an alternative to existing apparatus or methods for managing relative pulse timing in such systems.

SUMMARY

[0006] The following presents a simplified summary of one or more embodiments in order to provide a basic understanding of the present invention. This summary is not an extensive overview of all contemplated embodiments, and is not intended to identify key or critical elements of all embodiments nor delineate the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later.

[0007] Disclosed herein in accordance with one aspect of an embodiment is a laser system comprising a field programmable gate array configured to generate a first digital signal transitioning from a first logic level to a second logic level for a plurality of clock cycles and a second digital signal which is a logical inverse of the first digital signal, a first programmable delay circuit arranged to receive the first digital signal and configured to delay propagation of the first digital signal by a first delay to generate a delayed first digital signal, a second programmable delay circuit arranged to receive the second digital signal and configured to delay propagation of the second digital signal by a second delay greater than the first delay to generate a delayed second digital signal, and a first logic circuit arranged to receive the delayed first digital signal and the delayed second digital signal and configured to generate a pulse when and only when both the first digital signal and the delayed second digital signal are at the second logic level.

[0008] Also disclosed herein in accordance with one aspect of an embodiment is laser system comprising a module configured to supply a first pulse having a first duration and a second pulse having a second duration with a start of the first pulse and a start of the second pulse being separated in time by a delay interval, the module comprising a field programmable gate array configured to generate a first digital signal transitioning from a first logic level to a second logic level at a time ti for a plurality of clock cycles, a second digital signal which is a logical inverse of the first digital signal, a third digital signal transitioning from the first logic level to the second logic level at a time t ₂ later than ti for a plurality of clock cycles, and a fourth digital signal which is a logical inverse of the third digital signal, a first programmable delay circuit arranged to receive the first digital signal and configured to delay propagation of the first digital signal by a first delay to generate a delayed first digital signal, a second programmable delay circuit arranged to receive the second digital signal and configured to delay propagation of the second digital signal by a second delay greater than the first delay to generate a delayed second digital signal, a first logic circuit arranged to receive the delayed first digital signal and the delayed second digital signal and configured to generate the first pulse when and only when both the first digital signal and the delayed second digital signal are at the second logic level, a third programmable delay circuit arranged to receive the third digital signal and configured to delay propagation of the third digital signal by a third delay to generate a delayed third digital signal, a fourth programmable delay circuit arranged to receive the fourth digital signal and configured to delay propagation of the fourth digital signal by a fourth delay greater than the third delay to generate a delayed fourth digital signal, and a second logic circuit arranged to receive the delayed third digital signal and the delayed fourth digital signal and configured to generate the second pulse after cessation of the first pulse when and only when both the delayed third digital signal and the delayed fourth digital signal are at the second logic level.

[0009] The laser system may be a system for generating deep ultraviolet radiation and further comprising a first trigger circuit arranged to receive the first pulse and for causing a first chamber of the laser to fire in response to the first pulse and a second trigger circuit arranged to receive the second pulse and for causing a second chamber of the laser to fire in response to the second pulse.

[0010] The laser system may be a system for generating extreme ultraviolet radiation and further comprising a first trigger circuit arranged to receive the first pulse and for causing a first laser pulse to fire in response to the first pulse and a second trigger circuit arranged to receive the second pulse and for causing a second laser pulse to fire in response to the second pulse.

[0011] The laser system may comprise a first laser chamber arranged to receive a first laser chamber energizing pulse based on the first pulse, and a second laser chamber arranged to receive a second laser chamber energizing pulse based on the second pulse.

[0012] Also disclosed herein in accordance with one aspect of an embodiment is a method of generating trigger pulses for a laser system, the method comprising generating a first digital signal transitioning from a first logic level to a second logic level for a plurality of clock cycles and a second digital signal which is a logical inverse of the first digital signal delaying propagation of the first digital signal by a first delay to generate a delayed first digital signal delaying propagation of the second digital signal by a second delay greater than the first delay to generate a delayed second digital signal and generating a pulse when and only when both the first digital signal and the delayed second digital signal are at the second logic level.

[0013] Also disclosed herein in accordance with one aspect of an embodiment is a method of generating trigger pulses for a laser system, the method comprising generating a first digital signal transitioning from a first logic level to a second logic level at a time ti for a plurality of clock cycles and a second digital signal which is a logical inverse of the first digital signal, delaying propagation of the first digital signal by a first delay to generate a delayed first digital signal, delaying propagation of the second digital signal by a second delay greater than the first delay to generate a delayed second digital signal, and generating a first pulse when and only when both the first digital signal and the delayed second digital signal are at the second logic level, generating a third digital signal transitioning from the first logic level to the second logic level at a time t ₂ later than ti for a plurality of clock cycles, and a fourth digital signal which is a logical inverse of the third digital signal, delaying propagation of the third digital signal by a third delay to generate a delayed third digital signal, delaying propagation of the fourth digital signal by a fourth delay greater than the third delay to generate a delayed fourth digital signal, and generating a second pulse after cessation of the first pulse when and only when both the delayed third digital signal and the delayed fourth digital signal are at the second logic level.

[0014] The method may further comprise the steps of supplying the first pulse as a trigger to a power commutator of a first chamber of a multi-chamber laser and supplying the second pulse as a trigger to a power commutator of a second chamber of a multi-chamber laser.

[0015] The steps of generating the first, second, third, and fourth digital signals may be performed by a field programmable gate array.

[0016] The method may further comprise the steps of supplying the first pulse as a trigger to fire a first pulse at a target material and supplying the second pulse as a trigger to fire a second pulse at the target material. The first pulse may be a prepulse and the second pulse may be a main pulse.

[0017] The step of delaying the first digital signal may be performed by a first programmable delay circuit.

[0018] The step of delaying the second digital signal may be performed by a second programmable delay circuit. [0019] The step of delaying the third digital signal may be performed by a third programmable delay circuit.

[0020] The step of delaying the fourth digital signal may be performed by a fourth programmable delay circuit.

[0021] Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with reference to the accompanying drawings. It is noted that the present invention is not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Additional embodiments will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein.

BRIEF DESCRIPTION OF THE DRAWING

[0022] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the present invention and to enable a person skilled in the relevant art(s) to make and use the present invention.

[0023] FIG. 1 shows a schematic, not to scale, view of an overall broad conception of a photolithography system according to an aspect of the disclosed subject matter.

[0024] FIG. 2 shows a schematic, not to scale, view of an overall broad conception of an illumination system for producing deep ultraviolet radiation according to an aspect of the disclosed subject matter.

[0025] FIG. 3 shows a schematic, not to scale, view of an overall broad conception of an illumination system for producing extreme ultraviolet radiation according to an aspect of the disclosed subject matter.

[0026] FIG. 4 is a functional block diagram of circuitry for generating delayed pulses.

[0027] FIG. 5 is a functional block diagram of circuitry for generating delayed pulses according to one aspect of an embodiment.

[0028] FIG. 6 is a timing diagram showing signal levels and timing for an example of a mode of operation of the circuitry of FIG. 4 according to one aspect of an embodiment.

[0029] The features and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. DETAILED DESCRIPTION

[0030] Various embodiments are now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to promote a thorough understanding of one or more embodiments. It may be evident in some or all instances, however, that any embodiment described below can be practiced without adopting the specific design details described below. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate description of one or more embodiments. The following presents a simplified summary of one or more embodiments in order to provide a basic understanding of the embodiments. This summary is not an extensive overview of all contemplated embodiments, and is not intended to identify key or critical elements of all embodiments nor delineate the scope of any or all embodiments.

[0031] The embodiment(s) described, and references in the specification to “one embodiment”, “an embodiment”, “an example embodiment”, etc., indicate that the embodiment(s) described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is understood that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0032] Embodiments of the present invention may be implemented in hardware, firmware, software, or any combination thereof. Embodiments of the present invention may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device). For example, a machine-readable medium may include read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.), and others. Further, firmware, software, routines, instructions may be described herein as performing certain actions. However, it should be appreciated that such descriptions are merely for convenience and that such actions in fact result from computing devices, processors, controllers, or other devices executing the firmware, software, routines, instructions, etc.

[0033] Before describing such embodiments in more detail, it is instructive to present an example environment in which embodiments of the present invention may be implemented. While to following example is in terms of a DUV system, it will be understood by one of ordinary skill in the art that the subject matter disclosed herein may also be applied to other laser systems such as, for example, systems for generating EUV radiation.

[0034] Referring to FIG. 1, a photolithography system 100 that includes an illumination system 105. As described more fully below, the illumination system 105 includes a light source that produces a pulsed light beam 110 and directs it to a photolithography exposure apparatus or scanner 115 that patterns microelectronic features on a wafer 120. The wafer 120 is placed on a wafer table 125 constructed to hold wafer 120 and connected to a positioner configured to accurately position the wafer 120 in accordance with certain parameters.

[0035] In the example of FIG. 1, the photolithography system 100 uses a light beam 110 having a wavelength in the deep ultraviolet (DUV) range, for example, with wavelengths of 248 nanometers (nm) or 193 nm. The size of the microelectronic features patterned on the wafer 120 depends on the wavelength of the light beam 110, with a lower wavelength resulting in a smaller minimum feature size. When the wavelength of the light beam 110 is 248 nm or 193 nm, the minimum size of the microelectronic features can be, for example, 50 nm or less. The bandwidth of the light beam 110 can be the actual, instantaneous bandwidth of its optical spectrum (or emission spectrum), which contains information on how the optical energy of the light beam 110 is distributed over different wavelengths. The scanner 115 includes an optical arrangement having, for example, one or more condenser lenses, a mask, and an objective arrangement. The mask is movable along one or more directions, such as along an optical axis of the light beam 110 or in a plane that is perpendicular to the optical axis. The objective arrangement includes a projection lens and enables the image transfer to occur from the mask to the photoresist on the wafer 120. The illumination system 105 adjusts the range of angles for the light beam 110 impinging on the mask. The illumination system 105 also homogenizes (makes uniform) the intensity distribution of the light beam 110 across the mask.

[0036] The scanner 115 can include, among other features, a lithography controller 130, air conditioning devices, and power supplies for the various electrical components. The lithography controller 130 controls how layers are printed on the wafer 120. The lithography controller 130 includes a memory that stores information such as process recipes. A process program or recipe determines the length of the exposure on the wafer 120, the mask used, as well as other factors that affect the exposure. During lithography, a plurality of pulses of the light beam 110 illuminates the same area of the wafer 120 to constitute an illumination dose.

[0037] The photolithography system 100 also preferably includes a control system 135. In general, the control system 135 includes one or more of digital electronic circuitry, computer hardware, firmware, and software. The control system 135 also includes memory which can be read-only memory and/or random access memory. Storage devices suitable for tangibly embodying computer program instructions and data include all forms of non-volatile memory, including, by way of example, semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM disks.

[0038] The control system 135 can also include one or more input devices (such as a keyboard, touch screen, microphone, mouse, hand-held input device, etc.) and one or more output devices (such as a speaker or a monitor). The control system 135 also includes one or more programmable processors, and one or more computer program products tangibly embodied in a machine-readable storage device for execution by one or more programmable processors. The one or more programmable processors can each execute a program of instructions to perform desired functions by operating on input data and generating appropriate output. Generally, the processors receive instructions and data from the memory. Any of the foregoing may be supplemented by, or incorporated in, specially designed ASICs (application- specific integrated circuits). The control system 135 can be centralized or be partially or wholly distributed throughout the photolithography system 100.

[0039] Referring to FIG. 2, an exemplary illumination system 105 is a pulsed multi chamber laser source that produces a pulsed laser beam as the light beam 110. FIG. 2 depicts one particular assemblage of components and optical path strictly for purposes of facilitating the description of the broad principles of the invention in general, and it will be apparent to one having ordinary skill in the art that the principles of the invention may be advantageously applied to lasers having other components and configurations.

[0040] FIG. 2 shows illustratively and in block diagram a gas discharge laser system according to an embodiment of certain aspects of the disclosed subject matter. The gas discharge laser system may include, e.g., a solid state or gas discharge seed laser system 140, a power amplification (“PA”) stage, e.g., a power ring amplifier (“PRA”) stage 145, relay optics 150, and laser system output subsystem 160. The seed system 140 may include, e.g., a master oscillator (“MO”) chamber 165, in which, e.g., electrical discharges between electrodes (not shown) may cause lasing gas discharges in a lasing gas to create an inverted population of high energy molecules, e.g., including Ar, Kr, or Xe to produce relatively broad band radiation that may be line narrowed to a relatively very narrow bandwidth and center wavelength selected in a line narrowing module (“LNM”) 170, as is known in the art.

[0041] The seed laser system 140 may also include a master oscillator output coupler (“MO OC”) 175 which may comprise a partially reflective mirror, forming with a reflective grating (not shown) in the LNM 170, an oscillator cavity in which the seed laser 140 oscillates to form the seed laser output pulse, i.e., forming a master oscillator (“MO”). The system may also include a line-center analysis module (“LAM”) 180. The LAM 180 may include an etalon spectrometer for fine wavelength measurement and a coarser resolution grating spectrometer. A MO wavefront engineering box (“WEB”) 185 may serve to redirect the output of the MO seed laser system 140 toward the amplification stage 145, and may include, e.g., beam expansion with, e.g., a multi prism beam expander (not shown) and coherence busting, e.g., in the form of an optical delay path (not shown).

[0042] The amplification stage 145 may include, e.g., a lasing chamber 200, which may also be an oscillator, e.g., formed by seed beam injection and output coupling optics (not shown) that may be incorporated into a PRA WEB 210 and may be redirected back through the gain medium in the chamber 200 by a beam reverser 220. The PRA WEB 210 may incorporate a partially reflective input/output coupler (not shown) and a maximally reflective mirror for the nominal operating wavelength (e.g., at around 193 nm for an ArF system) and one or more prisms.

[0043] A bandwidth analysis module (“BAM”) 230 at the output of the amplification stage 145 may receive the output laser light beam of pulses from the amplification stage and pick off a portion of the light beam for metrology purposes, e.g., to measure the output bandwidth and pulse energy. The laser output light beam of pulses then passes through an optical pulse stretcher (“OPuS”) 240 and an output combined autoshutter metrology module (“CASMM”) 250, which may also be the location of a pulse energy meter. One purpose of the OPuS 240 may be, e.g., to convert a single output laser pulse into a pulse train. Secondary pulses created from the original single output pulse may be delayed with respect to each other. By distributing the original laser pulse energy into a train of secondary pulses, the effective pulse length of the laser can be expanded and at the same time the peak pulse intensity reduced. The OPuS 240 can thus receive the laser beam from the PRA WEB 210 via the BAM 230 and direct the output of the OPuS 240 to the CASMM 250.

[0044] The MO and PA delay commands can be used to indicate to the TEM 310 how long after a reference trigger, e.g., a trigger T from a customer interface to issue the respective triggers to the respective, the pulse power systems 315. There may be one pulse power system for each of the MO and PA or PRA.

[0045] In an EUV light source, EUV may be produced by preparing a target distribution from a flying metal droplet via a laser pre-pulse and subsequently heating the target distribution to a plasma state with a second laser pulse. The pre-pulse laser hits the droplet to modify the distribution of the target material and the main-pulse laser hits the target to heat it to an EUV- emitting plasma. In some systems the pre-pulse and the main heating pulse are provided by the same laser system and in other systems there are two separate lasers. In some cases, the reflection of the main pulse from the formed target is used as a diagnostic of the formed target or target location. It is important to“target” the flying droplet to within a few micrometers for efficient and debris-minimized operation of the light source.

[0046] FIG. 3 is a not-to-scale schematic diagram of an EUV system 260 using both a prepulse and a main pulse. EUV system 260 includes, among other features, a radiation source 265 capable of producing a prepulse 267 and a later main pulse 268. The prepulse 267 and the main pulse 268 propagate into a chamber 285 including a collector mirror 287 where they strike a quantity of target material 290 at an irradiation site 295. In the example shown, the target material 290 is originally in the form of a stream of droplets released by a target material dispenser 292, which in the example is a droplet generator. The target material 290 can be ionized by a main pulse in this form. Alternatively, the target material 290 can be preconditioned for ionization with a pre-pulse that can, for example, change the geometric distribution of the target material 290. Thus it may be necessary both to hit the target material 290 accurately with the pre-pulse 267 to ensure the target material 290 is in the desired form (disk, cloud, etc.), and to hit the target accurately with the main pulse to promote efficient production of EUV radiation. All of this occurs under the control of a control circuit

[0047] Several systems have been used in the past to accurately strike the target material with the pre-pulse or the main pulse including use of reflected light from an operational pulse or the use of second laser or light source to illuminate the droplet. For example, U.S. Patent No. 7,372,056, issued May 13, 2008 and titled“LPP EUV Plasma Source Material Target Delivery System,” hereby incorporated herein in its entirety, discloses the use of a droplet detection radiation source and a droplet radiation detector that detects droplet detection radiation reflected from a droplet of target material.

[0048] FIG. 4 is a functional block diagram of circuitry that may be used to control the relative timing of firing of pulses, for example, the MO chamber 165 and the PRA chamber 200 in a DUV system or the prepulse and the main pulse in an EUV system. Shown in FIG. 4 is a Fire Control Circuit (FCC) 300 that may send MO and PA delay commands from an Energy and Timing Controller 305 to a Timing and Energy Module (TEM) 310. The TEM 310 may further send MO and PA commutator triggers to a pulse power system 315 to initiate the discharge of a charging capacitor (not shown) through a solid state switching element (not shown) in pulse power system 315. The respective triggers create the eventual gas discharge due to electrical energy provided to a respective pair of electrodes through a lasing gas medium between the electrodes in each of the respective MO and PA. In an EUV system, a module such as the TEM could be used, for example, to control the relative timing of the firing of the prepulse and the main pulse.

[0049] The main function of the TEM 310 is to create high precision delay pulses. A TEM such as TEM 310 may be used in both DUV and EUV systems. The principles disclosed here are useful for both DUV and EUV systems. In a DUV system, the TEM creates two pulses, one for Master Oscillator (MO) and one for Power Amplifier (PA). Existing specifications for these two pulses are:

1 - Pulse duration for MO and PA = 500ns

2- Maximum Delay from Reference Trigger to MO Commutator Trigger=

27us

3- Maximum Delay from Reference Trigger to PA Commutator Trigger=

27us

4- Delay Resolution for both MO and PA Trigger < 250ps

5- Delay Jitter for both MO and PA Trigger < 250ps

[0050] According to one aspect of an embodiment, circuitry including Field Programmable Gate Arrays (FPGA) in combination with Programmable Delay Chips (PDC) is used to create the necessary high precision delays. These devices used apart from one another have limitations. For example, FPGAs generally cannot create sub-nanosecond logic. PDCs have a fixed propagation delay to their first tap and the delay range is also very small. Combining these two technologies, however, permits overcoming these limitations.

[0051] FIG. 5 shows an example of a circuit combining an FPGA 400 with PDCs 410, 415, 420, and 425. In more detail, FPGA 400 receives a pulse data command and input trigger A. As a result, circuitry 440 within the FPGA 400 generates four signals, bl, b2, b3, and b4, under control of an oscillator 445. The first signal bl is applied to a programmable delay circuit 410 which delays propagation of the first signal bl. The second signal b2 is inverted by inverter 450 and supplied to a programmable delay circuit 415 which delays propagation of the second signal b2 by a second delay having a magnitude greater than the magnitude of the first delay. The outputs of programmable delay circuit 410 and programmable delay circuit 415 are applied to logic circuit 430 which may be, for example, an AND gate. The resulting signal Pl is used, for example, as a trigger for one chamber of a multi-chamber laser.

[0052] The third signal b3 is applied to a programmable delay circuit 420 which delays propagation of the third signal b3. The fourth signal b4 is inverted by inverter 450 and supplied to a programmable delay circuit 425 which delays propagation of the fourth signal b4 by a delay having a magnitude greater than the magnitude of the delay imposed on the third signal by programmable delay circuit 420. The outputs of programmable delay circuit 420 and programmable delay circuit 425 are applied to logic circuit 435 which may be, for example, an AND gate. The resulting signal P2 is used, for example, as a trigger for a second chamber of a multi-chamber laser.

[0053] The programmable delay circuits 410, 415, 420, and 425 are programmed by a programming module 460 which may be, for example, part of FPGA 400.

[0054] An example of a suitable FPGA for use as FPGA 400 is the Xilinx Kintex 7 FPGA

(Speedgrade -3). This FPGA is limited to maximum 800MHz (l.25ns) clock frequency. An example of a suitable PDC for use as PDCs 410, 415, 420, and 425 is the ON Semiconductor Programmable Delay Chip MC100EP196BMNG with a total available delay between 2.5ns~l3ns in lOps increments.

[0055] In the arrangement of FIG. 5, FPGA 400 is used to create coarse delays (which makes microsecond and millisecond delays possible as well). The PDCs 410, 415, 420, and 425 are used to create the fine (lOps increments) delays. In the above example a Phase Lock Loop (PLL) inside the FPGA 400 is used to create 400MHz clock (2.5ns period) , this 2.5ns period matches the delay to the first tap of the PDCs 410, 415, 420, and 425, thus making it possible to have a continuous delay range. In this case the coarse delay resolution is 2.5ns and fine delay resolution is 10 ps calculated by:

TotalCommanded Delay

[0056] Coarse Delay ( FPGA ) 2.5 xltr ⁹ 1

TotalCommandedDelay -(2.5 ⁹ x(Coarse Delay+1))

[0057] Fine Delay ( PDC )

[0058] FIG. 6 shows the creation of two lns wide pulses with lns spacing. One nanosecond is used as the base for FIG. 5 to clarify the drawing but it will be apparent to one of ordinary skill in the art that the same relative timing can be used in the circuit shown in FIG. 4 to generate picosecond resolution timings. As shown in FIG. 5, the top signal labeled“1 ns period” is the clock signal. The next signal proceeding downward in figure is labeled“bl” and is the first signal described above. As can be seen, the signal bl goes from a first logic level to a second logic level on the rising edge of the clock and then several clock cycles later transitions from the second logic level to the first logic level.

[0059] The next signal down, labeled“~b2”, is the logical inversion of signal bl. The next signal down, labelled“bl_Delayed_2ns”, is the signal bl delayed by two clock cycles. The next signal down, labelled“~b2_Delayed_3ns”, is the signal ~b2 delayed by three clock cycles. The next signal down, labelled “Pulse l_lns”, is the result of ANDing

“bl_Delayed_2ns” and“~b2_Delayed_3ns”. This results in a pulse lasting one clock cycle.

[0060] The next signal proceeding downward in figure is labeled b3 and is the third signal described above. As can be seen, the signal b3 goes from a first logic level to a second logic level on the rising edge of clock and then several clock cycles later transitions from the second logic level to the first logic level.

[0061] The next signal down, labeled“~b4”, is the logical inversion of signal b4. The next signal down, labelled“b3_Delayed_2ns”, is the signal b3 delayed by two clock cycles. The next signal down, labelled“~b4_Delayed_3ns”, is the signal ~b4 delayed by three clock cycles. The next signal down, labelled “Pulse 2_lns”, is the result of ANDing

“b3_Delayed_2ns” and“~b4_Delayed_3ns”. This results in a pulse lasting one clock cycle that is delayed from the first pulse by one clock cycle. The relative timing of the transition in signal bl and signal b3 determines the amount of delay between Pulse 1 and Pulse 2.

[0062] The jitter in digital systems is caused by instabilities in the oscillator electronics. For this reason use of any PPL/DCM/MMCM internal to the FPGA should be avoided when using FPGAs, which may suffer jitter in a range of about 50-100 ps. Depending on the demands of the design, an oscillator may be chosen with the right frequency stability. An example of such an oscillator is the Abracon LLC ASGTX-D-400.000MHZ-1 with a maximum jitter of l.8ps). Both analog and digital techniques suffer from jitter caused by thermal noise and external interference through power and ground.

[0063] The above description includes examples of multiple embodiments. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the aforementioned embodiments, but one of ordinary skill in the art may recognize that many further combinations and permutations of various embodiments are possible. Accordingly, the described embodiments are intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the appended claims. Furthermore, to the extent that the term“includes” is used in either the detailed description or the claims, such term is intended to be inclusive in a manner similar to the term“comprising” as“comprising” is construed when employed as a transitional word in a claim. Furthermore, although elements of the described aspects and/or embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated. Additionally, all or a portion of any aspect and/or embodiment may be utilized with all or a portion of any other aspect and/or embodiment, unless stated otherwise.

[0064] Other aspects of the invention are set out in the following numbered clauses.

1. A laser system comprising:

a field programmable gate array configured to generate a first digital signal transitioning from a first logic level to a second logic level for a plurality of clock cycles and a second digital signal which is a logical inverse of the first digital signal;

a first programmable delay circuit arranged to receive the first digital signal and configured to delay propagation of the first digital signal by a first delay to generate a delayed first digital signal;

a second programmable delay circuit arranged to receive the second digital signal and configured to delay propagation of the second digital signal by a second delay greater than the first delay to generate a delayed second digital signal; and

a first logic circuit arranged to receive the delayed first digital signal and the delayed second digital signal and configured to generate a pulse when and only when both the first digital signal and the delayed second digital signal are at the second logic level.

2. A laser system comprising:

a module configured to supply a first pulse having a first duration and a second pulse having a second duration with a start of the first pulse and a start of the second pulse being separated in time by a delay interval, the module comprising

a field programmable gate array configured to generate a first digital signal transitioning from a first logic level to a second logic level at a time tl for a plurality of clock cycles, a second digital signal which is a logical inverse of the first digital signal, a third digital signal transitioning from the first logic level to the second logic level at a time t2 later than tl for a plurality of clock cycles, and a fourth digital signal which is a logical inverse of the third digital signal,

a first programmable delay circuit arranged to receive the first digital signal and configured to delay propagation of the first digital signal by a first delay to generate a delayed first digital signal, a second programmable delay circuit arranged to receive the second digital signal and configured to delay propagation of the second digital signal by a second delay greater than the first delay to generate a delayed second digital signal,

a first logic circuit arranged to receive the delayed first digital signal and the delayed second digital signal and configured to generate the first pulse when and only when both the first digital signal and the delayed second digital signal are at the second logic level,

a third programmable delay circuit arranged to receive the third digital signal and configured to delay propagation of the third digital signal by a third delay to generate a delayed third digital signal,

a fourth programmable delay circuit arranged to receive the fourth digital signal and configured to delay propagation of the fourth digital signal by a fourth delay greater than the third delay to generate a delayed fourth digital signal, and

a second logic circuit arranged to receive the delayed third digital signal and the delayed fourth digital signal and configured to generate the second pulse after cessation of the first pulse when and only when both the delayed third digital signal and the delayed fourth digital signal are at the second logic level.

3. The laser system as in clause 2 wherein the laser system is a system for generating deep ultraviolet radiation and further comprising

a first trigger circuit arranged to receive the first pulse and for causing a first chamber of the laser to fire in response to the first pulse and

a second trigger circuit arranged to receive the second pulse and for causing a second chamber of the laser to fire in response to the second pulse.

4. The laser system as in clause 2 wherein the laser system is a system for generating extreme ultraviolet radiation and further comprising

a first trigger circuit arranged to receive the first pulse and for causing a first laser pulse to fire in response to the first pulse and

a second trigger circuit arranged to receive the second pulse and for causing a second laser pulse to fire in response to the second pulse.

5. The laser system as in clause 2, further comprising

a first laser chamber arranged to receive a first laser chamber energizing pulse based on the first pulse, and

a second laser chamber arranged to receive a second laser chamber energizing pulse based on the second pulse.

6. A method of generating trigger pulses for a laser system, the method comprising: generating a first digital signal transitioning from a first logic level to a second logic level for a plurality of clock cycles and a second digital signal which is a logical inverse of the first digital signal;

delaying propagation of the first digital signal by a first delay to generate a delayed first digital signal;

delaying propagation of the second digital signal by a second delay greater than the first delay to generate a delayed second digital signal; and

generating a pulse when and only when both the first digital signal and the delayed second digital signal are at the second logic level.

7. A method of generating trigger pulses for a laser system, the method comprising: generating a first digital signal transitioning from a first logic level to a second logic level at a time tl for a plurality of clock cycles and a second digital signal which is a logical inverse of the first digital signal;

delaying propagation of the first digital signal by a first delay to generate a delayed first digital signal;

delaying propagation of the second digital signal by a second delay greater than the first delay to generate a delayed second digital signal;

generating a first pulse when and only when both the first digital signal and the delayed second digital signal are at the second logic level;

generating a third digital signal transitioning from the first logic level to the second logic level at a time t2 later than tl for a plurality of clock cycles, and a fourth digital signal which is a logical inverse of the third digital signal,

delaying propagation of the third digital signal by a third delay to generate a delayed third digital signal,

delaying propagation of the fourth digital signal by a fourth delay greater than the third delay to generate a delayed fourth digital signal, and

generating a second pulse after cessation of the first pulse when and only when both the delayed third digital signal and the delayed fourth digital signal are at the second logic level.

8. The method as in clause 7 further comprising:

supplying the first pulse as a trigger to a power commutator of a first chamber of a multi chamber laser; and

supplying the second pulse as a trigger to a power commutator of a second chamber of a multi chamber laser. 9. The method as in clause 7 wherein the steps of generating the first, second, third, and fourth digital signals are carried out by a field programmable gate array.

10. The method as in clause 7 further comprising the steps of

supplying the first pulse as a trigger to fire a first pulse at a target material and

supplying the second pulse as a trigger to fire a second pulse at the target material.

11. The method as in clause 7 wherein the first pulse is a prepulse and the second pulse is a main pulse.

12. The method as in clause 7 wherein the step of delaying the first digital signal is performed by a first programmable delay circuit.

13. The method as in clause 7 wherein the step of delaying the second digital signal is performed by a second programmable delay circuit.

14. The method as in clause 7 wherein the step of delaying the third digital signal is performed by a third programmable delay circuit.

15. The method as in clause 7 wherein the step of delaying the fourth digital signal is performed by a fourth programmable delay circuit.