Apparatus and Method for Segmentation of a Memory Device

BACKGROUND

[0001] Each core access in a dynamic random access memory (DRAM) generally involves a pair of row operations commonly referred to as a row activation and a row precharge or precharge. In a row activation, an address-specified word line is activated to couple a corresponding row of DRAM storage cells (each cell formed, for example, by a transistor switch and a capacitive element) to bit lines that extend along respective columns of DRAM cells to a bank of sense amplifiers. The row activation is usually destructive, as the charge levels on the capacitive storage elements are drained to impress the corresponding data values onto the bit lines. In a typical implementation, the sense amplifiers operate regeneratively, each sense amplifier latching and amplifying the data signal received via a respective bit line and driving the amplified signal back onto the bit line (or bit line pair) to restore the data output from the corresponding DRAM cell. In a precharge operation, the word line is deactivated to electrically isolate the DRAM cells from the bit lines and the bit lines are driven to a neutral voltage (e.g., midway between logic "T and logic '0' charge levels that may be recorded within the DRAM cells) in preparation for a subsequent row activation. [0002] DRAM chips consume a significant amount of power during row operations, a characteristic that is worsening as cell density increases. That is, increased column count (i.e., number of DRAM cells per row) results in proportionally more power per row operation, and increased row count extends the bit line length (and thus the bit line resistance and capacitance) so that more power is consumed per column to convey data between sense amplifier and selected storage cell.

Further, retention time is generally inversely proportional to cell size, so that smaller storage cells usually require more frequent refresh to avoid data loss (each refresh being effected by a row activation and precharge), consuming yet more power. This trend toward increased power consumption is particularly problematic for battery powered devices (e.g., ever more prevalent portable or mobile electronic devices) as increased density and storage capacity comes at the expense of reduced battery life.

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The accompanying drawings, that are incorporated in and form a part of this specification, illustrate embodiments discussed below, and, together with the description, serve to explain the principles of the disclosure:

[0004] Figure 1 shows a bit line having two segments and a segment switch located between the segments.

[0005] Figure 2 shows a bit line having two segments, a transistor implemented segment switch located between the two segments, and a control signal controlling the transistor.

[0006] Figure 3A shows an embodiment of a storage array 301 having a non- alternating bit line configuration.

[0007] Figure 3B shows an embodiment of a storage array having an alternating bit line configuration.

[0008] Figure 4 shows a memory array 401 coupled to a row of sense amplifiers

405 in a non-alternating bit line configuration. [0009] Figure 5 shows a bit line that has two segment switches and at least three bit line segments.

[00010] Figure 6 shows a memory array that is segmented into three memory regions by virtue of two rows of segment switches in a non-alternating bit line configuration. [00011] Figure 7A shows a row decoder and circuitry for controlling the segment switches in a non-alternating bit line configuration.

[00012] Figure 7B shows an embodiment of an alternating bit line configuration, whereby the segment switches are controlled by a core segmentation controller.

[00013] Figure 8 is a flowchart depicting the memory array segmentation process. [00014] Figure 9 shows a memory array segmentation with multiple latencies.

[00015] Figure 10 shows an embodiment of a system having devices with segmented cores and multiple access latencies.

[00016] Figure 11 shows a flowchart of the allocation of data to segmented regions of a memory.

[00017] Figure 12 shows memory latencies associated with Read and Write operations.

[00018] Figure 13A shows a top view of an example of an open bit line layout with segment switches for a non-alternating bit line configuration. [00019] Figure 13B shows an embodiment of a non-alternating configuration of a folded bit line layout in which the reference bit line extends across the same array as the bit line being used for data access.

[00020] Figure 14A shows an alternating, segmented bit line configuration for an open bit line embodiment. [00021] Figure 14B shows another embodiment which combines the alternating bit line embodiment of Figure 14A and the folded bit line embodiment of Figure 13B .

[00022] Figure 15 illustrates the transistor switching element provided for segmentation control to effect a bit line crossing.

[00023] Figure 16 illustrates an embodiment of a non-alternating folded bit-line array that employs the transistor-effected bit line crossing of Figure 15.

[00024] Figure 17 shows a system having a memory with memory array segmentation.

DETAILED DESCRIPTION [00025] Embodiments in the present disclosure pertain to an apparatus and method for segmentation in a memory device. A bit line is comprised of at least two bit line segments switchably coupled to one another by a segment switch. The segment switch is placed in-between the two bit line segments. The segment switch is selectively controlled (i.e., switched to either a conducting state or non-conducting state) to electrically couple or isolate a first one of the bit line segments to/from a second one of the bit line segments and thus to/from a sense amplifier coupled to the second one of the bit line segments. When the first bit line segment is electrically isolated from the second bit line segment (and therefore from the sense amplifier), an open-circuit or high-resistance path is formed between the first and second bit line segments so that negligible or no current may flow between the first and second bit line segments and the capacitance and resistance associated with the first bit line segment is electrically isolated from the sense amplifier. This decreases the amount of power dissipated during both Refresh and Read/Write operations. Furthermore, isolating one of the bit line segments from the sense

amplifier can reduce the time associated with transferring data between a sense amplifier and a memory cell, and thus the overall memory access latency (e.g., the time between issuance of a memory read request and return of Read data or the time between issuance of a memory Write request and the data being written to a memory cell) is reduced. Embodiments in the present disclosure can be applied to both non-alternating bit line as well as alternating bit line configurations. In a non- alternating bit line configuration, the sense amplifiers all reside on the same side of the ends of the bit lines. In an alternating bit line configuration, the sense amplifiers alternate between which of the two ends of the bit lines they respectively reside. [00026] Figure 1 shows a bit line 100 comprised of two bit line segments 102 and 103 and a segment switch 101 that is placed in-between bit line segments 102 and 103. The segment switch 101 can be controlled to be conducting or non-conducting (conducting small or negligible amount of current). Bit line 100 connects a column of memory cells 105 to a sense amplifier 104. Each memory cell includes a capacitor and a transistor. When segment switch 101 is non-conducting, segment 103 is electrically isolated from the sense amplifier 104. With segment switch 101 in a nonconducting state (i.e., switched off such that no or negligible current flows between switch terminals), the charge stored on a capacitor of a memory cell connected to segment 102 needs only to drive bit line segment 102 in order to be detected by sense amplifier 104. By electrically isolating bit line segment 103 from the sense amplifier 104, the capacitance and resistance associated with bit line segment 103 is electrically isolated from the sense amplifier 104. Isolating the capacitance from the sense amplifier 104 is desirable because less charge is needed to drive the signal to the sense amplifier, and hence, less power is consumed. [00027] Furthermore, isolating the capacitance associated with bit line segment 103 can reduce the minimum signal that can be read by sense amplifier 104 from memory cells 105. Reducing the minimum signal that can be read by sense amplifier 104 may increase the required interval between refresh operations for memory cells associated with bit line segment 103, thereby reducing the average power required to refresh these memory cells.

[00028] Furthermore, isolating the capacitance and resistance associated with bit line segment 103 from sense amplifier 104 reduces the time associated with transferring data between a sense amplifier and a memory cell. Although a simple switch is depicted, the segment switch 101 can be an N-channel transistor, P-

channel transistor, pass gate (e.g., PMOS transistor coupled in parallel with an NMOS transistor), multiplexer, or a non-volatile element. It should be noted that reading the cell is a charge-sharing operation. Consequently, the segment device does not directly affect the signal level, although it will slightly increase the time to completely transfer the charge. The resistance of the segment switch will slightly increase the time it takes to write or restore data to the cell. [00029] When segment switch 101 is conducting, bit line segments 102 and 103 are electrically coupled to the sense amplifier 104. With segment switch 101 conducting, all memory cells coupled to segment 103 are electrically coupled to sense amplifier 104. For example, with segment switch 101 conducting, the charge stored in capacitor 106 of memory cell 107 can be sensed and amplified by sense amplifier 104 through bit line segments 103 and 102.

[00030] Although Figure 1 shows the case where the sense amplifier 104 is coupled to one end (e.g., the bottom end) of the bit line 100, it is disclosed that sense amplifier 104 can alternatively be coupled to the opposite end of the bit line 100 (e.g., the top end). Coupling the sense amplifier to the top of bit line 100 means that when switch 101 is non-conducting, bit line segment 102 is electrically isolated from the sense amplifier [00031] Figure 2 shows a more detailed description of embodiments of the disclosure. A bit line 200 is comprised of an N-channel transistor 201 , bit line segment 202, and bit line segment 203. N-channel transistor 201 functions as a segment switch and is located between the two bit line segments 202 and 203. Bit line 200 can be any number of memory cells in length. Bit line segment 202 couples a sense amplifier 204 to N-channel transistor 201. Bit line segment 203 extends from the N-channel transistor 201 to the last memory cell that is furthest away from the sense amplifier 204. A control signal on line 207 is used to selectively cause N- channel transistor 201 to be conducting or non-conducting, depending on which memory cells are being accessed. The control signal causes N-channel transistor 201 to be conducting when accessing a memory cell coupled to segment 203. In this case, both bit line segments 202 and 203 are electrically coupled to the sense amplifier 204. Conversely, the control signal causes N-channel transistor 201 to be non-conducting when accessing a memory cell coupled to bit line segment 202. In this case, only bit line segment 202 is electrically coupled to the sense amplifier 204. This electrically isolates segment 203 from the sense amplifier 204. Consequently,

sense amplifier 204 is electrically isolated from the capacitance and resistance associated with bit line segment 203. In one embodiment, when N-channel transistor 201 is non-conducting, segment 203 is not coupled to any sense amplifier. For some storage technologies, this may mean that segment 203 is left floating, but for other storage technologies it may not be floating.

[00032] In one embodiment, a control circuit determines, based on incoming row address values of the memory cells being accessed, whether the memory cells are coupled to bit line segment 202 or to bit line segment 203. The control circuit then outputs the correct control signal to selectively cause N-channel transistor 201 to be conducting or non-conducting. For example, the control signal causes N-channel transistor 201 to conduct when performing self-refresh, refresh, and row activation operations for those memory cells associated with segment 203. A normal amount of power is dissipated under these conditions. However, the control signal causes N-channel transistor 201 to be non-conducting when performing self-refresh, refresh, and row activation operations for those memory cells associated with bit line segment 202. This causes the capacitance and resistance associated with bit line segment 203 to be isolated from sense amplifier 204. A lower capacitance and resistance directly translates into lower power consumption and reduces the time associated with transferring data between a sense amplifier and a memory cell. Note that for the case where N-channel transistor 201 is in a conducting state, the control signal 207 may have to be brought to a voltage level higher than the highest voltage of bit line 200 by at least the threshold voltage associated with N-channel transistor 201 to ensure that data is fully restored to memory cells associated with bit line segment 203. [00033] Furthermore, in one embodiment, distinct precharge circuits may be provided to precharge respective bit line segments. Alternatively, the distinct precharge circuits may be ganged together when precharging multiple segments. Alternatively, a single precharge circuit may be configurable during device operation to provide different levels of precharge currents, depending on which segment is being accessed. Alternatively, a single precharge circuit may be configurable at runtime by a host (e.g., via on-chip programmable registers or other storage circuits coupled to or included within the precharge circuit) to provide different levels of precharge currents, depending on which segment is being accessed. For precharging that entails multiple segments, the precharge voltage generator may

provide more current than for precharging that entails single or lesser number of segments.

[00034] Same as with Figure 1 , the sense amplifier 204 can alternatively reside on the other end of bit line 200. In this case, bit line segment 202 would be electrically isolated from the sense amplifier when the control signal causes transistor 202 to be non-conducting.

[00035] Figure 3A shows an embodiment of a storage array 301 having a non- alternating bit line configuration. In this particular embodiment, an 8x8 array is shown (the dashed box 304 represents the circuit as shown in Figure 2). A row of segment switches 302 is placed in the middle of the array (e.g., in-between the fourth and fifth rows of memory cells). The segment switches 302 segment the top half of the memory array from the bottom half. When performing self-refresh, row activate, and refresh operations on the top half of the 8x8 memory array, the segment switches 302 are conducting. This electrically couples the top half of the 8x8 memory array to the sense amplifiers 303. When accessing the memory cells (e.g., performing self-refresh, row activate, and refresh operations) on the bottom half of the 8x8 memory array, the segment switches 302 are non-conducting. This electrically isolates the top half of the 8x8 memory array from the sense amplifiers 303. By isolating the top half of the 8x8 memory array, the capacitance and resistance associated with the top half of the 8x8 memory array are, likewise, electrically isolated from the sense amplifiers 303. This translates into power saving and decreased memory latency for refresh and self-refresh operations, as well as activate operations. In modern DRAM memory arrays, which can have many more than eight rows, segmenting half of the DRAM memory array and accessing a row of cells in the between the segment switches and the sense amplifiers can result in up to approximately a 38-39% reduction in refresh and row activation power in normal operation when compared to a DRAM memory array that does not use segment switches. Furthermore, in a modern DRAM memory array, segmenting one sixteenth of the DRAM memory array and accessing a row of cells in the between the segment switches and the sense amplifiers can result in up to approximately a 72-73% reduction in refresh and row activation power in normal operation when compared to a DRAM memory array that does not use segment switches. [00036] The power savings and reduction in the time associated with transferring data between a sense amplifier and a memory cell comes at the expense of adding

the segment switches 302. In one embodiment, the addition of the segment switches 302 adds approximately 2.4% to the die area for a modern DRAM memory array design. This is a reasonable trade off based on industry experience and is within the acceptable die area impact for a value-added feature. By comparison, the die area grows by approximately 13.7% to achieve the same bit line capacitance as that of the segmented portion of the DRAM memory array (in a system with half memory array segmentation) by halving the length of segments electrically coupled to the sense amplifiers and doubling the number of sense amplifiers. Thus, memory array segmentation offers a superior trade off between power savings and die area for DRAMs.

[00037] The segment switches may be placed to segment the memory array at one-half, one-fourth, one-eighth, one-sixteenth, etc. of the memory array or at any arbitrary location. During operation, the DRAM storage cells need to be refreshed. The amount of power saved over the course of refreshing all the DRAM storage in the array cells (full-array refresh) depends on the location of the segment switches. With the segment switches placed at one-fourth of the memory array, refreshing one- fourth of the DRAM storage cells will consume lower power, and refreshing three- fourths of the DRAM storage cells will consume higher power. The total power consumed when refreshing all DRAM storage cells is a weighted average of the powers consumed when refreshing the individual DRAM storage cells. Compared to a memory array that does not implement segmentation, a DRAM with segment switches that can isolate one-half of the DRAM storage cells reduces total refresh power across all DRAM storage cells by approximately 34-35% in a modern DRAM. Compared to a memory array that does not implement segmentation, a DRAM with segment switches that can isolate one-fourth of the DRAM storage cells reduces total refresh power across all DRAM storage cells by approximately 22-23% in a modern DRAM. Compared to a memory array that does not implement segmentation, a DRAM with segment switches that can isolate one-eighth of the DRAM storage cells reduces total refresh power across all DRAM storage cells by approximately 12% in a modern DRAM. Compared to a memory array that does not implement segmentation, a DRAM with segment switches that can isolate one- sixteenth of the DRAM storage cells reduces total refresh power across all DRAM storage cells by approximately 6-7% in a modern DRAM. Thus, substantial average power saving is achieved with memory array segmentation during normal operation

or full-array refresh. The amount of power savings depends on where the segment switches are placed in the array.

[00038] Figure 3B shows an embodiment of a storage array having an alternating bit line configuration. The bit lines of the 8x8 array are alternately coupled to either sense amplifiers 305 or 306. The bit line switches 307 are arranged in two rows. One row corresponds to the bit lines coupled to sense amplifiers 305, whereas the other row corresponds to the bit lines coupled to sense amplifiers 306. This alternating bit line configuration saves power, but at approximately half of the savings as that of the non-alternating configuration. [00039] In one embodiment, memory array segmentation may be used in conjunction with selective refresh techniques (e.g. Partial Array Self Refresh (PASR)) that enable selective control over portions of the DRAM array to be self- refreshed. Power saving is achieved because the other, non-designated portions of the memory need not be refreshed (i.e., generally, not refreshing unused portions of the memory array). Write and Read operations can still occur, but only the designated regions (or portions) of the array are refreshed during self-refresh. During self-refresh, data in regions that are not designated will be lost, but important data can be kept in the portion of the memory designated for self-refresh. [00040] Figure 4 shows a memory array 401 coupled to a row of sense amplifiers 405 in a non-alternating bit line configuration. The memory array 401 is segmented into portions 403 and 404 by segment switches. An 8x8 memory array 401 is shown for ease of illustration, although memory array 401 can have more or less memory cells. During normal mode of operation, data can be stored in the entire memory array 401 without being lost because the entire memory array 401 is refreshed. In one embodiment, a quarter array memory array segmentation with a corresponding quarter array selective-refresh is implemented. For a quarter array selective-refresh operation, only a quarter of the array is self-refreshed. For an 8x8 array, the bottom two rows 403 are self-refreshed. The top six rows 404 are not self-refreshed. The result is that during self-refresh, only the bottom two rows 403 retain data, and data stored in the top six rows 404 can be lost (or no valid or meaningful data has been stored in those rows). In order to implement a quarter memory array segmentation, segment switches 402 are placed in-between the second and third rows. In other words, the segment switches 402 can segment one-quarter of the rows from the rest of the rows in the array. During a normal mode of operation, segment switches 402

are selectively switched to be conducting or non-conducting to achieve power saving as described above. However, during self-refresh, additional power savings is achieved by causing the segment switches 402 to be non-conducting. Keeping the segment switches 402 non-conducting means that the sense amplifiers 405 are electrically isolated from the capacitance and resistance associated with the bit line segments of the top six rows 404 throughout the selective refresh mode. For the quarter array selective-refresh with quarter memory array segmentation as depicted in the example of Figure 4, approximately 58-59% power saving can be achieved when compared to a memory array without segment switches that selectively refreshes one quarter of the memory array. In other embodiments, for a half array selective-refresh with half memory array segmentation, approximately 38-39% power saving can be achieved. For an eighth array selective-refresh with an eighth memory array segmentation, approximately 67-68% power saving can be achieved. For a sixteenth array selective-refresh with a sixteenth memory array segmentation, approximately 72-73% power saving can be achieved.

[00041] In similar fashion, embodiments of the present disclosure can have quarter, eighth, and sixteenth memory array segmentation in an alternating bit line configuration. Two rows of bit line switches would be implemented. Each of the two rows would be located one-quarter, one-eighth, and one-sixteenth of the array from their respective sense amplifiers.

[00042] In one embodiment, a bit line can be segmented into more than two bit line segments by implementing two or more segment switches. For example, Figure 5 shows a bit line that is segmented by at least two segment switches 504, 505 into at least three bit line segments 501 , 502, and 503. The bit line segments 501 , 502, 503 may have the same or different lengths and may each extend past and be coupled to any number of associated memory cells (e.g. where the segment length is proportional to the number of memory cells to which the segment is coupled) . Each of the segment switches 504 and 505 is selectively controlled to be conducting or non-conducting. When accessing memory cells corresponding to bit line segment 503, both segment switches 504 and 505 are conducting. This electrically couples the memory cells of bit line segment 503 to the sense amplifier 506. When accessing memory cells corresponding to bit line segment 502, segment switch 504 is conducting. This enables the memory cells of bit line segment 502 to be electrically coupled to the sense amplifier 506. However, segment switch 505 is

non-conducting. This electrically isolates the sense amplifier 506 from the capacitance and resistance associated with bit line segment 503. When accessing memory cells corresponding to bit line segment 501 , the segment switch 504 is nonconducting, and segment switch 505 can be either conducting or non-conducting. A non-conducting segment switch 504 electrically isolates the sense amplifier 506 from the capacitance and resistance associated with bit line segments 502 and 503. [00043] It should be noted that both the non-alternating and the alternating bit line configuration can have bit lines which are segmented into three or more bit line segments. [00044] Figure 6 shows a memory array that is segmented into three memory regions by virtue of two rows of segment switches in a non-alternating bit line configuration. In one embodiment, memory region 602 is electrically coupled to the sense amplifiers 601 via their respective bit lines. When accessing memory region 602, the segment switches 603 are non-conducting. This electrically isolates the sense amplifiers 601 from the capacitance and resistance associated with memory regions 604 and 606. When accessing memory region 604, the segment switches 603 are conducting, and the segment switches 605 are non-conducting. The capacitance and resistance associated with memory region 606 is electrically isolated from the sense amplifiers 601. In order to access portion 606, the segment switches 603 and 605 are controlled to be conducting. In other embodiments, more rows of segment switches can be incorporated to provide additional memory array segmentation. Adding rows of segment switches incrementally decreases power consumption but comes at a cost of die area for implementing the segment switches. [00045] In one embodiment of a non-alternating bit line configuration, the segment switches are controlled by a core segmentation controller as shown in Figure 7A. A row decoder 701 is coupled to the word lines 702-704. The row decoder 701 responds to an incoming row address by decoding the row address information to activate corresponding word lines corresponding to the rows that are to be self- refreshed, refreshed, or activated. A core segmentation controller 720 is coupled to the gates of the segment switches 706-708 through control line 705. It is the function of the core segmentation controller to control the segment switches 706- 708. In one embodiment, the core segmentation controller compares the row address information to the location of the segment switches 706-708. If the row address information indicates that the row being accessed is above the segment

switches 706-708 (e.g., the received row address information is greater than or equal to a row address stored in memory that corresponds to the relative position of the segment switches), the core segmentation controller causes segment switches 706- 708 to conduct. Otherwise, the core segmentation controller 720 causes segment switches 706-708 to be non-conducting. Consequently, the core segmentation controller 720 can be programmed to automatically control the segment switches 706-708 as appropriate by using existing address information. The same address information that is used to select the word lines can be used to also control the segment select signal. This means that there need not be any added external pins for a memory chip to implement the memory array segmentation. The power saving and reduction in the time associated with transferring data between a sense amplifier and a memory cell can happen automatically without any intervention by the user. In one embodiment, the core segmentation controller 720 can be made part of the row decoder circuit 701. [00046] Alternatively, the segment switches can be controlled by something outside of the DRAM, such as by a memory controller or a CPU. A control register can be used that controls the segment switches based on an operating mode. The memory array segmentation control signal can originate from a memory controller or CPU. The control signal instructs the core segmentation controller on when to perform the memory array segmentation process. The row decoder can be instructed to selectively enable and disable the memory array segmentation feature. Consequently, the segment select signals can be explicitly controlled externally. [00047] In one embodiment, mode-programmability is provided to enable and disable the array segmentation feature. For example, a bit can be set in a mode register to disable the array segmentation. This mode-programmability feature is applicable to both the external control case as well as the internal control case as described above.

[00048] Figure 7B shows an embodiment of an alternating bit line configuration, whereby the segment switches are controlled by a core segmentation controller similar to the one shown in Figure 7A. In the case of the alternating bit line configuration, it should be noted that for any row of cells accessed, some of the sense amplifiers will be attached to bit lines with non-conducting segment switches while other sense amplifiers will be attached to bit lines with conducting segment select switches. For example, when accessing word line 702, the core segmentation

controller 720 generates two segmentation control signals. One segmentation control signal is output on line 705 and causes segment switches 705 and 706 to be conducting, thereby coupling the data to sense amplifiers 709 and 710. The other segmentation control signal is output on line 713 and causes segment switches 707 and 714 to be non-conducting, thereby electrically isolating bit line segments from sense amplifiers 711 and 712. Conversely, when accessing word line 704, the segmentation control signals cause segment switches 705 and 708 to be nonconducting while segment switches 707 and 714 are controlled to be conducting. Because of this, the time associated with transferring data from the sense amplifier and a memory cell will be different between different sense amplifiers. Furthermore, in one embodiment, column addresses associated with sense amplifiers 709 and 710 are different from column addresses associated with sense amplifiers 711 and 712. In this way, different column addresses may have different access latencies. In many DRAM devices, a column access reads data from or writes data to multiple sense amplifiers in parallel. This data is then serialized at the I/O pads of the device. In another embodiment, data needed early in the data serialization sequence is associated with sense amplifiers with lower access latency while data not needed until later in the data serialization sequence is associated with sense amplifiers with higher access latency. In this way, the overall time needed to read or write data may be reduced.

[00049] Figure 8 is a flowchart depicting the process of accessing data in a device with memory array segmentation and one row of segment switches. In step 801 , a row is selected for Read or Write access. A determination is made in step 802 as to where that row is located. In one embodiment, the determination is made by using the row address information, provided as part of a row activation or precharge operation. If the row is located between the segment switch and the sense amplifier, the segment switch is turned off (e.g., non-conducting), step 803. However, if the segment switch is between the row and the sense amplifier, the segment switch is turned on (e.g., conducting), step 804. Turning on the segment switch enables the row to be electrically coupled to the sense amplifier. After selectively turning on or off the segment switch as appropriate, the row is accessed according to step 805. [00050] As described above, by electrically isolating capacitance and resistance associated with a segment of the bit line from the sense amplifier, segmenting the memory array results in reduced access latencies. Figure 9 shows a memory

system having multiple latencies in a non-alternating bit line configuration. Nine memory devices 901 -909 are shown. Each of the memory devices is segmented into two portions by virtue of segment switches, though segmentation into more than two portions may be effected by additional segment switches in alternative embodiments. For example, memory device 901 has a row of segment switches which segments the memory device into portion 911 and portion 914. Likewise, memory device 904 has a row of segment switches which segments the memory device into portions 917 and 920. Memory device 907 has a row of segment switches which segments the memory device into portions 923 and 926. Although the figure shows equally divided portions, the row of segment switches of a memory device can be placed to have different sized portions. The different portions of a memory device have different access latencies. For example, portion 911 has a lower access latency than portion 914 of memory device 901. For memory device 904, portion 917 has a lower access latency than portion 920. And for memory device 907, portion 923 has a lower access latency than that of portion 926. [00051] Moreover, the distance of the memory device relative the memory controller 930 affects access latencies. Because some memory devices are further down the memory bus from the memory controller 930, they actually have longer latencies due to propagation delay, or perhaps incur additional time to pass through buffer chips. In this case, it's possible that the time from when the memory controller 930 issues the sequence of commands to activate and read data from a DRAM, that some memory devices might respond in X clock cycles, while others may take X+1 clock cycles, from the viewpoint of the memory controller 930. [00052] For example, memory device 904 is further away from memory controller 930 than memory device 901. Consequently, portion 917 of memory device 904 can have a higher access latency than that of portion 911 of memory device 901. In addition, portion 920 of memory device 904 has a higher access latency than portion 914 of memory device 901. Portions that have approximately the same access latencies can be assigned to a given group. For example, portion 914 of memory device 901 may have approximately the same access latency as portion 917 of memory device 904. Portion 917 is part of memory device 904, which is further away from memory controller 930 than memory device 901. However, due to memory array segmentation, portion 917 transfers data from a memory cell to a sense amplifier faster than that of portion 914. Consequently, portions 914 and 917

may have the same memory latency. The portions can be grouped based on their respective memory latencies. Portions 911 -913 can be assigned to Group I; portions 914-919 can be assigned to Group II; portions 920-925 can be assigned to Group III; and portions 926-928 can be assigned to Group IV. Group I has the lowest access latencies. Group Il has slightly higher access latencies than Group I, Group III has higher access latencies than Group II, and Group IV has the highest access latencies.

[00053] Likewise, portions of the memory devices can be grouped based on their respective power consumption. For example, portions 911 -913, 917-919, and 923- 925 consume less power than portions 914-916, 920-922, and 926-928. The memory mapping can be performed in a manner that takes advantage of the different power savings. For example, software applications that issue a significant number of memory requests can map their memory address space so that the most frequent memory accesses consume the least power. By mapping the memory address space relative to software applications' number of memory requests, the performance per watt is improved.

[00054] Figure 10 shows an embodiment of a system having devices with segmented cores and multiple access latencies in a non-alternating bit line configuration. A memory controller 1040 is coupled to control memory modules 1041 -1044. Each of the memory modules contains memory devices that implement memory array segmentation. As depicted, each memory device is segmented into two portions. The portions which exhibit the same approximate access latency are grouped together. In this example, there are five groups (Group I - Group V). Accessing the memory addresses of one particular Group results in the same access latency.

[00055] By grouping the portions of memory based on their respective access latencies, the memory address space can be mapped to these latency groups to optimize overall performance. For example, software applications that are particularly sensitive to access latencies can have their memory references mapped to a physical portion that has lower access latency (e.g., Group 1 ). The memory mapping can be performed in a manner that enhances the advantages of the memory array segmentation. By preferentially mapping the memory address space so that applications with the largest number of latency-sensitive memory requests access the lowest latency areas of the memory space, the memory is mapped to

make efficient use of memory array segmentation in terms of access latencies and increase performance.

[00056] Techniques to identify entire applications or portions of applications with frequent memory accesses can be combined with the ideas disclosed in this application for segmentation of a memory device to achieve improved performance and/or lower power consumption. Modern operating systems monitor application memory usage, and modern processors include performance counters that can track memory accesses. Users can also identify applications or parts of applications that use memory frequently, or that would benefit from faster memory accesses or lower power memory accesses. Once identified, these applications or parts of applications can have all or part of their data allocated to the lower latency and/or lower power portions of the physical address space. Alternatively, operating systems can identify applications or parts of applications that use memory frequently and migrate their data to lower latency and/or lower power portions of the physical address space. Programming languages also have the ability to allow portions of application data to be designated with special identifiers. This concept can be combined with segmentation of a memory device by defining keywords (such as the C programming language keyword "volatile" that indicates that a variable should reload its contents from memory rather than keep a copy in registers) that instruct the program to allocate code and/or data into lower latency and/or lower power portions of the address space. Although the techniques presented here are not an exhaustive list, they represent some of the ways that applications or portions of applications can be identified, and when combined with segmentation of a memory device can result in higher performance and/or lower power consumption. [00057] Figure 11 shows a flowchart for allocation of data to segmented regions of a memory device. The first step 1101 identifies an application and/or data that can benefit from reduced latency and/or reduced power. Next, step 1102 allocates or migrates an application and/or data to the segmented region of the address space. [00058] It should be noted that access latencies refer to both Read and Write operations. Figure 12 shows memory latencies associated with Read and Write operations. The access latency for a Read operation is depicted as tRCD, Read, which corresponds to the time after a row activate command is issued until a Read command can be issued. For Writes, there are two latencies of interest. The first latency of interest is tRCD, Write which in this case is the time after a row activate

command is issued until a Write command can be issued. The second latency of interest, specific to Writes, is tWRP. The tWRP access latency corresponds to the time after a Write command is specified until the time a Precharge operation can begin. Bit line segmentation reduces not only tRCD, Write but also tWRP latencies for rows in the portion of the array whereby the bit line segmentation reduces the time required to move the data on a Write operation into the memory core. Note that different values of tRAS, MIN (the minimum time between a row activate operation and a precharge operation) may apply to the memory cells that are above and below the switch. [00059] Semiconductor layouts for implementing memory array segmentation are shown and described in reference to Figures 13A-B, 14A-B, and 15A-15B. Figure 13A shows a top view of an example of an open bit line layout with segment switches for a non-alternating bit line configuration. A sense amplifier (SA) 1301 is coupled to a bit line segment 1306 and reference bit line segment 1305 (note that the functions of segments 1305 and 1306 are may changeed according to the array being accessed, with segment 1306 being the reference bit line segment in an access to the array coupled to segment 1305). A sSegment switch 1307 (e.g., formed by a transistor), switchably couples bit line segments 1306 and 1309, and segment switch 1303 switchably couples reference bit line segments 1305 and 1302. In the particular embodiment shown, transistors 1303 and 1307 are switched between conducting and non-conducting states based on the potential applied to control lines 1304 and 1308 respectively. Note that the control lines 1304 and 1308 can be implemented by any conductive structure and extend, for example, across all the bit lines and reference bit lines in the array or any portion thereof. Further, in one embodiment, control lines 1304 and 1308 may be coupled together and driven by a single driver or may be electrically distinct and driven by separate drivers (the control lines being activated or deactivated concurrently in both cases). [00060] Figure 13B shows an embodiment of a non-alternating configuration of a folded bit line layout in which the reference bit line extends across the same array as the bit line being used for data access (in contrast to Figure 13A which depicts bit line and reference bit line extending across distinct different arrays). More specifically, sense amplifier 1310 is coupled to a bit line formed by bit line segments 1311 and 1314 (and which are switchably coupled to one another by transistor 1312), and to a reference bit line formed by bit line segments 1315 and 1317 (and

which are switchably coupled to one another by transistor 1316). One advantage of this configuration, at least from a switched bit line perspective, is that a single control gate 1313 may be activated and deactivated to electrically couple and decouple the bit line segments (1311 and 1314) and reference bit line segments (1315 and 1317). [00061] Figure 14A shows an alternating, segmented bit line configuration for an open bit line embodiment. As shown, bit lines (, formed by switchably coupled bit line segments), are alternately coupled to sense amplifiers on opposite sides of the array, thus enabling the sense amplifier layout to be relaxed. For example, bit line segments 1413 and 1415 (switchably coupled to one another via transistor 1414) are coupled to left-side sense amplifier 1401 , while bit line segments 1416 and 1418 (switchably coupled to one another via transistor 1417) are coupled to right-side sense amplifier 1402. Note that the left and right sides of the array are arbitrary designations of opposite sides of the array. As described in reference to Figure 7B, which discusses the alternating bit line configuration, separate control lines 1419 and 1420 are provided for establishing segment interconnections to the oppositely disposed sense amplifiers. In one embodiment, the control lines are laid out in close proximity to one another with storage cells disposed in part to the right of the control lines and in part to the left of the control lines. Alternatively, storage cells may additionally be disposed between the control lines. In the first instance (no cells between the control lines), one of the control lines is activated and the other deactivated in any memory access, with the activated control line determined according to the row of storage cells to be accessed. For example, if storage cells to the left of the control lines are to be accessed, control line 1420 is activated (thereby electrically coupling segment 1418 to right-side sense amplifier 1402) and control line 1419 is deactivated (as segment 1415 need not be coupled to sense amplifier 1401 ). Conversely, if storage cells to the right of the control lines are to be accessed, control line 1419 is activated (thereby electrically coupling segment 1415 to left-side sense amplifier 1401 ) and control line 1420 is deactivated (as segment 1418 need not be coupled to sense amplifier 1402). In an embodiment in which storage cells are disposed between the control lines, both control lines 1419 and 1420 may be activated to access such centrally disposed cells. [00062] Note that the foregoing operational description relates to an embodiment in which both the left-side and right-side sense amplifiers are enabled to access the array concurrently (i.e., as a unit). In an alternative embodiment (or alternative

operating mode, such as a reduced-power mode), the left-side and right-side sense amplifiers may be independently operated, in effect logically splitting the storage array into two different, physically interleaved, storage arrays, one coupled to the left-side sense amplifiers and the other coupled to the right-side sense amplifiers. In such an embodiment (or operating mode), both control lines may be deactivated in an access limited to the bit line segments coupled to the sense amplifiers for the logical array.

[00063] Figure 14B shows another embodiment which combines the alternating bit line embodiment of Figure 14A and the folded bit line embodiment of Figure 13B (note that reference bit lines, though present, are not shown in Figure 14A). More specifically, a separate pair of control lines is provided for the sense amplifiers on each side of the array. For example, control lines 1457 and 1459 are operated concurrently to provide segmentation control for the segmented bit line and segmented reference bit line coupled to sense amplifier 1451 (i.e., control line 1457 coupling or decoupling segments 1452 and 1464 via transistor 1456, and control line 1459 coupling or decoupling segments 1453 and 1465 via transistor 1458). Similarly, control lines 1461 and 1463 are operated concurrently to provide segmentation control for the segmented bit line and segmented reference bit line coupled to sense amplifier 1468 (i.e., control line 1461 coupling or decoupling segments 1454 and 1466 via transistor 1460, and control line 1463 coupling or decoupling segments 1455 and 1467 via transistor 1462). In this arrangement, in a memory access directed to storage cells disposed to the right of the segment- coupling transistors (1456, 1458, 1460, and 1462), control lines 1457 and 1459 are activated and control lines 1461 and 1463 are deactivated. Conversely, in a memory access directed to storage cells disposed to the left of the segment-coupling transistors, control lines 1457 and 1459 are deactivated and control lines 1461 and 1463 are activated. As in the embodiment of Figure 14A, cells may be disposed between the pairs of control lines, in which case, all the control lines may be activated concurrently to enable access to these cells. Also, as discussed above, the left side and right side sense amplifiers may be operated independently, in which case, the pairs of control lines 1457/1459 and 1461/1463 may also be operated independently.

[00064] Referring to an alternative segment control architecture shown at 1470, the number of control lines may be reduced by positioning transistors 1456 and 1458

in line such that they may be switchably controlled by a shared control line 1471 and similarly positioning transistors 1460 and 1462 in line such that they may be switchably controlled by a shared control line 1472.

[00065] It should be noted that in the foregoing embodiments, bit line segments may be twisted at one or more points along their lengths (i.e., two bit lines crossing each other, for example, by one bit line transitioning to a different conductive layer, crossing the other, and then returning to the original conductive layer). In one embodiment, shown for example in Figure 15, the transistor switching element provided for segmentation control additionally serves to effect the bit line crossing. More specifically, two bit line segments 1501 and 1503 are switchably coupled by transistor 1505 which is oriented to offset the two bit line segments such that the composite bit line (formed by segments 1501 and 1503) crosses bit line 1510. Control line 1507 is disposed over the crossing (i.e., offset-producing) transistor 1505 to provide segmentation control (i.e., enable transistor 1505 to be switched between conducting and non-conducting states). Note that while shown in an angled position relative to the bit line segments, the crossing transistor may have other orientations in alternative embodiments (e.g., extending, source to drain, in the direction along the control line). Figure 16 illustrates an embodiment of a non- alternating folded bit-line array that employs the transistor-effected bit line crossing of Figure 15. As shown, crossing transistor 1655 is provided to switchably couple bit line segments 1652 and 1657 while an in-line transistor 1653 is provided to switchably couple bit line segments 1651 and 1658. The transistor-effected bit line crossing is not limited to the non-alternating or folded-bit line architecture and may be employed in other array architectures, including those described herein. [00066] Figure 17 shows a system having a memory with memory array segmentation. The system can be a personal computer, server, network device, consumer electronic device, or any mobile device (e.g., laptop, handheld computing device, cell phone, camera, camcorder, personal digital assistant, media recorders/players, etc.). The system includes a central processing unit (CPU) 1701. The CPU 1701 can be comprised of one or more microprocessors, digital signal processors, or application specific integrated circuits. In one embodiment, the processor is specifically designed for the mobile or handheld market. Video or graphics data are output to a display 1702. Audio is output to one or more speakers 1703. A microphone 1704 can be coupled to the CPU. Other devices such as a

mouse, trackball, cursor pointing mechanism can be coupled to the system through an input/output (I/O) interface 1705. I/O interface 1705 can also provide wireless as well as networking capabilities. A non-volatile memory 1706 is coupled to CPU 1701. Non-volatile memory 1706 can be a hard disk drive, flash memory, or read- only memory. A memory controller 1707 coupled to CPU 1701 controls self-refresh, refresh, and Read/Write operations to DRAM memory devices 1708-1710. Memory controller 1707 can have logic for partial array self refresh 1711 as well as standby mode 1712. During standby mode, self-refresh is being performed. The memory devices 1708-1710 can be volatile or non-volatile. They can be DRAM, flash, ROM, SRAM, phase-change memory, etc. The memory devices 1708-1710 have memory arrays that are segmented by segment switches arranged in one or more rows, columns, or diagonals. The segment switches are used to reduce the length of bit lines, word lines, or any other type of conducting lines used to access the individual memory locations of the memory array. Reducing the length of these lines reduces their inherent capacitance and resistance. This translates into power saving and improved memory latencies to these portions.

[0010] In conclusion, an apparatus and method for reducing power in a memory device are disclosed. In the foregoing specification, embodiments of the claimed subject matter have been described with reference to numerous specific details that can vary from implementation to implementation. For example, embodiments of the claimed subject matter include applications such as flash memory, phase-change memory, stacked memory, gain memory, single-electron memory, molecular memory, etc. Furthermore, embodiments of the claimed subject matter can include segmenting word lines. Thus, the sole and exclusive indicator of what is, and is intended by the applicants to be the claimed subject matter is the set of claims that issue from this application, in the specific form in which such claims issue, including any subsequent correction. Hence, no limitation, element, property, feature, advantage or attribute that is not expressly recited in a claim should limit the scope of such claim in any way. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.