APPARATUS AND METHODS FOR RESISTIVE SWITCHING

RELATED APPLICATIONS

This application claims priority under 35 U.S.C. § 119(e) to U.S. Provisional

Application No. 62/741,957, filed October 5, 2018, and entitled“Apparatus and Methods for Resistive Switching,” which is incorporated herein by reference in its entirety for all purposes.

BACKGROUND

A lion’s share of current state-of-the-art nonvolatile memory is silicon-based flash memory due to its high density and low cost. However, flash memories have several disadvantages, such as low operation speed (e.g., write/erase times of about 1 ms/0.1 ms), poor endurance (e.g., about 10 ⁶ write/erase cycles), and high write voltage (e.g., greater than 10 V). Moreover, flash memories may reach the miniaturization limit in the near future due to large leakage currents.

One technology that may overcome the disadvantages of flash memories is resistive random access memory (RRAM). In general, a RRAM cell includes an insulator or semiconductor sandwiched between two conductors. The underlying physical mechanism of RRAM is usually resistive switching (RS), which allows the cell to be freely programmed into a high resistance state (HRS, or OFF state) or a low resistance state (LRS, or ON state) under external electrical stimuli. In most cases, current flows uniformly through the device in the HRS and is restricted to a local region with high conductance known as a conducting filament (CF) in the LRS. The simple structure of RRAM enables easy integration in passive crossbar arrays with a small size of 4F ² (F is the minimum feature size). The size can be further reduced to 4F ² /n within vertically stacked three-dimensional (3-D) architectures (n is the stacking layer number of the crossbar array).

However, RRAMs have their own limitations. For example, current RRAMs typically use amorphous materials as the switching medium disposed between electrodes. During switching events, conductive filaments can be formed anywhere within the amorphous material. As a result, it can be difficult to accurately locate or confine the conductive filament. In addition, the random formation of conductive filaments in RRAMs can also reduce the uniformity (and increase the variance) of performance among different cells. The increased individual variability of RRAM cells can in turn limit wide spread applications. SUMMARY

Embodiments of the present invention include apparatus, systems, and methods for resistive switching. In one example, an apparatus for electrical switching includes a crystalline layer having a first side and a second side opposite the first side. In this example, the crystalline layer has at least one channel extending from the first side to the second side.

In this example, the apparatus also includes a first electrode disposed on the first side of the crystalline layer and a second electrode disposed on the second side of the crystalline layer.

In this example, the first electrode includes an alloy material to provide at least one metal ion migrating along the at least one channel in response to a first voltage applied across the first electrode and the second electrode, and the alloy material includes a high- wetting material and a low-wetting material.

It should be appreciated that all combinations of the foregoing concepts and additional concepts discussed in greater detail below (provided such concepts are not mutually inconsistent) are contemplated as being part of the inventive subject matter disclosed herein. In particular, all combinations of claimed subject matter appearing at the end of this disclosure are contemplated as being part of the inventive subject matter disclosed herein. It should also be appreciated that terminology explicitly employed herein that also may appear in any disclosure incorporated by reference should be accorded a meaning most consistent with the particular concepts disclosed herein.

BRIEF DESCRIPTION OF THE DRAWINGS

The skilled artisan will understand that the drawings primarily are for illustrative purposes and are not intended to limit the scope of the inventive subject matter described herein. The drawings are not necessarily to scale; in some instances, various aspects of the inventive subject matter disclosed herein may be shown exaggerated or enlarged in the drawings to facilitate an understanding of different features. In the drawings, like reference characters generally refer to like features (e.g., functionally similar and/or structurally similar elements).

FIGS. 1A-1C illustrate resistive switching using a line defect to guide formation of conductive filaments, in accordance with certain embodiments.

FIG. 2 shows a schematic of an electrical switch apparatus including a resistive layer to control the conductivity of the switching medium, in accordance with some embodiments.

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7617654.1 FIG. 3 shows a schematic of an electrical switch apparatus including a blocking layer to decrease bulk leakage current, in accordance with certain embodiments.

FIGS. 4A-4E illustrate a method of fabricating an electrical switch apparatus including a line defect, in accordance with some embodiments.

FIGS. 5A-5G illustrate a method of fabricating an array of electrical switch apparatus including line defects, in accordance with certain embodiments.

FIGS. 6A-6G illustrate a method of fabricating an array of electrical switch apparatus with an individual active electrode for each electrical switch apparatus in the array, in accordance with some embodiments.

FIGS. 7A-7G illustrate a method of fabricating an array of electrical switch apparatus with compact individual active electrodes, in accordance with certain embodiments.

FIGS. 8 A and 8B illustrate a method of fabricating a switching medium via metal assisted etching, in accordance with some embodiments.

FIG. 9 illustrates a method of fabricating a switching medium via electrochemical etching, in accordance with certain embodiments.

FIGS. 10A-10F illustrate a method of fabricating a switching medium using an assistive crystalline metal layer, in accordance with some embodiments.

FIGS. 11A-11D illustrate a method of fabricating a switching medium with active materials surrounding the crystalline layers, in accordance with certain embodiments.

FIGS. 12A and 12B show measured current-voltage curves of switching devices including active electrodes made of a low-wetting material (Ag) and an alloy comprising a low-wetting material and a high- wetting material (AgCu), respectively, in accordance with some embodiments.

FIGS. 13A-13E show measured current- voltage curves of switching devices using different active materials, in accordance with certain embodiments.

FIGS. 14A and 14B show retention properties of memory devices using silver and alloy, respectively, as the active material, in accordance with some embodiments.

FIG. 15 shows conductance of a switching device using an alloy active electrode after multiple cycles of operations, in accordance with certain embodiments.

DETAILED DESCRIPTION

Electrical Switching with Confined Conductive Filaments

To address issues arising out of the random formation of conductive filaments in RRAMs, apparatus, systems, and methods described herein employ otherwise undesirable

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7617654.1 line defects (also referred to as dislocations) in crystalline materials to form conductive filaments. Based on this approach, in accordance with certain embodiments, a switching cell (also referred to as a switching element, switching device, or switch) includes a crystalline layer disposed between an active electrode and another electrode. The crystalline layer has, in some embodiments, at least one line defect extending from one surface of the crystalline layer to the other surface. In accordance with certain embodiments, applying a voltage across the two electrodes causes metal ions to migrate from the active electrode to the other electrode along the line defect, thereby forming a conductive filament within the line defect. The active electrode includes, in some embodiments, an alloy material that further includes a high- wetting material and a low-wetting material. The high-wetting material (also referred to as low-wetting-angle material) can form a stable conductive filament region at the line defect in the medium, whereas the low-wetting material (also referred to as high-wetting-angle material) can dominantly change a dimension (e.g., length) of the conductive filament, thereby resulting in resistive switching.

As would be understood by those of ordinary skill in the art, a high-wetting material is one that forms a contact angle (as measured through the bulk of the high-wetting material) of less than 90 degrees (and, in some embodiments, less than 80 degrees, less than 70 degrees, less than 60 degrees, less than 45 degrees, less than 30 degrees, or less than 15 degrees) with the solid surface with which it is in contact. Also, a low-wetting material would form a contact angle (as measured through the bulk of the low-wetting material) of greater than 90 degrees (and, in some embodiments, greater than 100 degrees, greater than 110 degrees, greater than 120 degrees, greater than 135 degrees, greater than 150 degrees, or greater than 165 degrees) with the solid surface with which it is in contact.

The growth of the conductive filament modulates the overall resistance of the switching cell, thereby controlling the switching status of the switching cell, in accordance with certain embodiments. In general, the formation of the conductive filament puts the switching cell in an ON state. Upon application of another voltage of a different sign, in accordance with certain embodiments, the ions migrate back to the active electrode, thereby putting the switching cell into an OFF state. Using dislocations as the channel for conductive filaments can precisely control the location and size of the conducting filament. The well- defined conductive filament can in turn improve the device-to-device uniformity. In addition, the uniformity of performance of each device can also be improved.

FIGS. 1A and 1B show schematics of an apparatus 100 for resistive switching in an ON and OFF state, respectively. In the example embodiment illustrated in FIGS. 1A-1B,

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7617654.1 apparatus 100 includes a crystalline layer 110 (also referred to as switching medium) having a first side 111 (also referred to as a first surface 111) and a second side 113 (also referred to as a second surface 113). An active electrode 120 is disposed on first side 111 of crystalline layer 110 and a base electrode 130 is disposed on second side 113 of crystalline layer 110. The solid solubility of active electrode 120 in crystalline layer 110 can be less than 1% to reduce compound formation between active electrode 120 and crystalline layer 110.

Similarly, the solid solubility of base electrode 130 in crystalline layer 110 can also be less than 1%. Crystalline layer 110 has a channel 115, such as a line defect 115, extending substantially through the thickness of crystalline layer 110 (see FIG. 1B).

Active electrode 120 is made of an active material, which can be defined as any material that can provide ions in response to an applied voltage. In other words, applying a voltage across the two electrodes 120 and 130 causes ions to migrate from the active electrode 120 along the line defect 115 and form a conductive filament 118 in the line defect 115. (See, e.g., FIG. 1A). The formation of the conductive filament can decrease the resistivity of the crystalline layer 110, thereby causing apparatus 100 to be in the ON state (i.e., turning on the switch), as illustrated in FIG. 1A.

Upon removal of the voltage applied between the two electrodes 120 and 130, the conductive filament usually remains within line defect 115. Therefore, memory made of switch apparatus 100 can be nonvolatile. This is because upon removing the power supply of the memory, the stored information (e.g., 0 or 1) in the form of switching state of each switch cell (e.g., ON or OFF) remains in the memory. In other words, the memory does not erase data stored in the memory upon a power outage.

In accordance with certain embodiments, apparatus 100 can be switched off by applying another voltage having an opposite polarity (also referred to as an opposite sign). In some such embodiments, in response to the voltage of an opposite polarity, the metal ions that form the conductive filament retreat back to active electrode 120, thereby leaving a substantially empty line defect 115, as shown in FIG. 1B. This dissolution of the conductive filament increases the resistivity of crystalline layer 110, thereby causing apparatus 100 to be in the OFF state.

Various materials can be used to form crystalline layer 110. In one example, crystalline layer 110 includes an insulator. In another example, crystalline layer 110 includes a group IV semiconductor, such as single-crystalline silicon and/or single-crystalline germanium, among others. In yet another example, crystalline layer 110 includes a group III- V semiconductor (including Ill-nitride semiconductor), such as boron nitride (BN), gallium

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7617654.1 nitride (GaN), gallium arsenide (GaAs), indium nitride (InN), indium phosphide (InP), and/or indium arsenide (InAs), among others. In yet another example, crystalline layer 110 includes a group II- VI semiconductor, such as cadmium selenide (CdSe), zinc oxide (ZnO), zinc selenide (ZnS), or zinc sulfide, among others. Crystalline layer 110 can be single crystalline or polycrystalline, although the use of single crystalline materials in crystalline layer 110 can be advantageous in certain instances.

The thickness of crystalline layer 110 can be about 2 nm to about 1 /mi (e.g., about 2 nm, about 5 nm, about 10 nm, about 20 nm, about 50 nm, about 100 nm, about 200 nm, about 500 nm, or about 1 /mi, including any values and sub ranges in between). The thickness of crystalline layer 110 can also be less than 2 nm or greater than 1 /mi, depending on the desired performance of the resulting switch. For example, decreasing the thickness of crystalline layer 110 can decrease the distance for metal ions to migrate from active electrode 120 to reach base electrode 130, thereby increasing the switching speed. On the other hand, increasing the thickness of crystalline layer 110 can decrease the probability of conductive filament formation at a location outside line defect 115 due to, for example, discharge. This can in turn improve the stability of the resulting switch.

In one example, line defect 115 is all the way through crystalline layer 110. In other words, in such cases, line defect 115 extends from first side 111 of crystalline layer 110 to second side 113 of crystalline layer 110 (e.g., the length of line defect 115 is substantially the same as the thickness of crystalline layer 110). In another example, line defect 115 extends substantially through crystalline layer 110. Stated differently, the length of line defect 115 can be less than the thickness of crystalline layer 110. The ratio of the length of line defect 115 to the thickness of crystalline layer 110 can be about 50% to about 99% (e.g., about 50%, about 60%, about 70%, about 80%, about 90%, about 95%, about 97%, or about 99%, including any values and sub ranges in between).

The lateral dimension of line defect 115 (also referred to as the lateral size, such as diameter or width) can be about 0.1 nm to about 30 nm (e.g., about 0.1 nm, about 0.2 nm, about 0.5 nm, about 1 nm, about 2 nm, about 3 nm, about 4 nm, about 5 nm, about 10 nm, about 20 nm, or about 30 nm, including any values and sub ranges in between). The cross section of line defect 115 can be, for example, round, square, polygonal, or any other appropriate shape.

Apparatus 100 shown in FIGS. 1A-1C includes only one line defect 115. In practice, apparatus 100 can include multiple line defects 115. Memory made of apparatus 100 usually includes an array of the apparatus 100. Each apparatus 100 includes at least one line defect

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7617654.1 and the collection of the line defects in the memory can also form an array. In either case, the density of the line defects can be about 10 ² line defects per pm ² to about 10 ⁶ line defects per pm ² (e.g., 10 ² pm ² , 10 ³ pm ² , 10 ⁴ pm ² , 10 ⁵ pm ² , or about 10 ⁶ pm ² , including any values and sub ranges in between).

In general, it can be beneficial for the solid solubility of active electrode 120 in the crystalline layer 110 to be less than 1% (atomic percentage) so as to reduce the probability for active electrode 120 to form a compound with crystalline layer 110. In one example, the solid solubility of active electrode 120 in crystalline layer 110 can be less than 1% at room temperature. In another example, the solid solubility of active electrode 120 in crystalline layer 110 can be less than 1% at high temperature (e.g., at about 400 K, about 500 K, about 750 K, about 1000 K, or above). In yet another example, the solid solubility of active electrode 120 in crystalline layer 110 can be less than 0.1% (e.g., less than 0.1%, less than 0.05%, less than 0.02%, or less than 0.01%, including any values and sub ranges in between) at room temperature. In yet another example, the solid solubility of active electrode 120 in crystalline layer 110 can be less than 0.1% at high temperature (e.g., at about 400 K, about 500 K, about 750 K, about 1000 K, or above).

As described above, the active material in active electrode 120 can include an alloy that further includes a high- wetting material and a low-wetting material. In one example, the low-wetting material can include silver (Ag) and/or zinc (Zn) and the high- wetting material can include copper (Cu) and/or nickel (Ni). In some embodiments, the amount of the high- wetting material in the alloy can be about 10% to about 40% (e.g., about 10%, about 20%, about 30%, or about 40%, including any values and sub ranges in between).

The thickness of active electrode 120 can be about 5 nm to about 10 /mi (e.g., about 5 nm, about 10 nm, about 20 nm, about 50 nm, about 100 nm, about 200 nm, about 500 nm, about 1 //m, about 2 //m, about 3 //m, about 4 //m, or about 5 //m, including any values and sub ranges in between).

In one example, base electrode 130 in apparatus 100 can be a passive electrode, in which case base electrode 130 does not provide conductive ions (or other charged particles) to form filaments in crystalline layer 110. In another example, base electrode 130 can also be an active electrode. The material of base electrode 130 can be selected from a wide range of materials. In one example, base electrode 130 includes metal materials, such as gold, platinum, copper, tantalum, tin, tungsten, titanium, tungsten, cobalt, chromium, silver, nickel, aluminum, or any mixture including one or more of these (e.g., a binary or ternary system of any of these conductive materials). In another example, the base electrode includes a

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7617654.1 conductive metal oxide, such as TiN, TiB ₂ , MoSi ₂ , n-BaTi0 ₃ , (Fe, Ti) ₂ 0 ₃ , Re0 ₃ , Ru0 ₂ , and/or Ir0 ₂ , among others. In yet another example, base electrode 130 can include carbon- based conductive materials, such as graphene.

The solid solubility of base electrode 130 in crystalline layer 110 can be less than 1% (e.g., less than 1%, less than 0.5%, less than 0.2%, less than 0.1%, less than 0.05%, or less than 0.01%, including any values and sub ranges in between). This low solubility can be at room temperature or at high temperature (e.g., at about 400 K, about 500 K, about 750 K, about 1000 K, or above).

In one example, the solid solubility of active electrode 120 in crystalline layer 110 (referred to as the first solid solubility) can be the same as the solid solubility of base electrode 130 in crystalline layer 110 (referred to as the second solid solubility). In another example, the first solid solubility can be different than the second solubility.

The thickness of base electrode 130 can be about 5 nm to about 10 /mi (e.g., about 5 nm, about 10 nm, about 20 nm, about 50 nm, about 100 nm, about 200 nm, about 500 nm, about 1 mpn, about 2 mpn, about 3 mpn, about 4 mpn, or about 5 mpn, including any values and sub ranges in between). In one example, the two electrodes 120 and 130 can have the same thickness. In another example, the two electrodes 120 and 130 can have different thicknesses.

FIG. 1C shows a schematic of the apparatus 100 to illustrate an advantage of using an alloy material for the active electrode 120. Without wishing to be bound by any particular theory or mode of operation, it is believed that when a conducting channel is solely formed by highly mobile and high-wetting-angle materials (which can lead to weak bonding with a line defect), disconnection of the conduction channel can easily occur, thereby resulting in poor retention properties. Furthermore, it is believed that the switching location in the conduction channel is dynamically changed, inducing non-uniform switching properties.

In contrast, it is believed that the use of an alloy comprising highly mobile material and low-wetting-angle material (which can lead to strong bonding with a line defect), can drive outstanding retention properties as the conduction channel sticks to the line defect. Furthermore, it is believed that the switching uniformity can be enhanced because the switching region is hardly changed. As illustrated in FIG. 1C, the high-wetting material forms a wall structure 122 that is substantially in conformal contact with the inner wall of channel 115. This wall structure 122 can define a channel to guide ions 124 provided by the low-wetting material.

Electrical Switching with Resistive Layer

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7617654.1 FIG. 2 shows a schematic of an apparatus 200 including a resistive layer 240 to control the resistivity of apparatus 200. In accordance with certain embodiments, apparatus 200 includes a crystalline layer 210 disposed between an active electrode 220 and resistive layer 240. A base electrode 230 is disposed on resistive layer 240. Crystalline layer 210 has a line defect 215 extending substantially through the thickness of crystalline layer 210. In contrast, resistive layer 240 does not have a line defect. As a result, a conductive filament 218 formed within line defect 215 stops at or before resistive layer 240. Apparatus 200 has a higher resistivity in its ON state than apparatus 100 in FIGS. 1A-1C.

Resistive layer 240 can be made of an intrinsic semiconductor (e.g., intrinsic silicon) and base electrode 230 can be made of a doped semiconductor (e.g., p ⁺ silicon). In this configuration, resistive layer 240 reduces the bulk leakage current of apparatus 200 by reducing discharge between the two electrodes 220 and 230.

The thickness of resistive layer 240 can be about 1 nm to about 5 nm (e.g., about 1 nm, about 2 nm, about 3 nm, about 4 nm, or about 5 nm, including any values and sub ranges in between).

Electrical Switching with Blocking Layer

FIG. 3 shows a schematic of an apparatus 300 including a blocking layer 350 to reduce bulk leakage current of apparatus 300. In accordance with certain embodiments, apparatus 300 includes a crystalline layer 310 disposed between blocking layer 350 and base electrode 330. An active electrode 320 is disposed on blocking layer 350. Crystalline layer 310 has a line defect 315 extending substantially through the thickness of crystalline layer 310. Blocking layer 350 also has an opening 355 (which can also be a line defect) aligned with line defect 315 such that a continuous conductive filament 318 can be formed between the two electrodes 320 and 330. Blocking layer 350 can reduce the possibility of discharge between the two electrodes 320 and 330 at locations outside line defect 315, thereby reducing bulk leakage current of apparatus 300.

In one example, blocking layer 350 and crystalline layer 310 can form a p-n junction. For example, blocking layer 350 can be doped with a p-type dopant and crystalline layer 310 can be doped with an n-type dopant. In another example, blocking layer 350 can be doped with an n-type dopant and crystalline layer 310 can be doped with a p-type dopant. The p-n junction can further reduce bulk leakage current of apparatus 300.

The thickness of blocking layer 350 can be about 1 nm to about 5 nm (e.g., about 1 nm, about 2 nm, about 3 nm, about 4 nm, or about 5 nm, including any values and sub ranges in between).

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7617654.1 In one example, apparatus 300 can include just one blocking layer 350. In another example, apparatus 300 can include multiple blocking layers 350. For example, apparatus 300 may include two blocking layers 350, including a doped blocking layer and an intrinsic blocking layer, such that they can form a PIN junction with crystalline layer 310. In yet another example, crystalline layer 310 can be sandwiched between two blocking layers 350 (one on the top and the other on the bottom of crystalline layer 310).

Apparatus 300 can also include a resistive layer (not shown in FIG. 3) that is the same as or substantially identical to resistive layer 240 shown in FIG. 2 and described above.

Electrical Switching with Other Types of Channels

In apparatus 100, 200, and 300 shown in FIGS. 1-3, respectively, and described above, confinement of the conductive filaments is achieved by ion migration along line defects (i.e., 115, 215, and 315) in crystalline layers. Alternatively, precise confinement of conductive filaments can also be achieved using other channels in the switching medium.

In one example, the crystalline layers (i.e., 110, 210, and 310 shown in FIGS. 1-3) can be replaced by a porous silicon layer. Pores in the porous silicon layer can be used as channels for metal ions from the active electrodes (i.e., 120, 220, and 320) to form one or more conductive filaments.

In another example, gold nanoparticle catalytic etching can be used to create channels in materials such as silicon (described below). The created channels can then provide the path for ions from the active electrodes (i.e., 120, 220, and 320) to form conductive filaments.

In yet another example, the crystalline layers (i.e. 110, 210, and 310 shown in FIGS. 1-3) can be replaced by a layer made of anodized aluminum. As understood in the art, anodized aluminum can be porous, thereby providing ion migration channels to form conductive filaments.

Methods of Fabricating Switching Devices Based on Line Defects

FIGS. 4A-4E illustrate a method 400 of fabricating switching devices using line defects for generating conductive filaments. As shown in FIG. 4A, in accordance with certain embodiments, method 400 includes preparing a substrate 410, which can be made of a conductive material that can be used in base electrode 130 as described above (e.g., metal, conductive metal oxide, carbon-based material, etc.). Substrate 410 can be an epitaxial layer with a lattice structure.

FIG. 4B shows, in accordance with some embodiments, that a crystalline layer 420 (also referred to as the switching medium) is epitaxially grown on substrate 410. Crystalline layer 420 also has a lattice structure, which is different from the lattice structure of substrate

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7617654.1 410, thereby creating one or more line defects 425 in crystalline layer 420. The density of line defects 425 can be adjusted by changing the lattice mismatch between crystalline layer 420 and substrate 410. In general, a larger lattice mismatch can result in a higher density of line defects 425.

An optional step of dislocation opening can also be performed via a selective etching technique, such as Schimmel etching or Secco etching. In Si and Ge, Schimmel etching and Secco etching can preferentially etch the line defects over the bulk material. The selective etching can ensure that line defects 425 have openings at the top surface of crystalline layer 420 so as to facilitate formation of conductive filaments by receiving metal ions from active electrodes disposed above (see, e.g., FIG. 4E and description below). Selective etching can also control the lateral dimension of line defects 425 (e.g., enlarging the opening of line defects 425). In general, increasing the etching time increases the lateral dimension of line defects 425.

Another optional step of forming a resistive layer (not shown in FIG. 4B) can also be performed before crystalline layer 420 is grown. The resistive layer can be the same as or substantially identical to resistive layer 240 shown in FIG. 2 and described above.

FIG. 4C shows, in accordance with certain embodiments, that an insulating layer 430 is disposed on crystalline layer 420. In one example, insulating layer 430 can be disposed via chemical deposition. In another example, insulating layer 430 can be disposed via physical deposition. In yet another example, insulating layer 430 can be disposed on switching medium 420 via epitaxial growth. In yet another example, insulating layer 430 can be disposed via electrodeposition. In yet another example, insulating layer 430 can be disposed via thermal oxidation.

Insulating layer 430 can include various types of materials, such as dielectric material, poly-crystalline materials, and polymers. For example, insulating layer 430 can include Si0 ₂ . In another example, insulating layer 430 can include AI2O3. In yet another example, insulating layer 430 can include Hf0 ₂ . In yet another example, insulating layer 430 can include poly-silicon. In yet another example, insulating layer 430 can include porcelain. In yet another example, insulating layer 430 can include ethylene-propylene rubbers (EPM). In yet another example, insulating layer 430 can include ethylene-propylene-diene rubber (EPDM).

In FIG. 4D, in accordance with some embodiments, an opening 435 (also referred to as a cavity 435) is created in insulating layer 430. In one example, opening 435 can be created via wet etching. In another example, opening 435 can be created via dry etching.

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7617654.1 Opening 435 exposes at least one line defect 425 for further processing, such as forming an active electrode.

In FIG. 4E, in accordance with certain embodiments, an active material is deposited into opening 425 to form an active electrode 440. The active material can include, for example, silver (Ag), aluminum (Al), gold (Au), indium (In), Tin (Sn), zinc (Zn), or any other active material known in the art. In some embodiments, openings 425 can have a larger dimension at the entrance as illustrated in FIG. 4E. This configuration can be achieved via selective etching that is employed to create openings 425. The larger entrance of openings 425 can facilitate the depositions of active electrode 440 and formation of filaments.

An optional step of forming a blocking layer can be performed before active electrode 440 is formed. The blocking layer can be deposited on crystalline layer 420. The active material is then deposited on the blocking layer. The blocking layer can be the same as or substantially identical to blocking layer 350 shown in FIG. 3 and described above.

Methods of Fabricating an Array of Switching Devices

FIGS. 5A-5G illustrate a method 500 of fabricating an array of switching devices so as to, for example, facilitate mass production of the switching devices. As shown in FIG. 5A, in accordance with certain embodiments, a substrate 510 is prepared. Substrate 510 can include an intrinsic or non-conducting epitaxial material and function as a platform for subsequent steps of fabrications.

FIG. 5B shows, in accordance with some embodiments, that a conductive layer 520 is epitaxially grown on substrate 510. Conductive layer 520 (or at least a portion of conductive layer 520) can function as the base electrode (e.g., base electrode 130) in the resulting electrical switch.

FIG. 5C shows, in accordance with certain embodiments, that a crystalline layer 530 (which can function as a switching medium) is epitaxially grown on conductive layer 520. Crystalline layer 530 and conductive layer 520 have a lattice mismatch such that crystalline layer 530 has line defects 535. The amount of mismatch can be adjusted to change the density of line defects 535. In addition, etching steps can be carried out to create openings of line defects 535 and/or change the lateral size of line defects 535.

In FIG. 5D, and in accordance with some embodiments, the assembly of conductive layer 520 and crystalline layer 530 are etched into isolated islands (one island is shown in FIG. 5D), each of which can be fabricated into an individual switching cell. In this manner, method 500 can produce multiple switching devices simultaneously, thereby allowing mass

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7617654.1 production or at least batch fabrication. The etching step shown in FIG. 5D can be, for example, dry etching or wet etching as known in the art.

FIG. 5E shows, in accordance with certain embodiments, that an insulating layer 540 is disposed on and around the assembly of conductive layer 520 and crystalline layer 530. In other words, in FIG. 5E, insulating layer 540 surrounds conductive layer 520 and crystalline layer 530. Insulating layer 540 can be disposed via conformal coating or deposition techniques, such as atomic layer deposition (ALD), chemical vapor deposition, or any other conformal coating methods known in the art.

FIG. 5F shows, in accordance with some embodiments, that an opening 545 is created in insulating layer 540 to expose at least one line defect 535 for further processing. Opening 545 can be created via dry etching or wet etching. An active material is then, in some embodiments, disposed into opening 545 so as to form an active electrode 550, as shown in FIG. 5G. Optionally, a capping layer 560 can be disposed on active electrode 550. In practice, capping layer 560 can block undesired degradation of active materials such as oxidation and/or out-diffusion.

The active electrode 550 as shown in FIG. 5G, in accordance with certain

embodiments, not only fills opening 545 in insulating layer 540 but also covers a significant portion (or all) of insulating layer 540. In this case, the switching devices that are batch fabricated can share a common active electrode 550. Alternatively, active electrode 550 can be an individual active electrode 550 electrically connected only to crystalline layer 530 right below but not adjacent crystalline layers (see, e.g., FIG. 6G below).

FIGS. 6A-6G illustrate a method 600 of fabricating an array of switching devices in which each individual switch device in the array has an individual active electrode. The first steps of method 600 as illustrated in FIGS. 6A-6F can be the same as or substantially similar to the first steps of the method 500 illustrated in FIGS. 5A-5F. In method 600, a substrate 610 is prepared (FIG. 6A) and a conductive layer 620 is disposed on substrate 610 (FIG. 6B). A crystalline layer 630 is epitaxially grown on conductive layer 620 (FIG. 6C). The lattice mismatch between crystalline layer 630 and conductive layer 620 creates line defects 635 in crystalline layer 630, as well as controls the density of line defects 635. In FIG. 6D, in accordance with certain embodiments, conductive layer 620 and crystalline layer 630 are segmented into individual assemblies via dry etching or wet etching. Each individual assembly of the conductive layer 620 and the crystalline layer 630 is surrounded by an insulating layer 640 as shown in FIG. 6E, in accordance with certain embodiments. An

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7617654.1 opening 645 is created for each individual assembly of conductive layer 620 and crystalline layer 630, as shown in FIG. 6F, in accordance with some embodiments.

FIG. 6G shows, in accordance with certain embodiments, that an active material is disposed in opening 645 to form an active electrode 650. In contrast to active electrode 550 shown in FIG. 5G, active electrode 650 in FIG. 6G extends to only the proximity of opening 645. In this case, each crystalline layer 630 can have an individual active electrode 650, instead of sharing a common active electrode with other switching devices on the substrate 610. An optional capping layer 660 can also be disposed on active electrode 650 and insulating layer 640.

FIGS. 7A-7G illustrate a method 700 of fabricating an array of switching devices. In the method illustrated in FIGS. 7A-7G, each switching device in the array has an individual active electrode that covers only the switching medium. The first steps of method 700 as illustrated in FIGS. 7A-7F are substantially similar to the first steps of the method 500 illustrated in FIGS. 5A-5F. In method 700, a substrate 710 is prepared (FIG. 7A) and a conductive layer 720 is disposed on substrate 710 (FIG. 7B). A crystalline layer 730 is epitaxially grown on conductive layer 720 (FIG. 7C). The lattice mismatch between crystalline layer 730 and conductive layer 720 creates line defects 735 in crystalline layer 730, as well as controls the density of line defects 735. In FIG. 7D, in accordance with certain embodiments, the assembly of conductive layer 720 and crystalline layer 730 is segmented into individual assemblies via dry etching or wet etching. Each individual assembly of conductive layer 720 and crystalline layer 730 is surrounded by an insulating layer 740 as shown in FIG. 7E, in accordance with some embodiments.

FIG. 7F shows that, in accordance with some embodiments, an opening 745 is created for each individual assembly of conductive layer 720 and crystalline layer 730. An active material is disposed in the opening 745 to form an active electrode 750, which extends vertically from crystalline layer 730 and does not cover the top surface of insulating layer 740. Compared to active electrode 650 in FIG. 6G, active electrode 750 in FIG. 7G can be more compact and may reduce the cost of the resulting devices by reducing the amount of active material. In FIG. 7G, an optional capping layer 760 is disposed on active electrode 750 and insulating layer 740. Capping layer 760 can be conductive so as to electrically couple together the individual active electrodes 750 in different individual switching devices. Methods of Fabricating Switching Devices Based on Other Channels

As described above, other channels in materials can also be used to facilitate the formation and confinement of conductive filaments. FIGS. 8A-8B illustrate a method 800 of

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7617654.1 creating channels in a switching medium using metal assisted etching. In FIG. 8A, in accordance with certain embodiments, metal nanoparticles 820 are disposed on a substrate 810, which can be an epitaxial layer. In one example, metal nanoparticles 820 include gold nanoparticles. In another example, metal nanoparticles 820 include silver nanoparticles. In yet another example, metal nanoparticles 820 include copper nanoparticles. The size of metal nanoparticles 820 can be about 1 nm to about 5 nm (e.g., about 1 nm, about 2 nm, about 3 nm, about 4 nm, or about 5 nm, including any values and sub ranges in between).

Metal nanoparticles 820 can be disposed on substrate 810 via spin coating techniques. Optionally, metal nanoparticles 820 can be covered with thiol-terminated polystyrene (e.g., forming a polymer shell surrounding each metal nanoparticle). The polymer shell can facilitate the formation of highly ordered arrays of metal nanoparticles 820 via self-assembly.

FIG. 8B shows, in accordance with some embodiments, that an etching process is carried out to etch the portion of substrate 810 right underneath metal nanoparticles 820 so as to form a plurality of channels 815. These channels 815 allow the formation and confinement of conductive filaments. Accordingly, substrate 810 including channels 815 can be used as a switching medium. The etching can use a mixture of hydrogen fluoride (HF) and H ₂ 0 ₂ , as known in the art. An additional step can be performed to remove possible polymer shell surrounding nanoparticles 820. In one example, the polymer shell can be removed by plasma treatment. In another example, the polymer shell can be removed by flame annealing.

Method 800 can further include the optional step of removing metal nanoparticles 820 after the formation of channels 815. The removal can be achieved by, for example room temperature etching in an aqueous solution of iodine and potassium iodide.

FIG. 9 illustrates a system 900, in accordance with certain embodiments, for fabricating porous silicon, which can also be used as switching medium as described above. System 900 includes a container 930 to hold an electrolyte 920, such as HF-ethanol or HF- H ₂ 0 ₂ . A silicon sample 910 including an intrinsic silicon region 912 and a p ⁺ type silicon region 914 is at least partially immersed in electrolyte 920. Two electrodes 940a and 940b are placed on two sides of container 930 and are in direct contact with electrolyte 920. A current source 950 is electrically coupled to the two electrodes 940a and 940b so as to perform electrochemical anodization of the silicon sample. Upon application of a current flowing through the electrolyte, pores can be created in p ⁺ silicon region 914, which can then be used as the switching medium to create and confine conductive filaments in the pores. Methods of Fabricating Switching Devices Using Assistive Metal Layers

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7617654.1 FIGS. 10A-10F illustrate a method 1000 of fabricating switching devices using assistive metal layers. FIG. 10A shows, in accordance with certain embodiments, a conductive crystalline layer 1020 disposed on a substrate 1010 that can be insulating. FIG. 10B shows that conductive crystalline layer 1020 is patterned so as to, for example, define areas for subsequent growth of switching medium. FIG. 10C shows that a crystalline layer 1030 is conformally deposited on the etched conductive crystalline layer 1020. Crystalline layer 1030 includes at least one line defect 1035. In FIG. 10D, an insulating layer 1040 is disposed on crystalline layer 1030. Insulating layer 1040 can, for example, block direct electrical current from the top electrode to the bottom electrode. In FIG. 10E, an opening 1045 is created in insulating layer 1040 via wet etching or dry etching. Opening 1045 exposes at least one line defect 1035 so as to facilitate next steps. In FIG. 10F, an active material 1050 is filled in to opening 1045 as well as disposed above insulating layer 1040 so as to define a top electrode. An optional capping layer 1060 is then disposed on active material 1050.

FIGS. 11A-11D illustrate a method 1100 of fabricating switching devices with active materials surrounding the crystalline layer. FIG. 11A shows, in accordance with certain embodiments, a conductive crystalline layer 1120 disposed on a substrate 1110 that can be insulating. FIG. 11B shows that conductive crystalline layer 1120 is patterned so as to, for example, define areas for subsequent growth of switching medium. FIG. 11C shows that a crystalline layer 1130 is conformally deposited on the etched conductive crystalline layer 1120. Crystalline layer 1130 includes at least one line defect 1135. In FIG. 11D, an active material 1140 is directly disposed on crystalline layer 1130 and surrounds the entire crystalline layer 1130 to define a top electrode. An optional capping layer 1150 is then disposed on active material 1140.

Characterization of Resistive Switching Using an Alloy Active Material

FIGS. 12A and 12B show measured current-voltage curves of switching devices including active electrodes made of a low-wetting material (Ag) and an alloy including a low- wetting material and a high-wetting material (AgCu alloy), respectively. The devices used to generate the data in FIGS. 12A and 12B were fabricated using methods similar to those described above with respect to FIGS. 4A-4E. SiGe (10 at% Ge) was used as the switching medium and p-type Si was used as the counter electrode. The curves in FIG. 12A have high current variations in low current regime. In contrast, the variation in FIG. 12B is much smaller, thereby demonstrating the advantage of using the alloy material as the active electrode.

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7617654.1 FIGS. 13A-13E show measured current- voltage curves of switching devices using different active materials. The devices used to generate the data in FIGS. 13A-13E were fabricated using methods similar to those described above with respect to FIGS. 4A-4E.

SiGe (10 at% Ge) was used as the switching medium and p-type Si was used as the counter electrode. The device in FIG. 13 A uses pure silver (a low-wetting material) as the active material and the resulting switching behavior has a noticeable non-uniformity. The device in FIG. 13E uses pure copper (a high- wetting material) as the active material, and no switching was achieved. The devices in FIGS. 13B-13D use an alloy of silver and copper having different ratios. When the Ag/Cu ratio in the alloy was 8:2 and 7:3 (FIGS. 13B and 13C, respectively), resistive switching occurred with better uniformity than pure Ag. However, when the Ag/Cu ratio was 6:4 (FIG. 13D), the resulting device shows irreversible breakdown behavior without switching.

FIGS. 14A and 14B show retention properties of memory devices using silver and a silver-copper alloy (with an Au/Cu atomic ratio of 8:2), respectively, as the active material. The devices used to generate the data in FIGS. 14A and 14B were fabricated using similar methods described above with respect to FIGS. 4A-4E. SiGe (10 at% Ge) was used as the switching medium and p-type Si was used as the counter electrode. In FIG. 14A, the measured current curves have more significant fluctuation compared to the current curves shown in FIG. 14B. In addition, the current in FIG. 14A decreases more significantly as a function of time compared to the current in FIG. 14B. These two figures demonstrate that devices using an alloy active electrode can have improved retention.

FIG. 15 shows analog functionality of the switching device comprising the alloy active electrode that was used to generate the data in FIGS. 14A and 14B. To generate the data in FIG. 15, a pulse train was applied consisting of potentiation (5.2 V, 50 ps), depression (-3.6 V, 50 ps), and read (2.5 V, 0.5 ms) pulses. During 100 cycles of potentiation and 100 cycles of depression, the devices showed gradual and linear conductance changes with on/off ratio of 9, demonstrating superior analog switching performance and suitability for neuromorphic computing.

Conclusion

While various inventive embodiments have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and/or structures for performing the function and/or obtaining the results and/or one or more of the advantages described herein, and each of such variations and/or modifications is deemed to be within the scope of the inventive embodiments described herein. More generally, those

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7617654.1 skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and/or configurations will depend upon the specific application or applications for which the inventive teachings is/are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific inventive embodiments described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described and claimed. Inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and/or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and/or methods, if such features, systems, articles, materials, kits, and/or methods are not mutually inconsistent, is included within the inventive scope of the present disclosure.

The above-described embodiments can be implemented in any of numerous ways.

For example, embodiments of designing and making the technology disclosed herein may be implemented using hardware, software or a combination thereof. When implemented in software, the software code can be executed on any suitable processor or collection of processors, whether provided in a single computer or distributed among multiple computers.

Further, it should be appreciated that a computer may be embodied in any of a number of forms, such as a rack-mounted computer, a desktop computer, a laptop computer, or a tablet computer. Additionally, a computer may be embedded in a device not generally regarded as a computer but with suitable processing capabilities, including a Personal Digital Assistant (PDA), a smart phone or any other suitable portable or fixed electronic device.

Also, a computer may have one or more input and output devices. These devices can be used, among other things, to present a user interface. Examples of output devices that can be used to provide a user interface include printers or display screens for visual presentation of output and speakers or other sound generating devices for audible presentation of output. Examples of input devices that can be used for a user interface include keyboards, and pointing devices, such as mice, touch pads, and digitizing tablets. As another example, a computer may receive input information through speech recognition or in another audible format.

Such computers may be interconnected by one or more networks in any suitable form, including a local area network or a wide area network, such as an enterprise network, an

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7617654.1 intelligent network (IN) or the Internet. Such networks may be based on any suitable technology and may operate according to any suitable protocol and may include wireless networks, wired networks or fiber optic networks.

The various methods or processes outlined herein may be coded as software that is executable on one or more processors that employ any one of a variety of operating systems or platforms. Additionally, such software may be written using any of a number of suitable programming languages and/or programming or scripting tools, and also may be compiled as executable machine language code or intermediate code that is executed on a framework or virtual machine.

In this respect, various inventive concepts may be embodied as a computer readable storage medium (or multiple computer readable storage media) (e.g., a computer memory, one or more floppy discs, compact discs, optical discs, magnetic tapes, flash memories, circuit configurations in Field Programmable Gate Arrays or other semiconductor devices, or other non-transitory media or tangible computer storage media) encoded with one or more programs that, when executed on one or more computers or other processors, perform methods that implement the various embodiments of the invention discussed above. The computer readable medium or media can be transportable, such that the program or programs stored thereon can be loaded onto one or more different computers or other processors to implement various aspects of the present invention as discussed above.

The terms“program” or“software” are used herein in a generic sense to refer to any type of computer code or set of computer-executable instructions that can be employed to program a computer or other processor to implement various aspects of embodiments as discussed above. Additionally, it should be appreciated that according to one aspect, one or more computer programs that when executed perform methods of the present invention need not reside on a single computer or processor, but may be distributed in a modular fashion amongst a number of different computers or processors to implement various aspects of the present invention.

Computer-executable instructions may be in many forms, such as program modules, executed by one or more computers or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Typically the functionality of the program modules may be combined or distributed as desired in various embodiments.

Also, data structures may be stored in computer-readable media in any suitable form. For simplicity of illustration, data structures may be shown to have fields that are related

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7617654.1 through location in the data structure. Such relationships may likewise be achieved by assigning storage for the fields with locations in a computer-readable medium that convey relationships between the fields. However, any suitable mechanism may be used to establish a relationship between information in fields of a data structure, including through the use of pointers, tags or other mechanisms that establish relationships between data elements.

Also, various inventive concepts may be embodied as one or more methods, of which examples have been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

Unless specified to the contrary, all percentages and ratios described herein that are related to amounts or relative amounts of components are based on atomic percentages of those components.

All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and/or ordinary meanings of the defined terms.

The indefinite articles“a” and“an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean“at least one.”

The phrase“and/or,” as used herein in the specification and in the claims, should be understood to mean“either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with“and/or” should be construed in the same fashion, i.e.,“one or more” of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the“and/or” clause, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to“A and/or B”, when used in conjunction with open-ended language such as“comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.

As used herein in the specification and in the claims,“or” should be understood to have the same meaning as“and/or” as defined above. For example, when separating items in a list,“or” or“and/or” shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as“only one of’

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7617654.1 or“exactly one of,” or, when used in the claims,“consisting of,” will refer to the inclusion of exactly one element of a number or list of elements. In general, the term“or” as used herein shall only be interpreted as indicating exclusive alternatives (i.e.,“one or the other but not both”) when preceded by terms of exclusivity, such as“either,”“one of,”“only one of,” or “exactly one of.”“Consisting essentially of,” when used in the claims, shall have its ordinary meaning as used in the field of patent law.

As used herein in the specification and in the claims, the phrase“at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase“at least one” refers, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example,“at least one of A and B” (or, equivalently,“at least one of A or B,” or, equivalently“at least one of A and/or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another

embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one,

B (and optionally including other elements); etc.

In the claims, as well as in the specification above, all transitional phrases such as “comprising,”“including,”“carrying,”“having,� �“containing,”“involving,”“holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases“consisting of’ and“consisting essentially of’ shall be closed or semi-closed transitional phrases, respectively, as set forth in the United States Patent Office Manual of Patent Examining Procedures, Section 2111.03.

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7617654.1