BACKGROUND

[0001] Power consumption for high-speed input-output (I/O) transceivers is a critical metric especially in mobile applications such as notebooks, tablets, and smart phones. Low active power is desired during data transmission. Ability to transition quickly from standby/hibernate to active mode keeps the power usage minimal. In an embedded-clocking application, Clock Data Recovery (CDR) solutions are power hungry during active mode, and slow during power state transitions. Most conventional CDR techniques utilize feedback, that restrict their ability to quickly acquire lock during transition from hibernate/standby state to active state.

[0002] For example, traditional CDR circuits in I/O receivers employ feedback mechanisms that inhibit fast power transition. One known CDR technique that uses no feedback is Blind- Oversampling (BOS) CDR, but it suffers from high power consumption, large area and limited operational speed thereby impeding its adoption in high-speed links.

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific

embodiments, but are for explanation and understanding only.

[0004] Fig. 1Α illustrates a conventional Blind-Oversampling (BOS) Clock Data Recovery

(CDR) architecture.

[0005] Fig. IB illustrates waveforms to show the basic concept of BOS CDR.

[0006] Fig. 2Α illustrates BOS CDR architecture with Proportional Integral Derivative

(PID) Controller and weight adjustment, according to one embodiment of the disclosure.

[0007] Fig. 2B illustrates a waveform in a Unit Interval (UI) and the concept of phase prediction and weight adjustment using architecture of Fig. 2Α, according to one embodiment of the disclosure.

[0008] Fig. 3 illustrates BOS CDR architecture with Proportional (P) Controller and reconstruct unit, according to one embodiment of the disclosure.

[0009] Fig. 4 illustrates BOS CDR architecture with edge averaging, according to one embodiment of the disclosure.

[0010] Fig. 5 illustrates an Edge Generator for use in BOS CDR architecture, according to one embodiment of the disclosure. [0011] Fig. 6 illustrates an Edge Filter for use in BOS CDR architecture, according to one embodiment of the disclosure.

[0012] Fig. 7 illustrates an Edge Select Unit for use in BOS CDR architecture, according to one embodiment of the disclosure.

[0013] Fig. 8 illustrates a Data Select Unit for use in BOS CDR architecture, according to one embodiment of the disclosure.

[0014] Fig. 9 illustrates a Data Conditioner for use in BOS CDR architecture, according to one embodiment of the disclosure.

[0015] Fig. 10 illustrates a FIFO Synchronizer for use in BOS CDR architecture, according to one embodiment of the disclosure.

[0016] Fig. 11 illustrates an I/O system having a receiver which includes the BOS CDR architecture, according to one embodiment of the disclosure.

[0017] Fig. 12 is a smart device or a computer system or an SoC (System-on-Chip) with

BOS CDR architecture, according to one embodiment of the disclosure.

DETAILED DESCRIPTION

[0018] Fig. 1A illustrates a conventional Blind-Oversampling (BOS) Clock Data Recovery

(CDR) architecture 100. A BOS CDR receives input data "Data_in" and samples it by a blind sampler Nx Sampler 101 using receive (Rx) Clock. Nx Sampler 101 oversamples "Data_in" by 'N' times. Here, input data stream "Data_in" is oversampled by uniformly spaced clock signal phases to generate a series of zeros and ones as possible data samples. The output of Nx Sampler 101 is received by Synchronizer 102, which synchronizes all data samples to one clock phase.

[0019] The synchronized data from Synchronizer 102 is stored in large Data Storage 103 e.g., FIFOs (first-in-first-out). The synchronized data stored in the FIFOs is then received by Boundary Selection Unit 104 in which successive sampled data bits are XOR-ed to determine the edge transitions in Data_in. Output of Boundary Selection Unit 104 is then received by Data Select Unit 106 to select a data sample. The Delta Unit 105 compensates for any timing path- delay in the Boundary Selection Unit. The selected data sample is then stored in FIFO 107 for alignment and overflow/underflow correction. Output of FIFO 107 is then received by FIFO Synchronizer 108 which conditions the output data, "Data_out," to be received by other logic units for further processing.

[0020] Fig. IB illustrates waveforms 120 to show the basic concept of BOS CDR. Here, the top waveform is receiver input RX In (which is same as "Data_in"). The next waveform from the top is D _samp ied, which shows the values of the data samples by oversampling "Data_in." Boundary Selection Unit 104 then determines the Edges, which are shown below the D _samp i _e d. In order to avoid the effect of false transitions due to noise, these Edges are accumulated (i.e., Edge Acc.) over a period of many unit intervals (UI) of incoming data, and then tallied (i.e., Edge Tally) over multiple bytes of data to finally derive the majority edge position. Once the edge position is chosen, the bit in the center between the two edges is chosen as the correct data sample (i.e., Stored D _samp i _e d).

[0021] The conventional BOS CDR architecture 100 suffers from several drawbacks. For example, Boundary Selection Unit 104 that performs edge accumulation, majority tally and voting, uses adders and complicated logic which results in large power consumption, and limits the operating frequency. Boundary Selection Unit 104 also results in the need for a large Data Storage 103 to store the sampled data during this time interval, which results in power consumption and higher area. Boundary Selection Unit 104 and associated Data Storage 103 result in several UI latency to pick the appropriate phase. This degrades the power state transition performance.

[0022] One way to reduce some complexity of BOS CDR is by using a "center-picking" algorithm. In this algorithm, data bit is picked between two edges. However, BOS CDR using "center-picking" algorithm suffers from several drawbacks. For example, there is no majority voting or edge tally and so BOS CDR using "center-picking" is highly susceptible to errors caused by noise and jitter. Also, to account for the plesiochronous clocking, the overflow/underflow FIFO is large and complicated which degrades the overall power consumption, operating speed, and area.

[0023] Some embodiments describe an edge- averaging BOS CDR which obviates the use of data storage FIFO (i.e., reduces power and area), simplifies edge-recovery and corrects for underflow/overflow in plesiochronous clocking (i.e., reduces power, increases operating speed) and implements on-the-fly data recovery (i.e., reduces latency). The embodiments describe an all- digital solution; thereby they are amenable to process scaling and quick time-to market design.

[0024] In one embodiment, apparatus is provided which averages consecutive edges prior to the edge selection to provide a first order filtering response to jitter and noise. In such an embodiment, robustness of CDR is improved. In one embodiment, an edge-filter is provided which is implemented using counters. These counters can be reconfigured to change the jitter filtering bandwidth. In one embodiment, a data conditioner block is provided which obviates the need of complex underflow/overflow FIFO. In such an embodiment, circuit complexity, area and power is reduced. In one embodiment, the data conditioner uses simple logic, multiplexers, and flip-flops to ensure that the underflow and the overflow conditions are properly met by gating or inserting a data bit into the FIFO sync in the right sequence. [0025] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0026] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0027] Throughout the specification, and in the claims, the term "connected" means a direct electrical connection between the things that are connected, without any intermediary devices. The term "coupled" means either a direct electrical connection between the things that are connected or an indirect connection through one or more passive or active intermediary devices. The term "circuit" means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" means at least one current signal, voltage signal or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0028] The term "scaling" generally refers to converting a design (schematic and layout) from one process technology to another process technology. The term "scaling" generally also refers to downsizing layout and devices within the same technology node. The term "scaling" may also refer to adjusting (e.g., slow down) of a signal frequency relative to another parameter, for example, power supply level. The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 20% of a target value.

[0029] Unless otherwise specified the use of the ordinal adjectives "first," "second," and

"third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0030] For purposes of the embodiments, the transistors are metal oxide semiconductor

(MOS) transistors, which include drain, source, gate, and bulk terminals. The transistors also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. Source and drain terminals may be identical terminals and are interchangeably used herein. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors— BJT PNP/NPN, BiCMOS, CMOS, eFET, etc., may be used without departing from the scope of the disclosure. The term "MN" indicates an n-type transistor (e.g., NMOS, NPN BJT, etc.) and the term "MP" indicates a p-type transistor (e.g., PMOS, PNP BJT, etc.).

[0031] Fig. 2A illustrates BOS CDR architecture 200 with proportional integral derivative

(PID) controller and weight adjustment, according to one embodiment of the disclosure. It is pointed out that those elements of Fig. 2A having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0032] In one embodiment, architecture 200 comprises Nx Sampler 101, Synchronizer

102, Delta Select Unit 105, Edge Generator 201, Edge Filter 202, PID Controller 203, Weight Adjuster 204, Adder 206, Comparator 207, Data Select Unit 106, Data Conditioner 209, and FIFO Synchronizer 108. In one embodiment, Edge Generator 201 receives successive data samples from Synchronizer 102 and performs an XOR operation on them to generate a plurality of edges (i.e., quantized edge information). For example, successive data samples di and d ₂ are XORed to generate an edge signal ¾. One embodiment of Edge Generator 201 is described with reference to Fig. 5.

[0033] Referring back to Fig. 2A, in one embodiment, Edge Filter 202 filters the quantized edge information. One technical effect of Edge Filter 202 is that its averages consecutive edges from the plurality of edges (i.e., averages the quantized edge information) prior to edge selection to provide a filtering response to jitter and noise thereby improving the robustness of the CDR. For example, Edge Filter 202 monitors the edges over time and when multiple edges occur at the same place then it outputs a valid edge (i.e., the filtered edge information). In one embodiment, Edge Filter 202 is a first order filter. In other embodiments, a multiple order filter (e.g., second order, third order, etc.) may be used to implement Edge Filter 202. In one embodiment, Edge Filter 202 is implemented using simple counters which can be reconfigured to change the jitter filtering bandwidth. In one embodiment, Edge Filter 202 filters glitches in data. For example, if there are abrupt changes in edges between data cycles, then Edge Filter 202 filters those abrupt edges. One embodiment of Edge Filter 202 is described with reference to Fig. 6.

[0034] Referring back to Fig. 2A, in one embodiment, the filtered output from Edge Filter

202 is received by PID Controller 203. In one embodiment, PID Controller 203 generates predicted phase (PP) using the filtered response. For example, PID Controller 203 receives the averaged or filtered quantized edge information and generates predicted phase information which indicates predicted phase of the data. Here, predicted phase refers to a time point in a UI that indicates where clock edge for sampling the incoming data should be placed to sample the correct data. In one embodiment, any known PID controller may be used for PID Controller 203.

[0035] In one embodiment, output of PID Controller 203 is received by Weight Adjuster

204 which applies a weight to the closest data samples (e.g., two data samples) one on either side of the PP. In one embodiment, Weight Adjuster 204 assigns a first weight to a first quantized edge, from the quantized edge information, to generate a first weighted edge, and assigns a second weight to a second quantized edge, from the quantized edge information, to generate a second weighted edge. Here, the predicted phase information indicates a phase location of data between the first and second quantized edges. In one embodiment, output from Delta Unit 105 is used by Weight Adjuster 204. In one embodiment, Delta Unit 105 has propagation delay equal to propagation delay of Edge Generator 201, Edge Filter 202, and PID Controller 203.

[0036] In one embodiment, the weighted data samples are added by Adder 206 to generate a weighted value. For example, Adder 206 adds the first and second weighted edges and generates a summed value. In one embodiment, the summed value is compared by Comparator 207 to a threshold level to generate an output indicating whether the sampled data in a unit interval (UI) is a logical high or logical low as described with reference to Fig. 2B.

[0037] Fig. 2B illustrates a waveform 220 in a UI and the concept of phase prediction and weight adjustment using architecture of Fig. 2A, according to one embodiment of the disclosure. It is pointed out that those elements of Fig. 2B having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0038] Here, x-axis is time and y-axis is voltage. The bold dots A, B, C, and D are data sampling points for Data_in that are sampled by Nx Sampler 101 using sampling edges si, s2, s3, and s4. The sampled data (e.g., A, B, C, and D) by Nx Sampler 101, after being synchronized by Synchronizer 102 and delayed by Delta Unit 105, is provided to Weight Adjuster 204. Here, PP is the predicted phase which is between samples B (e.g., 0.5) and C (e.g., 0.5). The dashed line is the threshold (e.g., 3.0) for the comparator. In this example, sample B (i.e., first quantized edge) is closer to PP than sample C (i.e., second quantized edge) and so a higher weight (e.g., 5) is multiplied with sample B (i.e., 0.5) by Weight Adjuster 204 to generate a first weighted edge (i.e., 2.5), and a smaller weight (e.g., 2) is multiplied with sample A (i.e., 0.5) by Weight Adjuster 204 to generate a second weighted edge (i.e., 1.0).

[0039] Continuing with the example, Adder 206 adds the first weighted edge (i.e., 2.5) with the second weighted edge (i.e., 1.0) to generate the summed value of 3.5. Comparator 207 then compares 3.5 with the threshold value of 3.0. In this example, since 3.5 is greater than 3.0, output of Comparator 207 indicates that the sampled data is a logical one. [0040] Referring back to Fig. 2A, in one embodiment, output of Comparator 207 is received by Data Select Unit 106. In one embodiment, Data Select Unit 106 also provides a valid bit indication associated with the selected data sample. The valid bit indication is used to inform whether data is valid in overflow or underflow cases.

[0041] In one embodiment, selected data samples DA, DB, and their associated valid bits

VA and VB from Data Select Unit 106 are received by Data Conditioner 209. In this

embodiment, Data Conditioner 209 obviates the need of complex underflow/overflow FIFO 107 of traditional BOS-CDR 100. In one embodiment, output of Data Conditioner 209 is received by FIFO Synchronizer 108. One embodiment of Data Conditioner 209 is described with reference to Fig. 9.

[0042] Fig. 3 illustrates BOS CDR architecture 300 with Proportional (P) Controller and reconstruct unit, according to one embodiment of the disclosure. It is pointed out that those elements of Fig. 3 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Fig. 3 is described with reference to Figs. 2A-B. So, as not to obscure the embodiments, elements previously described are not described in detail again.

[0043] In one embodiment, architecture 300 comprises a Proportional Controller (also called P-Controller 301) instead of PID Controller 203. In one embodiment, P-Controller 301 provides more accurate control (generally at the cost of complexity) tracking of the phase than PID Controller 203. In this embodiment, output of P-Controller 301 is a Best Sampler Phase (BSP) instead of predicted phase. In one embodiment, BSP is received by Weight Adjuster 204 and the rest of the process described with reference to Fig. 2A continues. In this embodiment, Delta Unit 105 includes delay equal to propagation delay of Edge Generator 201, Edge Filter 202, and P-Controller 301.

[0044] Fig. 4 illustrates BOS CDR architecture 400 with edge averaging, according to one embodiment of the disclosure. It is pointed out that those elements of Fig. 4 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Fig. 4 is described with reference to Fig. 1. So, as not to obscure the embodiments, elements previously described are not described in detail again.

[0045] In one embodiment, architecture 400 comprises Nx Sampler 101, Synchronizer

102, Delta Select Unit 105, Edge Generator 201, Edge Filter 202, Edge Select Unit 401, Data Select Unit 106, Data Conditioner 209, and FIFO Synchronizer 108. In one embodiment, Edge Generator 201 receives successive data samples from Synchronizer 102 and performs an XOR operation on them to generate a plurality of edges (i.e., quantized edge information). For example, successive data samples di and d2 are XORed to generate an edge signal e ₂ . One embodiment of Edge Generator 201 is described with reference to Fig. 5.

[0046] Referring back to Fig. 4, in one embodiment, Edge Filter 202 filters the quantized edge information. In one embodiment, the filtered output from Edge Filter 202 is received by Edge Select Unit 401. In one embodiment, Edge Select Unit 401 selects either a previously identified/known edge or a filtered edge from Edge Filter 202 i.e., Edge Select Unit 401 recycles the previous edge information when no valid edge from filter is provided. One embodiment of Edge Select Unit 401 is discussed with reference to Fig. 7.

[0047] Referring back to Fig. 4, in one embodiment, output of Edge Select Unit 401 is received by Data Select Unit 106. In one embodiment, data sample associated with the selected edge from Edge Select Unit 401 is selected from Data Select Unit 106. In one embodiment, Data Select Unit 106 also provides a valid bit indication associated with the selected data sample. In one embodiment, selected data samples DA, DB, and their associated valid bits VA and VB, respectively, from Data Select Unit 106 are received by Data Conditioner 209. In one

embodiment, when combinational logic of Edge Select Unit 401 identifies an underflow, then valid bits are set low i.e., the outputs DA and DB of Data Select Unit 106 are not valid. When Edge Select Unit 401 identifies an overflow, then valid bits are set high, i.e., the outputs DA and DB of Data Select Unit 106 are valid. Data Select Unit 106 reorders data samples from the Delta Unit 105 according to edges provided by Edge Select Unit 401 such that the reordered data is in the same order as the data that was received by Nx Sampler 101. In one embodiment, Delta Unit 105 includes delay equal (or substantially equal) to propagation delay of Edge Generator 201, Edge Filter 202, and Edge Select Unit 401.

[0048] In this embodiment, Data Conditioner 209 obviates the need of complex underflow/overflow FIFO 107 of traditional BOS-CDR 100. In one embodiment, output of Data Conditioner 209 is received by FIFO Synchronizer 108. In one embodiment, Data Conditioner 209 generates clock signals and associated data samples for serially storing the data samples in FIFO Synchronizer 108. In one embodiment, FIFO Synchronizer 108 provides Data_Out which in a parallel fashion.

[0049] Fig. 5 illustrates an Edge Generator 500 for use in BOS CDR architecture, according to one embodiment of the disclosure. It is pointed out that those elements of Fig. 5 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0050] In one embodiment, Edge Generator 500 comprises a plurality of XOR logic gates

XORo-N- For purposes of explaining this embodiment, 'N' is four. In one embodiment, input to each XOR gate is a pair of successive data samples. For example, data samples d_ ₄ and do are successive samples and are received by XORo gate to generate quantized edge eo; data samples do and di are successive samples and are received by XORi gate to generate quantized edge ei; data samples di and d2 are successive samples and are received by XOR2 gate to generate quantized edge Q2, data samples d2 and d ₃ are successive samples and are received by XOR ₃ gate to generate quantized edge e3 _; data samples d ₃ and d ₄ are successive samples and are received by XOR ₄ gate to generate quantized edge e ₄ .

[0051] Fig. 6 illustrates an Edge Filter 600 for use in BOS CDR architecture, according to one embodiment of the disclosure. It is pointed out that those elements of Fig. 6 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0052] In one embodiment, Edge Filter 600 comprises a plurality of OR logic gates ORO-N and a plurality of Counters Countero-N, where 'N' is an integer. The embodiment is described with reference to 'N' being four. In one embodiment, Edge Filter 600 averages consecutive edges prior to the Edge Selection Unit 401. In such an embodiment, filtering response to jitter and noise is provided which improves robustness of the CDR. In one embodiment, quantized edges eo-e ₄ are received by OR logic gates OR ₀ -OR4 which generate reset signals rst ₀ to rst ₄ . In one embodiment, output of OR logic gates OR ₀ -OR4 is received by Countero-4 to generate a filtered output evo^. In one embodiment, Countero-4 is a one, two, or three bit a counter. In one embodiment, length of Counter is programmable. In other embodiments, counters larger than three bit counters may be used. In one embodiment, each of the counters is an UP counter. In one embodiment, each of the counters is a DOWN counter. In one embodiment, by changing the number of bits of the counter, jitter filtering bandwidth of Edge Filter 600 can be modified.

[0053] Fig. 7 illustrates an Edge Select Unit 700 for use in BOS CDR architecture, according to one embodiment of the disclosure. It is pointed out that those elements of Fig. 7 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0054] In one embodiment, Edge Select Unit 700 comprises an 'N' input OR gate (which can be implemented with a number of OR/NOR gates); 'N' number of two input multiplexers Muxo-N, and 'N' number of sequential units FFO-N, where 'N' is an integer. In this example, 'N' is four. In one embodiment, additional combinational logic is used to generate the

overflow/underflow correction es ₀ .

[0055] In one embodiment, output of OR gate is the select signal 's,' which is received by each multiplexer among multiplexers Muxo- ₄ . In one embodiment, each multiplexer receives two inputs, one input being the filtered quantized edge and the other being a latched or flopped value of the output of that multiplexer. For example, Muxi receives input evi from Edge Filter 600 and previous value of Mu i output, which is generated by FFi. Here, each sequential unit (e.g., FFi) is coupled to output of its corresponding multiplexer (e.g., Muxi) and generates an output (e.g., esi) which is coupled to another input of that corresponding multiplexer. In one embodiment, output of Muxo, output of FFo, output es ₄ , and output of Mux ₄ are received by combination logic to generate eso. In one embodiment, when all filtered quantized edge samples are one (i.e., output of 's' is one) then the selected edges are the filtered edges. In such an embodiment, the multiplexers select the filtered output. In one embodiment, when any of the filtered quantized edge samples are invalid (i.e., s=0) then Edge Select Unit 700 recycles the previous edge samples for Data Select Unit 106 i.e., it sends out the last known edge samples. In such an embodiment, the multiplexers select the output from the flip-flops

[0056] Fig. 8 illustrates a Data Select Unit 800 for use in BOS CDR architecture, according to one embodiment of the disclosure. It is pointed out that those elements of Fig. 8 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0057] In one embodiment, Data Select Unit 800 comprises combination logic having

NAND (or AND) and OR (or NOR) gates. In one embodiment, each AND gate receives selected edge signal from Edge Select Unit 700 and one of the data samples from Delta Unit 105. In one embodiment, output of each AND gate is received by an OR gate to generate a data signal. In this example, two data signals DA and DB are generated by the two OR gates. In one embodiment, valid bits corresponding to the data signals are generated by OR gates. In such an embodiment, selected edge signals eso to es ₄ are received by OR gates to generate valid bits VA and VB. Here, VA corresponds to DA, and VB corresponds to DB.

[0058] As discussed above, in BOS, Rx Clock for oversampling incoming data is faster than incoming data. When edges of Rx Clock used to sample a frame of data cannot determine where to place the edge to sample the data, underflow is indicated. Underflow indication causes VA and VB to be logical low. Logical low VA and VB indicate invalid data DA and DB. In one embodiment, clock signals CK0 and CK1 (as shown in Fig. 9) remain low when VA and VB are low. In such an embodiment, data DA and DB is not stored in FIFO Synchronizer 108. When edges of Rx Clock used to sample a frame of data determine where to place the edge to sample the data, overflow is indicated because multiple edges may sample the same data. Overflow indication causes VA and VB to be logical high. Logical high VA and VB indicate valid data DA and DB. In one embodiment, clock signals CK0 and CK1 toggle when VA and VB are high. In such an embodiment, data DA and DB are stored in FIFO Synchronizer 108.

[0059] Fig. 9 illustrates a Data Conditioner 900 for use in BOS CDR architecture, according to one embodiment of the disclosure. It is pointed out that those elements of Fig. 9 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0060] In one embodiment, Data Conditioner 900 comprises sequential units FFi, FF ₂ , and

FF ₃ , combinational logic gates logici, logic ₂ , and logics; and multiplexers Muxo- ₃ . In one embodiment, FFi and FF ₂ receive valid bits VA and VB. In one embodiment, output of FFi is received by logici gate. Here logici gate is an AND gate. In one embodiment, output of FF ₂ is inverted and received by logici gate. In one embodiment, output of logici is received by logic ₂ . In one embodiment, logic ₂ is an XOR gate. In one embodiment, valid bit VA is inverted and received by logics. In one embodiment, logic ₃ is an AND gate. In one embodiment, the other input to logic ₃ is valid bit VB. In one embodiment, output of logic ₃ is received as second input of logic ₂ . In one embodiment, output of logic ₂ is received as enable signal for FF ₃ .

[0061] In one embodiment, output of FF ₃ is used as select signal for multiplexers Muxo- ₃ .

In one embodiment, inverted version of output of FF ₃ is received as input to FF ₃ . In one embodiment, output of FF ₃ is inverted to generate select signal for Muxi and MUX ₃ . In one embodiment, output of FF3 is used as select signal for Muxo and Mux ₂ . In one embodiment, Muxo and Mux _! receive valid bits VA and VB as input and generate clock signals CKO and CKl. In one embodiment, Mux ₂ and MUX ₃ receive selected data DA and DB and generate corresponding data DO and Dl respectively. In one embodiment, when data is valid i.e., VA and VB are logical high, Data Conditioner 900 causes Clocks CKO and CKl to transition from logical low to logical high.

[0062] In such an embodiment, output data DA and DB passes on as DO and Dl which are stored in FIFO Synchronizer 108. In one embodiment, when data is valid i.e., VA and VB are logical low, Data Conditioner 900 causes Clocks CKO and CKl to transition to logical low. In such an embodiment, output data DA and DB are swizzled when passed on as DO and Dl. In such an embodiment, DA is passed on as Dl and DB is passed on as DO.

[0063] Fig. 10 illustrates a FIFO Synchronizer 1000 for use in BOS CDR architecture, according to one embodiment of the disclosure. It is pointed out that those elements of Fig. 10 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0064] In one embodiment, FIFO Synchronizer 1000 comprises a first set of flip-flops

FFA _O - _N and a second set of flip-flops FFB ₀ - _N , where 'N' is an integer. For purposes of describing this embodiment, 'N' is seven. The first set of flop-flops form a first FIFO, while the second set of flip-flops form a second FIFO. In one embodiment, output DO and Dl of Data Conditioner 209 are stored in respective FIFOs. In one embodiment, first FIFO is clocked by clock signal CKO while the second FIFO is clocked by clock signal CKl . In one embodiment, output of flip-flops FFAo-7 are OutO-7 and output of flip-flops FFB ₀ -7 are Out 8-15. These outputs are combined to form a parallel bus Data_out.

[0065] Fig. 11 illustrates an I/O system 1100 having a receiver which includes the BOS

CDR architecture, according to one embodiment of the disclosure. It is pointed out that those elements of Fig. 11 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0066] In one embodiment, I/O system 1100 includes a transmitter Tx which receives

Data_TX_in. Data_TX_in transmitted by Tx over transmission line (TL) to receiver Rx. In one embodiment, Rx includes one of the BOS CDR architecture of various embodiments. In one embodiment, output of Rx is Data_out. In one embodiment, the Rx and Tx are MIPI® MPHY compliant receiver and transmitter as described in the MIPI® Alliance Specification for M-PHY ^SM Version 1.00.00 of February 8, 2011 and approved on April 28, 2011. In other embodiments, Rx and Tx are compliant to other standards.

[0067] Fig. 12 is a smart device or a computer system or an SoC (System-on-Chip) with

BOS CDR architecture, according to one embodiment of the disclosure. It is pointed out that those elements of Fig. 12 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0068] Fig. 12 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In one embodiment, computing device 1700 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1700.

[0069] In one embodiment, computing device 1700 includes a first processor 1710 with

BOS CDR architecture described with reference to embodiments discussed. Other blocks of the computing device 1700 may also include BOS CDR architecture described with reference to embodiments discussed. The various embodiments of the present disclosure may also comprise a network interface within 1770 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

[0070] In one embodiment, processor 1710 (and processor 1790) can include one or more physical devices, such as microprocessors, application processors, microcontrollers,

programmable logic devices, or other processing means. The processing operations performed by processor 1710 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1700 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

[0071] In one embodiment, computing device 1700 includes audio subsystem 1720, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1700, or connected to the computing device 1700. In one embodiment, a user interacts with the computing device 1700 by providing audio commands that are received and processed by processor 1710.

[0072] Display subsystem 1730 represents hardware (e.g., display devices) and software

(e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1700. Display subsystem 1730 includes display interface 1732, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 1732 includes logic separate from processor 1710 to perform at least some processing related to the display. In one embodiment, display subsystem 1730 includes a touch screen (or touch pad) device that provides both output and input to a user.

[0073] I/O controller 1740 represents hardware devices and software components related to interaction with a user. I/O controller 1740 is operable to manage hardware that is part of audio subsystem 1720 and/or display subsystem 1730. Additionally, I/O controller 1740 illustrates a connection point for additional devices that connect to computing device 1700 through which a user might interact with the system. For example, devices that can be attached to the computing device 1700 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

[0074] As mentioned above, I/O controller 1740 can interact with audio subsystem 1720 and/or display subsystem 1730. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1700. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1730 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1740. There can also be additional buttons or switches on the computing device 1700 to provide I/O functions managed by I O controller 1740. [0075] In one embodiment, I/O controller 1740 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1700. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[0076] In one embodiment, computing device 1700 includes power management 1750 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 1760 includes memory devices for storing information in computing device 1700. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1760 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1700.

[0077] Elements of embodiments are also provided as a machine -readable medium (e.g., memory 1760) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine -readable medium (e.g., memory 1760) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[0078] Connectivity 1770 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1700 to communicate with external devices. The computing device 1700 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

[0079] Connectivity 1770 can include multiple different types of connectivity. To generalize, the computing device 1700 is illustrated with cellular connectivity 1772 and wireless connectivity 1774. Cellular connectivity 1772 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile

communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1774 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

[0080] Peripheral connections 1780 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1700 could both be a peripheral device ("to" 1782) to other computing devices, as well as have peripheral devices ("from" 1784) connected to it. The computing device 1700 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1700. Additionally, a docking connector can allow computing device 1700 to connect to certain peripherals that allow the computing device 1700 to control content output, for example, to audiovisual or other systems.

[0081] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1700 can make peripheral connections 1780 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), Display Port including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[0082] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[0083] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0084] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures e.g., Dynamic RAM (DRAM) may use the embodiments discussed. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[0085] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[0086] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[0087] For example, an apparatus is provided which comprises: a sampler to sample data using blind oversampling technique; an edge generator to receive sampled data and to generate quantized edge information using the sampled data; an edge filter to average the quantized edge information; and a proportional integral derivative (PID) controller to receive averaged quantized edge information and to generate predicted phase information which indicates predicted phase of the data.

[0088] In one embodiment, the apparatus further comprises a weight adjuster to assign a first weight to a first quantized edge, from the quantized edge information, to generate a first weighted edge. In one embodiment, the weight adjuster assigns a second weight to a second quantized edge, from the quantized edge information, to generate a second weighted edge. In one embodiment, the PID to generate the predicted phase information indicating a phase location of data between the first and second quantized edges. In one embodiment, the apparatus further comprises an adder to add the first and second weighted edges and to generate a summed value.

[0089] In one embodiment, the apparatus further comprises a comparator to compare the summed value against a threshold, the comparator to generate an output indicating whether the sampled data in a unit interval (UI) is a logical high or logical low. In one embodiment, the apparatus further comprises a data conditioner to generate reordered data samples with associated clock signals for storing in a storage unit. In one embodiment, the edge filter comprises an up- down counter. In one embodiment, the edge filter is a first order digital filter. In one embodiment, the edge filter is a multiple order digital filter. In one embodiment, the edge generator comprises an exclusive-OR (XOR) gate.

[0090] In another example, a system is provided which comprises: a memory unit; and a processor coupled to the memory unit, the processor having a receiver according to the apparatus discussed above. In one embodiment, the system further comprises a wireless interface for allowing the processor to communicate with another device. In one embodiment, the system further comprises a display unit. In one embodiment, the receiver is MIPI MPHY compliant receiver as described in the MIPI® Alliance Specification for M-PHY ^SM Version 1.00.00 of February 8, 2011 and approved on April 28, 2011. In other embodiments, the receiver is compliant to other standards.

[0091] In another example, an apparatus is provided which comprises: a sampler to sample data using blind oversampling technique; an edge generator to receive sampled data and to generate quantized edge information using the sampled data; an edge filter to average the quantized edge information; and a proportional controller to receive quantized edge information and to generate best sample phase information which indicates a location in time to sample data properly. In one embodiment, the apparatus further comprises an edge selector to select an edge for quantized edge information according to the best sample phase information.

[0092] In one embodiment, the apparatus further comprises a data selection unit to select data from the sampled data using the selected edge. In one embodiment, the apparatus further comprises a data conditioner coupled to the data selection unit, the data conditioner to generate reordered data samples with associated clock signals for storing in a storage unit. In one embodiment, the edge filter comprises an up-down counter. In one embodiment, the edge filter is a first order digital filter. In one embodiment, the edge filter is a multiple order digital filter. In one embodiment, the edge generator comprises an exclusive-OR (XOR) gate.

[0093] In another example, a system is provided which comprises: a memory unit; and a processor coupled to the memory unit, the processor having a receiver according to the apparatus discussed above. In one embodiment, the system further comprises a wireless interface for allowing the processor to communicate with another device. In one embodiment, the system further comprises a display unit. In one embodiment, the receiver is MIPI MPHY compliant receiver as described in the MIPI® Alliance Specification for M-PHY ^SM Version 1.00.00 of February 8, 2011 and approved on April 28, 2011. In other embodiments, the receiver is compliant to other standards.

[0094] In another example, an apparatus is provided which comprises: a sampler to sample data using blind oversampling technique; an edge generator to receive sampled data and to generate quantized edge information using the sampled data; an edge filter to average the quantized edge information; and a edge select unit to select an edge according to an output of the edge filter, the edge for selecting data from the sampled data. In one embodiment, the apparatus further comprises a data selection unit to select data from the sampled data using the selected edge. In one embodiment, the apparatus further comprises a data conditioner coupled to the data selection unit, the data conditioner to generate reordered data samples with associated clock signals for storing in a storage unit.

[0095] In one embodiment, the edge filter comprises an up-down counter. In one embodiment, the edge filter is a first order digital filter. In one embodiment, the edge filter is a multiple order digital filter. In one embodiment, the edge generator comprises an exclusive-OR (XOR) gate.

[0096] In another example, a system is provided which comprises: a memory unit; and a processor coupled to the memory unit, the processor having a receiver according to the apparatus discussed above. In one embodiment, the system further comprises a wireless interface for allowing the processor to communicate with another device. In one embodiment, the system further comprises a display unit. In one embodiment, the receiver is MIPI MPHY compliant receiver as described in the MIPI® Alliance Specification for M-PHY ^SM Version 1.00.00 of February 8, 2011 and approved on April 28, 2011. In other embodiments, the receiver is compliant to other standards.

[0097] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.