Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
APPARATUSES AND METHODS INCLUDING FERROELECTRIC MEMORY AND FOR ACCESSING FERROELECTRIC MEMORY
Document Type and Number:
WIPO Patent Application WO/2018/044487
Kind Code:
A1
Abstract:
Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell plate of the capacitor, a second digit line, and a second sense node. The voltage of the second cell plate and the second digit line is decreased to change the voltage of the first cell plate, a first digit line, and a first sense node. The first node is driven to a first voltage and the second node is driven to a second voltage responsive to the voltage of the first node being greater than the second node. The first node is driven to the second voltage and the second node is driven to the first voltage responsive to the voltage of the first node being greater than the second node

Inventors:
DERNER, Scott J. (5032 E. Sagewood Drive, Boise, Idaho, 83716, US)
KAWAMURA, Christopher J. (1778 S. Toluka Way, Boise, Idaho, 83712, US)
Application Number:
US2017/045182
Publication Date:
March 08, 2018
Filing Date:
August 02, 2017
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
MICRON TECHNOLOGY, INC. (8000 South Federal Way, Boise, Idaho, 83716, US)
International Classes:
G11C11/22; H01L27/11502
Foreign References:
US20020044477A12002-04-18
US20090010037A12009-01-08
US20120170348A12012-07-05
US20080265300A12008-10-30
US5959922A1999-09-28
Attorney, Agent or Firm:
END, Kimton et al. (DORSEY & WHITNEY LLP, 701 5th AveSuite 610, Seattle Washington, 98104, US)
Download PDF:
Claims:
CLAIMS

What is claimed is:

1 , A method, comprising:

increasing a voltage of a first cell plate of a capacitor to change a voltage of a second ceil plate of the capacitor, a second digit line, and a second sense node;

decreasing the voltage of the second ceil plate and die second digit line t change the voltage of the first ceSi plate, a first digit Mae, and a first sense node;

driving the first sense node to a first voltage and driving the second sense node to a second voltage responsive to the voltage of the first sers.se node being greater than the voltage of the second sense node; gad

driving the first sense node to the second voltage and driving the second sense node to the 'first voltage responsive to the voltage of the first sense node being less than the voltage of the second sense node,

2, The method of claim 1 wherein the voltage of the first sense node is greater than the voltage of the second sense node when the capacitor has a first' polarization, aftd wherein the -voltage of the first sense node is less than the voltage of second sense node when the capacitor has a second polarization different than, the first polarization.

3, The method of claim 1, further comprising providing a constant voltage to the second sense node as a reference voltage.

4, The method of claim 3 wherein decreasing the voltage of the second cell plate and the second digit line comprises decreasing the voltage of th second cell plate from the constant voltage to ground,

5, The method of claim 1 wherein the second cell plate of the capacitor changes from an initial voltage to a first increased voltage responsive to increasing the voltage of the first cell plate for a first polarization of the capacitor and wherein the second cell plate of the capacitor changes from the initial voltage to second increased voltage responsive to increasing the voltage of the first cell plate fox a second polarization of the capacitor, the second and third voltages are different.

6. The method of claim 5 wherein decreasing the voltage of the second cell plate and the second digit line comprises decreasing the voltage of the second eel! plate from the first or second increased to tire initial voltage.

7. A method, comprising:

providing a read voltage to a first digit line and to a first plate of a capacitor coupled to the first digit line to cause a voltage of a second plate of the capacitor, of a second digit line coupled to the second plate of the capacitor, and of a second sense node of a sense component to change from an mi rial voltage to a increased, voltage, the second sense -node coupled to the second digit line;

coupling a first sense node of the sense component to the first digit line;

decoupling the second sense node from the second, digit line;

driving the voltage of the second digit line and the second plate of the capacitor from the increased voltage to the initial voltage t cause a voltage of the first plate of the capacitor, the first digit line, and the first sense node to change;

comparing at the sense component the voltage of the first sense node to a reference voltage; and

based on the comparison, driving the first sense node, first digit line, and first plate of the capacitor to a first voltage and driving the second sense node, second digit line, and Second plate of the capacitor to a second voltage, the second voltage complementary to the first voltage.

8. The method of claim 7, further comprising activating selection components to coiiple the first plate of the capacitor to the first digit line and to couple the second plate of the capacitor to the second digit line.

9. The method of claim ?, farther comprising:

changing the voltage of the first and second plates of the capacitor to a same voltage; and deactivating selection components to isolate the first plate and the second plate of "the capacitor from the first and second digit lines, respectively.

10. The method of claim 7 wherein the initial voltage is ground.

13. The method of claim 7 wherein driving the first sense node, first digit line, and first plate of the capacito to a first voltage and driving the second sense node, second digit line, and second plate of the capacito to & second, voltage, the second voltage complementary- to the first voltage, comprises:

driving the first sense node, first di it Sine, and first plate of the capacitor to ground sad driving the second sense node, second digit line, and second piate of the capacitor to the read voltage responsive to the voltage of the first sense node being less than the reference voltage; and

driving the first sense node, first digit line, and first plate.- of the capacitor to the read voltage and driving the second sense node, second digit line, and second plate of the capacitor to ground responsive to the voltage of the firs sense node being greater than the reference voltage,

12. TSie method of claim 7 wherein the reference voltage is a constant voltage,

13. The method of claim ? wherein the reference voltage is a first reference voltage responsive to a first, increased voltage and wherein the reference voltage is a second reference voltage that is different than the first reference voltage responsive to the a second increased voltage.

14. A method, comprising:

coupling a voltage increase across a capacitor from a first plate to a second plate, a resulting voltage at the second plate provided t a sense component, the resulting voltage at the second plate having a first voltage responsive to the capacitor ftaving a first polarization and havin a second voltage responsive to the capacitor having a second polarization; c u ling a voltage decrease across th capacitor from the second plate to the first plate, a resultkig voltage- at the first plate provided to the sense component; sa latching at the sense component a voltage difference between the resulting voltage at the first plate and a referefice voltage.

35. The method of claim 14 wherein the reference voltage is die resulting voltage at the second plate.

16. The method of claim .1 wherein the reference voltage is a constant voltage.

17. The method of claim. 14, further comprising:

ontputting 'a first logic value when the resulting voltage at die first plate is greater tha the: reference voltage; and

ottiputiing a second logic value when the resetting voltage at five first plate is less than the reference vol tage.

18. The method of claim 1.4 wherein coupling -a voltage decrease across the capacitor from the second plate to the firs plate comprises driving the second plate from the resulting voltage at the secon plate to ground.

19. The method of claim 14 wherein coupling a voltage increase across a capacitor from a first plate to a second plate comprises driving the first plate from .ground to a read voltage;

20. The method of claim 14 wherein latching at the sense component a voltage difference between, the resulting' -voltage at 'the first plate and. the reference voltage comprises:

detecting the voltage difference between the resulting, voltage at the first plate and the reference voltage; and

amplifying the voltage difference between the resulting voltage at the first plate and the reference voltage. -JO

21. The method of claim 14, further comprising restoring the polarization of the capacitor with the latched voltages.

22. A method, comprising:

providing a read voltage to a first plate of a ferroelectric memory ceil to change a voltage on a second plate of the ferroelectric memory cell;

driving ilie seeoad plate of die ferroelectric memory cell to ground to change a voltage on the first plate of the : ferroelectric memory cell;

after driving the second plate of the ferroelectric memory cell to ground, comparing the voltage on the -first plate of the ferroelectric memory eel! to a reference voltage at a sense node;

providing a first voltage to the sense node responsi ve to the voltage on the first plate of the ferroelectric memory cell being less than the reference voltage; and

providing a second voltage to die sense node responsive to the voltage on the first plate of the ferroelectric memory ceil being greater than the reference voltage.

23. The method of claim 22, further comprising:

providing the second' voltage to a complementary- sense node responsive to the voltage on the first plate of the ferroelectric memory eel! being less than the reference voltage; and

providing the first voltage to the complementary sense node responsive to the voltage on the first plate of the ferroelectric rneniory ceil being greater than the reference voltage.

24. The method of claim 22, further comprising:

providing the first voltage to the second plate of the ferroelectrk memory cell responsive to the voltage on the first plate of the ferroelectric memory cell being less than the reference voltage; and

providing the second voltage to the second plate of the ferroelectric- .memory cell responsive to the voltage on the first plate of the ferroelectric memory ceil being greater than the reference voltage.

25. The method of claim 22, further comprising providing a reference signal to the sense node, the reference signal having die reference voltage,

26, The metticd of claim 22 wherein the reference voltage at the sense node is based o the voltage on the second plate of the ferroelectric memory ceil resulting from providing the read voltage to the- first plate of the ferroelectric memory cell,

27. The method of claim 22 wherein the reference voltage at the sense node is a first reference voltage responsive to a first polarization of the ferroelectric memory cell and the reference voltage at the sense node is & second reference voltage responsive to a second polarization of the ferroelectric memory cell,

28, An ap aratus, comprising:

a first digit line;

a second digit line;

a ferroeiectric memory cell including a ferroelectric capacitor, a first selection component, and a second selection component the first selection component' coupled between the first digit line and a first plate of the ferroeiectric capacitor and the second selection component coupled between the second digit line and a second plate of the ferroelectric eapaes tor;

a first word line coupled to a gate of the first selection component;

second word line coupled to a gate of the second selection component;

a sense component including, a first sense node coupled to the first digit line through a switch.', and further including a second sense node coupled to the second digit line through, an isolation switch, the sense component configured to latch voltages of the first and second sense nodes;

a first driver circuit coupled t the first digit line and configured to provide a read voltage when activated and

a second driver circuit coupled to the second digit line and configured to provide a ground voltage when activated.

29. The apparatus of claim 28, further comprising a reference switch coupled to the second sense node and configured to provide a eanstaut reference voltage to the first sense node wl ten activated.

30. The apparatus of claim 28, further comprising a memory controller configured to control the first driver circuit to drive the first digit line to a read voltage mi to deactivate- ie second selection component,, the memory controller farther configured to control the second driver circuii to dri ve the second digit line to ground and control the sense component to compare the voltage of die first sense node to the voltage of the second sense node.

Description:
I

APPARATUSES AND METHODS INCLUDING FERROELECTRIC MEMORY AND FOR ACCESSING FERROELECTRIC MEMORY

CROSS-REFERENCE TO RELATED APPLICATION

] This application claims the filing benefit of U.S.. Provisional Application .No.

62/381,900, filed August 31 , 2016, This application is incorporated by reference- herein in its entirety and for all purposes.

BACKGROUND

] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication, devices, cameras, digital displays, and the like, Information is stored by programing di fferent states of a memor device. For example, binary devices have two states, often denoted by a logic "1 " or a logic ** ø." in -other systems, more than two states may be stored. To access the stored information, the electronic device may read, or sense, the stored state in the memory device. To store information, the electronic devic may write, or program, the state in the memory device,

] Various types of memory devices exist including random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic- RAM (SDRAM), ferroelectric RAM: (FeRAM), magnetic RAM. (MRAM), resistive RAM (RRAM), flash memory, and others. Memory devices may be volatile or nonvolatile. ' Hon- volatile memory, e.g., flash memory, can store data for extended periods of time even in the absence of an externa! power source. Volatile memory ..devices, e.g., DRAM, may lose their stored state over time unless they are periodically refreshed by an external power source, A binary memory device may, for example, include a. charged or discharged capacitor. A charged capacitor may, however, become discharged over time through leakage currents, resulting in the loss of the stored information. Certain features of volatile memory may offer performance advantages, such: as faster i¾ad or write speeds, while features of non-volatile memory, such as the ability to store data without periodic refreshing, may be advantageous,

] FeRAM may use similar ' device · architectures as volatile memory' but may have non-volatile properties due to the use of a ferroelectric capacitor as a storage device. FcRAM devices ma thos have improved performance compared to -other non-volatile and volatile tiaecntxy devices, It is desirable, however, to improve the operation of FeRAM devices. For example,: it may be desirable to have improved noise resistance during memory cell sensing, more compact circuits and reduced layout size, and improved timing for operation of FeRAM devices.

SUMMARY

j§05| Apparatuses and methods ar disclosed that include ferroelectric memory and for accessing ferroelectric memory. In an aspect -of the disclosure, an example method includes increasing a voltage of a first cell plate of a capacitor to change ise voltage of a second eel! plate of the capacitor, a second digit line, and second sense node. Tie voltage of the second cell plate and the second digit line is decreased to change the voltage of the first cell plate, a first digit line, and a first sense node. The first node is driven to a first voltage and the second node is driven to a second voltage responsive to the voltage of the first node being greater than the second node. The first node is driven to the second, voltage and the second node is driven to the first voltage responsive to the voltage of the first node being greater than the second node.

[0 6 In another aspect of the disclosure, an example apparatus includes first and second digit lines, a ferroelectric: capacitor., first and second word .lines, a sense component, and first and second drivers. The ferroelectric memory cell includes a ienOel.ect.ric capacitor, a first selection component, and a second selection component The first selection -component is coupled between the first digit line and a first plate of the ferroelectric capacitor and the second selection component coupled between the second digit line and a second plate of the ferroelectric capacitor. The first word line is conpled to a gate of the first selection component and the second word line is coupled to a gate of the second selection- component.: The sense component includes a first sense node coupled to the first digit line through a switch and further includes a second sense node coupled to the second digit: line through an isolation switch. The sense component is configured to latch voltages of the first and second sense nodes. The first driver circuit is coupled to the first digit line and configured to provide read voltage when activated. The second driver circuit is coupled to the second digit line and configured to provide a ground voltage when activated. BRIEF DESCRIPTION OF THE DRAWINGS

[807} Figure 1 is a Mock diagram of an exam le memory array (feat supports ferroelectric memory in accordance with various embodiments of the present disclosure.

}00$} Figure 2A is a schematic diagram of an example circuit that includes a column of memory cells according to an embodiment of the present disciosure. Figure 2B is a schematic diagram of a sense component according to an embodiment of the disclosure.

[009J Figure 3A and Figure 3B are diagrams of example non-Hsiear electrical properties for a ferroelectric memory cell in accordance with various embodiments of the present disclosure.

|0I8] Figures 4A-4.E are timing diagrams of various signals during a read operation according to -an embodiment of the disclosure.

}0I.lj Figures 5A-5E are timing diagrams of various signals during a read operation according to an embodiment of the disclosure.

[012] Figure 6 is a timing diagram of various signals during a write operation according to an embodiment of the disclosure.

jM3| Figure 7 is a timing diagram of various signals during a write operation according to as embodiment of the disciosure.

}0l4j Figure 8 is a diagram depicting a cross-sectional side view of a portion of a memory array showing memory cells according to an embodiment of the disclosure. }015j Figure 9 is a block diagram of a memory array that supports a ferroelectric memor in accordance with various embodiments of the present disclosure,

j 0 J 6] Figure 10 i s a block diagram of a s stem that supports a ferroelectric memory in accordance with various embodiments of the present disclosure,

DETAILED DESCRIPTION

01 } Certain details are set forth below to provide a sufficient understanding of embodiments of the. disclosure. However, it will be clear to one skilled in the art that embodiments of the disclosure may be practiced without these particular details. Moreover, the particular embodiments of the present disclosure described herein are pro vided by way of example and should not be used to limit the scope of the disclosure to these particular embodiments. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the disclosure.

f018 Figure .1 illustrates an example memor array 100 that supports ferroelectric memory in accordance with various embodiments of die present disclosure. Memory array 100 may aiso be referred to as an electronic memory apparatiis. Memor array 100 includes. ' memory cells 105 that are programmable to store different states. Each state: may represent different logic Values. For example, for a memory storing two. states, the logic values may be denoted as a logic 0 and a logic 1. in some cases, memory cell 105 is configured to store more than two logic slates. A memory cell 105 may include a capacitor to store a charge representative of the programmable states. Fo example, a charged and uncharged capacitor may represent two logic states, respectively.

|01 ] A ferroelectric memory ceil may include a capacitor that has a ferroelectric as the dielectric materia!. Different levels of charge of a ferroelectric capacitor may represent different logic states. Ferroelectric memory ceils .105 may have beneficial properties that may resul in improved performance relative to othe memory architectures, for example, persistent storage of logic state without the need for periodic refresh operations.

|020) Operations such as reading and writing may be per.fon.ned on memory cells 105 b -activating -or selecting the appropriate access line .1 10 and digit lines 115. Access lines 1 10 may also be referred, to as word lines ! 10, Activating o selecting a word line i 10 or a. digit line 115 ma include applying a voltage to the .respective line. Word lines 110 and digit lines 115 are made of conductive materials. For example, ward lines 110 and digit lines 115 may be made of metals (such as copper, aluminum, gold, tungsten, etc.), metal alloys, doped .semiconductors, other conductive materials, or the like. According to the example of Figure 1, each row of memory cells 1 5 is coupled to word lines 110 WL-CT and WL-CB, and each column of memory cells 105 is coupled -to digit hues 115 BL-CT * and. BL-CB. By activating the respective word lines 1 10 and digit lines 1 15 (e.g., applying voltage to the word lines 1 1 or digit lines 1 15), a memory cell 105 may be accessed at their intersection. Accessing the memory cell 105 ma include reading or writing the memory cell 105. The intersection of a word lines 1 10 and digit lines I IS ma be referred to as an address of a memory cell

[021 J In some architectures, : the logic storing device of a cell e.g., a capacitor, may be electrically isolated from the digit lines by selectio components. A word line 110 may be coupled to and may canto! a respective selection component. For example-, the selection component may be a transistor and the word line 1 10 may be coupled to the gate of the transistor. Activating -the word Sine S 10 results in an electrical -coupling or closed circuit between ' the capacitor of a memory cell 105 and corresponding digit line Ϊ 15. The digit lines may then be accessed to either read or write the memory eel! 105.

[022] Accessing memory cells 105 may be controlled through a row decoder 120 and a column decoder 130. in some examples, a row decoder 120 -receives a row address from the memory controller 140 and aetivates the appropriate word lines I lf) based on die received row address. Similarly, a column decoder 130 receives a colomu -address from the memory controller- 14Q and activates t e appropriate digit lines 1 15. For example, memory array 100 may include multiple word lines 1 10, and multiple digit lines 115. T¾us, by activating word lines 1 10 WL-CT and WL-CB and digit lines 115 BL-CT and BL-CB, the memory cell 105 at their intersection may be accessed.

[023] Upon accessing, a memory ceil 105 may be read, or sensed, by sense component 125; to determine- the stored state of the memory cell 105. For example, after accessing fee memory cell 105, the ferroelectric- capacitor of memory ceil 105 may discharge onto corresponding digit lines 1 15. Discharging the ferroelectric capacitor may be based on biasing - or applying a voltage, to the ferroelectric capacitor. The discharging.- may cause a change in the voliage of the digit lines 11.5, which sense component 125 may compare to a reference voliage (not shown) m order to determine the stored state of fee memory cell 105, For example, if a digit line l ! S has a higher voltage than the reference voltage, then sense component 125 may determine that the stored state in memory ceil 105 is a logic 1 and vice versa. Sense component 125 may Include various transistors or amplifiers hi order to detect (e.g., compare) and amplify a difference in the signals, which may include latching the amplified, difference. A separate sense component 125 may be provided for each, pair of digit lines BL-CT and BL-CB. The detected logic state of memory cell 105 may then he output through column decoder 130 as output 135. 024] A memory celt 1 5 may be programmed, or written, by activating me relevant word lines H - and digit lines 115. As discussed above, activating word Uses 1 10 electrically couples the corresponding row of memory cells 105 to their respective digit lines 115. By controlling ' the -relevant digit lines Π while the word lines 110 are activated, a memory cell 105 may he written— e.g., a logic value may he stored in the memory ceil 105. Column decoder 130 may ' accept data, for example input 135, to be written to the memor cells 105. A ferroelectric, memory cell 105 ma be written by applying a voltage across the ferroelectric capacitor. This process is discussed in more detail below.

0251 In some memory architectures, accessing the memory cell 105 may degrade or destroy the stored logic state, and re-write (e.g., restore) operations m be performed to return the original logic state to memory ceil 105. For example, the capacitor ma be partially or completely discharged during a sense operatioii, eomipthig the stored logic state. So the logic state may be -re- written after a sense operation. Additionally, activating word lines 110 may result, in the discharge of all memory cells in the row. thus, several or all memory ceils 105 in the row may need to be re-written.

[026] The memory controller 140 ma control the operation (e.g., read, write, rewrite, etc.) of memory cells 305 throug the various components, such as row decoder 120, column decoder 130, and sense component 125. Memory controller .14 may generate row an column address signals is order to activate the desired word lines 1 1 and digit lines 115, Memory controller 140 ma also generate and control various voltage potentials used during the -operation of memory array 100. in general, the amplitude, shape, or duration of an applied voltage discussed herein may he: adjusted -or varied and may be different for the various operations for operating memory ' arra 1 0. Furthermore, ' oae, multiple, or all memory cells 1 5 within memory array 1 0 may be accessed- simultaneously. For example, multiple or. all cells of .memory array 100 may ¬ be accessed -simultaneously during a reset operation in which ail memory ceils 105, or a group of memory cells 105, are set to a single logic state.

027] Figure 2 A illustrates an example circuit 200 that includes column ' of memory cells according to an embodiment of the present disclosure. Figure 2 illustrates an example circuit 200 that includes memory cells 105 in accordance with various embodiments of the present disclosure. Circuit.200 includes memory cells 1 5 MC(0)- MC(ii), where "a" depends on the array size. The circuit 200 .further includes word lines WL-CT(0)- WL-CT(n) a»d WL-CB(0)-WL-CB(a) t digit ikes BL-CT and BL-CB, and sense component 125. The word lines, digit lines, and. sense component may be examples of memory cells 105, word lines I K\ digit lines 1 15, and sense component 125, respectively, as described with reference to Figure 1. While one column and n rows of memory cells 105 are shown in Figure 2 A, a memory array may include many columns and rows of memor cells as those shown,

j § 81 Memo cells 105 may include , a logic storage component, such as capacitor

205 that has a first plate, cell top 230, and a second plate, cell bottom 215. Ceil tops

23 and cell bottoms 215 may be capacitively coupled through a ferroelectric material positioned between them. The ' .orientation of cell tops 230 and cell bottoms 2.15: may be flipped without changing the operation of memory ceil 105. The memory cells 105 may further include selection components 220 arid 224. The selection components 220 and 224 may be transistors. For examp e, n-type field effect transistors. n. such an example, each of fee- memory cells 105 includes two transistors and one capacitor (e.g., 2T1C).

[029] Circuit 200 also includes isolation switch 231. and reference switch 233. A reference signal VBLEEF is provided to the .reference switch 233. The isolation switch

231 and the reference switch 233 are coupled to a sense node A of the -sense component 125. Activation of the isolation switch 231 is controlled by a signal ISO and activation of the reference switch 233 is controlled by a signal ISORBF. in some embodiments, the reference, switc 233 is not included in the circuit 200. For example, in embodiments where the circuit 200 provides on its own reference voltage for determining the logic value stored by a memory cell 1 5. in such embodiments, providing a separate reference voltage (e.g., the voltage VREF of the VBLREF reference signal) to the sense ' component 125 is. not necessary. Circuit 200 also includes switch 235 and driver circuits 237 and 239. In some examples, isolation switch 231, reference switch 233, .and switch 235 may be transistors, for example, n« type field effect transistors, which may be activated by applying a voltage equal to or greater than its threshold voltage. Activation of the switch 235 is controlled by a signal RESTORE. The driver circuit 237 provides a VREAD voltage when activated and the driver circuit 239 provides a ground voltage when activated. 0] Memory cells 105 ma be in electronic communication with sense component 125 through digit line BL-CT arid digit line BL-CB. The switch 235 may be coupled m series between &e. sense, c mponent .125 aud the digit litre BL-CT and the driver circuit 237. The switch 235 electrically coupi.es or isolates the sense component 5 from the memory ceils 1.05 and the driver circuit 237. In the example of Figure 2A, ceil tops 230 may be accessed via digit line BL-CT and cell bottoms may be accessed via digit line BL-CB. As described above, various states may be stored b charging or discharging capacitor 205.

i| The stored stars of capacitor 205 may be read or sensed by operating various elements represented in circuit 200. Capacitor 205 may be in electronic communicatsou with digit lines -BL-CB .and BL-CT. For example, capacitor 205 can be isolated from digit lines BL-CB and BL-CT when seleeticni components 220 and 224 are deactivated,, and capacitor 205 can be coupled to digit lines BL-CB and BL-CT when selection components 220 and 224 are activated. Activating selection components 220 and 224 may be referred to as selecting- memory cell 105. In some cases, selection components 220 and 224 are transistors and the operation is controlled by applying voltages to the transistor gates, where the voltage magnitude is greater than the threshold voltage of the transistors. Word line WL-CB ma activate selection component 220 and word line WL-CT may activate selection component 224. For example, a voltage applied to word line WL-CB is applied to the transistor gate of selection component 220 and a voltage applied to word line WL-CT is applied to the transistor gate of selection component 224. As a result, the respective capacitor 205 is coupled to digit lines BL-CB and BL-CT, respectively. The memor cell 105 may he considered in storage mode when both word lines WL-CB and WL-CT are deactivated. The memory cell 105 may also be- considered in storage mode when both word lines WL-CB and WL-C are activated and the voltages of the digit lines BL-CB and. BL- CT are the same.

j Word Maes WL-CB(0)-WL-CB(s) and WL-CT(0)-WL-CT(n) are in electronic communication with selection components 220 and. 224 of memory cells 105 MC(0)~ MC(u). respectively. Thus, activating word. lines WL-CB. and WL-CT of a respective memor cell 105 ma activate the memor cell 105. For example, activating WL~ CB(0) and WL-CT(0) activate memory* cell MC(0), activating WL-CB(l) and-WL- CT(I). activates memory ceil M ' C(l), and so on. In some examples, the positions of selection components 220 and 2:24 may ' be switched, such that selection component 220 is coupled between, digit fine BL-CT and cell top 230, and. the selection component 224 is coupled etween digit Hue BL-CB an cell bottom 215,

Due to die ferroelectric material between the plates of capacitor 205, and as discussed in more detail below, capacitor 205 may not discharge upon coupling to digit lines BL-CB and BL-CT. To sense the-logic state stored by ferroelectric capacitor 205, word lines WL-CB an WL-CT m y be biased to select a respective me ry ceil 105, and a voltage may be applied to the digit line BL-CT, for example, by driver -circuit 237. The digit line BL-CT bias may be applied before or after activating selection component -224-. Biasing- -the digit Mae BL-CT may result in a voltage difference across capacitor 205, which may yield a change in the stored charge on capacitor 205. Likewise, biasing the digit line BL-CB may also result in a voltage difference across capacitor 205, which may yield a change in the stored charge on capacitor 205. The magnitude of the change in stored charge may depend on the initial state of each capacitor 205— e.g., whether the initial state stored a logic 1 or -a logic 0. When the selection component 22 is activated by the word line WL-CB, the change in stored charge due to biasing the digit line BL-CT may ea»se a change in the voltage of digit line BL-CB based on the charge stored on capacitor 205. Similarly, when the selection component 224 is activated by tire word line WL-CT, the change in stored charge due to biasing the digit line BL-CB may cause a change in the voltage of digit line BL-CT based on the charge stored on capacitor 205. The change in the voltage of digit hues BL-CB or BL-CT may cause a change on sense nodes A and B when the isolation switch 231 and switch 235 are activated, all respectively. The resulting "voltage of digit line BL-CB or digit line BL-CT may be compared to- a reference voltage by the sense component 125 in order to determine the logic value represented by the stored state: of each memory cell 105. In some embodiments, the resulting voltage of digit line BL- CB or digit line BL-CT may be compared by the sense component 125 to a reference voltage that is a constant voltage, for example, a V. EP voltage of the VBLREF signal, hi other emhodirnesits, the resulting voltage of digit line BL-CB or digit line BL-CT may be compared by the sense- component 125 to a reference voltage that is self- provided,, for example, a reference ' voltage that results ftom biasing of the digit lines BL-CB and BL-CT during an access operation.

j Sense component 125 may include various transistors or ampUfiers to detect md amplify a difference in signals, which ma including latching the amplified difference. Sense component 125 may include a sense amplifier that receives and compares the voltage of either of sis sense nodes (e.g.. sense nodes A or B) and the voltage of ' the reference signal VBLREF, which may be a reference voltage. In some emb diments, the, voltage o either of the sense nodes may be compared to a self- provided reference voltage. The voltages of the sense nodes A and B may be affected by the voltages of the digit lines BL-CB and BL-CT, respectively, for example, when the sense node A is coupled, to tie digit line BL~GB and when the sense node 8 is coupled to the digit line BL-CT, The sense .amplifier output (e.g., sense node) may be driven to the higher (e.g., a positive) or lower (e.g., negative or ground) supply voltage based on -the comparison and the other sense- ode ' may- be ' riven to the complementary voltage (e.g., the positive supply voltage is complementary to the negative or ground voltage, and the negative or ground voltage is complementary to the positive supply voltage). For instance, if the sense node B has a higher voltage than .reference signal VBLREF or .& higher voltage than a self-provided reference voltage, then the sense amplifier may drive the sense node . to a positive supply voltage and drive the sense node A to a negati ve or ground voltage. Sense component 125 may latch the stat e of the sense amplifier (e.g., voltages of sense node A and/or sense node B and/or the voltages of digit fines BL-CB and/or BL-CT), which may be used to determine the stored state and logic value of memory cell 105, e.g., logic 1. Alternatively, if the sense node B has a lower voltage than reference signal VBLREF or lower voltage than, a self-provided reference voltage, the sense amplifier may drive the sense node B to a negative or ground voltage and drive the sense node A to a positive supply voltage. Sense component 125 may also latch the sense amplifier state for determining the stored state and the logic value of memory eel! 105, e.g., logic 0. The stored state may represent a logic value of memory cell 1.05, which may then be output, for example, through column decoder 130 as output 135 with reference to Figure L in embodiments where the sense component 125 also drives the digit lines BL-CB and BL-CT to complementary voltages, the complementary "voltages ma be applied to the memory cell 105 to restore the original data state read- By restoring the 'data, & separate restore operation is inHteeesssry,

[035] As -previously described, the word oes WL-CB and WL-CT and the selection components 220 and 224 provide independent control of ceil bottom 2 ! 5 and cell bottom 230 of the capacitor 205,. thus, removing the need for a shared cell plate, as is typical with conventional .ferroelectric memories. As a result, the cells may he less susceptible to disturb mechanisms, for example, ceil plate related pattern noise. . Additionally,, cell plate driver circuits * which are needed for shared cell plate designs, are not needed which can reduce circui t size. The digit lines of the plurality of columns of memory cells may be dri en to voltages independently of one another. For example, the digit line BL-CT (the digit line .coupled -through a selection component to the eel! to , which is opposite of the cell bottom) of a first column of memory cells may be drives to a voltage independently of the voltage to which, the digit line BL-CT of a second colu : of memory cells are driven,

| 36| Figure 2B illustrates a sense component 125 according to an embodiment of the disclosure. The sense component 125 includes p-type field effect transistors 252 and 256 and ti-type field effect transistors ' 262 and 266. Gates of the transistor 252 and transistor 262 are coupled to sense node A. Gates of the transistor 256 and transistor 266 are coupled .to sense node B. The transistors 252 and 256, and. the transistors 262 and 266 represent a sense amplifier. A p-type field effect transistor 258 is configured to be coupled to a power suppl (e.g., VREAD voltage power supply) and is coupled to a common- node of the transistors 252 and 256. The transistor 258 is activate by an active PSA signal (e.g., active low logic). An n.~type field effect transistor 268 is configured to be coupled to a sense amplifier reference voltage (e.g.,, ground) and is coupled to a common node of the transistors 262 and 266. The transistor 268 Is activated by an active NSA signal (e.g., active high logic). Reference switch 233 coupled to sense node A. is also shown in Figure -2B. A reference signal VBL. EF is provided to the reference switch 233. Activation of the reference switch 233 is controlled by a signal iSG&EF. As previously described, in some embodiments, the reference switch 233 is not included in the circuit 200, such as in embodiments where the circuit ' 200 provide on its own reference voltage for determining the logic value stored b a memory cell 105. In such embodiments, providing a separate reference voltage (e.g., the voltage VREF of the VBL EF reference signal) to the sense component 125 is not necessary .

[037] In operation, the sense amplifier is activated by activating the PSA and SA signals to couple the sense amplifier to the voltage of the power supply and the sense amplifier reference voltage. When activated, the sense amplifier compares the voltages of sense nodes A and B, and amplifies a voltage difference by driving the sense nodes A and B to complementary voltage levels (e.g., driving sense node A t VREA and •sense node 8 to ground, or drivin sense node A to ground and sense node B t VREAD). When the sense nodes A and B have bee drive to the complementary voltage levels, the voltages of sense nodes A and B are latched by the sense ampisfier and remain latched un il the sense amplifier is deactivated,

838j With reference to Figure 2A. to write memory ceil 1.0 ' S, a voltage may be applied across capacitor 205, Various methods may be ased. in some examples, selection components 220 and 22.4 may be ' activated through word tines WL-CB and WL-CT, respectively, in order to electrically couple capacitor 205 to digit lines BL-CB and BL~CT. For a ferroelectric capacitor 205, a voltage may he applied across capacitor 205 by controlling the voltage of cell top 230 (through digit line BL-CT) and cell bottom 215 (through digit line BL-CB) to apply a positive or negative voltage across the capacitor 205.

039] In some examples, a restore .operation may be performed after sensing- As .previously discussed, the sense operation may degrade or destroy the originally stored state of the memory eel! 105. After sensing, the state may he written back to the memory cell 1 5. For example, sense component 125 may determine the stored state of memory cell 105 and may then write the same state back, for example, through isolation switch 23! and switch 235,

10 0] ferroelectric materials have non-linear polarization properties. Figure 3 A and Figure 3B illustrate examples of non-linear electrical properties with hysteresis curves 300-a (Figure 3 A) and 300-b (Figure 3B) for a memor cell for ferroelectric memory in accordance with various embodiments, of the present disclosure.. Hysteresis curves 300- a and 300-b illustrate an example ferroelectric memory cell writing and reading process, respectively. Hysteresis curves 300 depict the charge, Q, stored on a ferroelectric capacitor (e.g., capacitor 205 of Figure 2) as a function of a voltage difference, V,

[Θ4Ϊ j A ferroelectric material is characterized by a spontaneous electric polarization, for exam le, it .maintains a non-aero electric polarization in the absence of an electric field. Example ferroelectric materials include barium titanate (BaTi03), lead titanate (PbTi.03), lead zirconium titanate (PZT), and strontium bismuth tantaiate (SBT). The ferroelectric capacitors described herein may include these or other ferroelectric .materials. Electric polarization within a ferroelectric ' capacitor results m a. net charge at the ferroelectric material's surface and attracts opposite charge through the capacitor terminals. Thus, charge is stored at the interface of the ferroelectric material and the capacitor terminals. Because the electric polarization ma be maintained in the absence of an externally applied electric field for relatively long times, even indefinitely , charge leakage may be significantly decreased as compared with, for example, capacitors employed in volatile ' memory arrays. This may reduce the need to perform refresh operations as described above for some volatile memory architectures.

042] Hysteresis curves 300 may be understood from the perspective of a single terminal of a capacitor. By way of example, if the ferroelectric material has a negative polarization, positive charge accumulates at the terminal. Likewise, if the .ferroelectric material has a positive polarization, negative charge accumulates at the terminal. Additionally, it should be understood that the voltages in hysteresis carves 300 represent a voltage .difference across the capacitor and are directional. For example, a positive voltage m y he realized by applying a positive voltage to the te minal in question (e.g., a cell top 230) and maintaining the secon terminal (e.g., a cell bottom 215) at ground (or approximately zero volts (0V)). A negative voltage may be applied by niahitatnhig the terminal in question at ground and applyin a positive voltage to the second terminal, for example, positive voltages may be applied to negatively polarize the terminal in question. Similarly, two positive voltages, two negative voltages, or any combination of positive and negative voltages may be applied to the appropriate capacitor terminals to generate the voltage .difference shown in hysteresis curves 300.

043] As depicted in hysteresis curve 300~a, five ferroelectric material may maintai a positive or negative polarization with a zero voltage difference, resulting in two possible charged states; charge state 305 and charge state 310, According to the 1.4 example- of Figure 3, charge .state 305 represents a logic 0 and charge state 31.0 represents a logic 1. In some examples, the ' logic values of the respective charge states may be reversed without loss of understanding.

|044 A logic 0 or i may be written to the memor ceil by controlling the electric polarization of the ferroelectric, material, and tots the charge on the capacitor terminals, by applying voltage. For example, applying a net positive voltage 315 across the capacitor results in charge accumulation until charge state 305-a is reached. Upon .removing . voltage 315,. charge state 305-3 follows path 320 until it reaches charge state 305 at zero voltage potential. Similarly, charge state 310 is written by applying a net negative voltage 325, which results in charge state 3.10-a. After removing negative voltage 325, charge state 310-a follows path 330 until it reaches charge state 310 at zero voltage. Charge states 305 and 310 ma also be referred t as the remnant polarization (Pr) values, which is the polarization (or charge) that remains upon removing the external bias {e.g., voltage).

|045] To read, or sense, the stored state of the ferroelectric capacitor, a voltage may be applied across the capacitor, in response, the stored eharge, Q, changes, and the degree of the change depends on the ioitiai eharge s tate, and as a result,, the .final stored eharge (Q) depends on whether eharge state 305-b or 31 -b was init ally stored. For example, hysteresis carve 300-b illustrates- two possible stored charge states 305-b and 31 -b. Voltage 335 ma be applied across the capacitor as previously discussed. Although depicted as a positive voltage, voltage 335 may be negati ve, in response to voltage 3:35, charge state ' 305-b may follow path 340. likewise, if charge state 3i0~b was initially stored, then it, follows path 345. The final position of charge state 305-c arid charge state 10-c depend on a number of factors, including the specific sensing scheme and circuitry.

[046] In some cases, the final charge may de end, on the intrinsic- ' capacitance of the digit line coupled to the memory cell For example, if the capacitor is electrically coupled to the digit line and voltage 335 is applied, the voltage of the digit line may rise due to its intrinsic capacitance. So a voltage measured at a sense component may not equal voltage 335 and instead, may depend on the voltage of the digit line. The position of final charge states 305-c and 310-e on hysteresis curve 300~b may thus depend on the capacitance of the digit line and may be determined through a load-line analysts. Charge states 305-c and 3 iO~e may be defined with respect to the digit line capacitance. As a result, ti.se voltage of the capacitor, voltage 350 or voltage 355, may be different and may depend on the initial slate of the capacitor.

047| By eoniparing the digit line voltage to a reference voltage, the initial state- of the capacitor may he determined. The digit Use voltage may he the difference between voltage 335 and the final voltage across the capacitor, voltage 350 or voltage 355 (e.g., voltage 335 - voltage 350} or (e.g., voltage 335 - voltage 355), A reference Voltage may be generated, such that its magnitude is between the. two possible digit line voltages is order to determine the stored logic state, for example, if the digit line voltage is higher or lower than the reference voltage. For example, the reference ■voltage may be an average of the two A antities (voltage 335 - voltage 350) and (voltage 335 - voltage 355). In another example, the reference voltage may be provided by isolating a voltage on first sense node of a sense component, then causing a voltage change on a second sense node of the sense component ' through · a digit line, and comparing- the resulting voltage of the second sense node with the isolated voltage of the first sense node. Upon comparison by the sense component, the sensed digit line voltage may be determined to be higher or lower than the reference voltage, and the stored logic value of the ferroelectric memory cell (e.g., a logic Θ or 1) may be determined.

f048j Figures 4A-4E are timing diagrams o various signals during a read operation according to an embodiment of the disclosure. Figures 4A-4B will be described with reference to memory array 10 and example circuit 200 of ' Figures 1 and 2. The example read operation of Figures 4A.- B m y provide increased voltage margin relative to a reference voltage used to determine the stored state (and the corresponding logic value) of a memory cell.

|049| Prior to time TO the digit line BL-CB is coupled to the sense node A of the sense component .125 through an. .activated isolation switch 231. The switch 235 is deactivated so that the voltage of the digit line BL-CT is and the voltage of the sense node B are independent of one another. The digit line BL-CB and sense node A, and the digit line BL-CT and sense node B are all precharged to a voltage, such as ground. At time TO, the word line W1.-CB is activated to activate the selection component 220 to couple the cell bottom 215 to the digit line BL-CB, At time Tl the driver circuit 23? is: enabled to drive a voltage: VREAD onto the digit line BL-C , The word line WL-CT is acti vated at time T2 to activate the selection componeat 224 to couple, die cell top 230 to the digit Ike BL-CT (Figure 4A).

{058j The voltage V EAD is a plied t the cell top 230 through Ac activated selection component 224 to cause a voltage change at the cell bottom 215. As previously discussed, die magnitude of the change in voltage caused at the cell bottom 215 is based at least in part on the charge state mit&Uy stored by tlie capacitor 205. The voltage change at the eel! bottom. 215 from an initial voltage to. aa increased voltage also causes the voltage of the digit line BL-CB and the sense node A to change as well. Where the initial, charge state represents a logic 1, the sense node A (SENSBA-J in Figure 4C) and the digit line BL-CB (BL-CB- ί in Figure 4B) change from ground (e.g., the initial voltage) to a first voltage (e.g., the increased voltage) (Figure 4C). Where die initial charge state represents a logic 0 $ . the sense node A (SENSEA-0 in Figure 4E) and the digit line BL-CB (BL-CB-0 in Figure 4B) change from ground (e.g., the initial voltage) to a second voltage (e.g., the increased voltage). In the example shown in Figures 4A- E, the first voltage is greater than the second voltage.

[051] The switch 235 is still not active at time T2, and thus, the digit line BL-CT and sense node B are not coupled through an active switch 235.. Nonetheless, , ' coupling the voltage VREAD at time T2 to the cell top 230 through the digit line BL-CT and the activated selection compoaent 224 also causes the voltage of sense node B to change. Where the initial charge state represents a logic 1, the sense node B ( SENSES- 1 in Figure 4C) changes from ground to a third, -voltage. Where the initial . charge state represents a logic 0, the sense node B (SENSEB-0 in Figure 4D) changes from ground to a fourth voltage, in the example shown ia Figure 4, the third voltage is greater than the fourth. voltage, and both the thM and fourth voltages are less thas the second voltage. The voltages of sense node A, sense node B, and the digit line BL-CB develop between time T2 and T3,

|052j At time- T3 the isolation switch 231 is deactivated so that the sense node A is isolated from the digit line BL-CB (Figure 5A.) and the switch 235 is activated by the signal RESTORE to conduct voltage between the sense node B and the digit line BL- CT. The reference switch 233 is thea activated to provide a voltage VREF of a reference signal VBLREF to the sense node A, " The voltage VR ' EF of the reference signal VBLREF is a constant (e.g., fixed) voltage. As a result, the voltage of sense node A changes from the first or second voltage to the voltage VREF by the reference signal VBLREF (figures 4C and 4E). The sense node B is coupled to tlie digit line BL-CT through the activated switch 235, which causes the voltage of sense node B to change from, the third or fourth voltage to the voltage VREAD, which is the voltage of the digit line BL-CT (Figures C and 4Έ.}.

eS3j The driver circuit 239 is enabled at time T4 to drive the digit line. BL-CB to ground, which causes the cell bottom 21.5 to also change to ground. The voltage of the digit line BL-CB may change from the first voltage (due to the initial charge state of the capacitor 205 corresponding to logic 1} to ground. (Figure 4B), or from the second voltage (due to the initial charge state of the capacitor 205 corresponding to logic 0) to ground (Figure 40). The change in voltage from the first voltage to ground is greater than the change in. voltage from the second voltage to ground.

054] The change in voltage of the cell bottom 215 due to the digit line BL-CB bein driven to ground is coupled across the capacitor 205 to cause a change in voltage of the cell top 230. With the sense node B coupled to the cell top 230 through activated selection component: 224, digit line BL-CT, and activated switch 235, the change in voltage causes the voltage of the sense node B to change as well.. The change in voltage of sense node B will depend on the change in voltage of the digit line BL-CB. For example, where the change hi voltage of the digit line BL-CB is ftoM the first voltage to ground, the voltage of sense node B changes from the VREAO voltage, to a fifth voltage (Figure 4C) that is less than the voltage VREF of the VBLREF signal applied to sense node A. Where the change in voltage of the digit line BL-CB is from the second voltage to ground, tlie voltage of sense node B changes from tlie VREAD voltage to a sixth voltage (SENSEB-0) that is greater than the voltage VREF of the VBLREF signal applied to sense node A.

055} Prior to tiuie T5 the switch 235 is deactivated by the signal RESTORE to isolate the sense node B from the digit line BL-CT. At time TS the sense component .125 is activated and the isolation switch 231 is activated to couple the sense node A. to the digit line BL-CB. Also at time TS, or shortl thereafter, the switch 235 is activated: to couple the sense node B to the digit line BL-CT. With the sense component 2 activated, a voltage difference between the sense node A and sense node B is detected and amplified to drive the sense nodes to complementary voltages (e.g., VREAD and ground). The digit lines BL-CB and BL-CT re likewise driven to complementary voltages by the sense component 125 through the activated isolation switch 231 and the activated switch 235. For example, where the voltage of sense node B is less than the voltage VREF of sense node A (e.g., sense node B at the fifth voltage -(SENSEB-l in Figure- 4Q the activated seme component 125 drives the sense node B (and digit line BL-CT) to groun and the sense node A (and digit line BL-CB) to voltage VREAD. In contrast, where the voltage of sense node B is greater than the VREF voltage of sense node A (e.g., sense node B a the sixth voltage (SENSEB-0 in Figure 4E)), the activated sense component 125 drives the sense node B (and digit line BL-CT) to voltage VREAD and the sense node A (and digit line BL-CB) to ground Figure 4E. The voltages of the sense node A and sense node B are latched by the sense component 125 after being driven to complementary voltages. The latched voltages of the sense nodes A and 8 represent a corresponding logic value, which may be output, for example, through column decoder 130 as output 1.35 (Figure .1).

[056] Also at time TS or after time T5 the isolation switch 23 ! is activated to couple the sense node A to the digi line BL-CB (Figure A). Sense node B is coupled to the digit line BL-CT through the activated switch 235. As a result, the driving of the sense nodes A and B to complementary voltages by the sense component 125 also drives the digit lines BL-CB and BL-CT to the corresponding complementar voltages. Similarly, the: driving, of the digit lines BL-CB; and BL-CT also drives the cell bottom 215 and eel! top 230 to the complementary voltages .

[057] For example, dri ving the sense node B to ground and the sense node A to the voltage "VREAD (Figure 4G) also drives the digit line -BL-CT and cell top 230 to ground and drives the digit line BL-CB and cell bottom 215 to the voltage VREAD (Figure 4B). Driving the sense node B to voltage VREAD and the sense node A to ground (Figure 4E) also drives the digit line BL-CT and the cell top 230 to voltage VREAD and drives the digit line BL-CB and the ceil bottom 215 to ground (figure 4D). Driving the complementary voltages to the cell to 230 and the cell bottom 2.15 ensures that the read operation does not change or degrade the original charge state of the capacitor 205 by restoring the original charge state of the capacitor 205. ] The sense component 125 is deactivated at time T6 and the voltages of sense nodes A and B, and digit lines BL-CB and BL-CT are driven to ground. The word lines WL-CB and WL-CT are deactivated at time T? (Figure 4A) to deactivate the selection components 220 and 224 to isolate the capacitor 205 from the digit lines BL- CB and BL-CT, all respectively, to complete she read operation.

] Figures 5A-5E are timing diagrams of various signals during a read operation according to an embodiment of the disclosure. Figures 5A-5E will be described with reference to memory array .100 and example circuit 200 of Figures ! and 2. As will be described in more detail below, the read operation of Figures 5A-5E relies on self- provided reference voltage for determining the logic value stored by a memory cell. Thus, a separate reference voltage for this ptnpose is not needed in the example read operation of Figures 5A-5E, which may reduce circuit complexity and improve circuit density. For example, self-provided (e.g., locally created) reference voltages may allow for eliminating two transistors from the sense component, and ma allow for eliminating reference amps and a reference distribution network. Additionally, self- provided reference voltages may be beneficial because ferroelectric memory cells are subject to cycling, imprinting and sensitivit of temperature ' variations affecting a sense window relative to a constant reference voltage.

] Prior to time TO the digit line BL-CB is coupled to the sense node A of. the sense component 125 through an active isolation switch 231. The digit tine BL-CB and sense node A, and the digit line BL-CT and sense node B are all precharged to a reference voltage, such, as ground. At lime T6, the word line WL-CB is activated to activate the selection, component 220 to couple the digit line BL-CB to the cell bottom 215. At time Tl tile driver circuit 237 is enabled to drive a voltage VREAD onto the digit line BL-CT. The word line WL-CT is activated at time T2 to activate the selection component 224 to couple the digit line BL-CT to the. cell top 230 (Figure 5A).) The voltage VREAD is applied to the cell top 230 through the activated selection component 224 to cause a voltage change, a! the cell bottom. 215. As previously discussed, the .magnitude of the change in voltage caused at the cell bottom 215 is based at least in part on the charge state initially stored by the capacitor 205. The voltage change at the ceil bottom 215 also causes the voltage of the digit line BL- CB and the sense node A to change as well. Where fee initial charge state represents a logic 1 , the .sense node: A (SENSE A- 1 in Figure SC) and the digit line BL-CB (BL-CB- I in Figure SB) change from ground to a first -voltage. Where the initial charge state represents a logic (X the sense node A (SBN5EA-0 is Figure 5E) aad the digit line BL- CB BL-CB-0 in. Figure 5D) change from . round, to a second voltage. In the example shown, in Figures 5B-5E, the first voltage is greater than the second voitage.

) The switch 235 is still not active at time T2 > and thus, the digit line BL-C and sense node B are not coupled through an active switch 235. Nonetheless, coupling the voitage VREAD at time T2 to the cell to 230 through the digit line BL-CT d the activated selection component 224 also causes the voltage of sense node B to change. Where the initial charge state represents a logic I, the sense node B (SENSES- 1 in Figure 5C) changes f om ground to a third voltage. Where the initial charge state represents a logic 0. the sense node B (SENSEB-G hi Figure 5D) changes from ground to a fourth voltage, hi the example shown in Figure 5, the third voltage is greater than the fourth, voltage, and both the third and fourth voltages are less than the second voltage. The voltages of sense node A, sense node B, and the digit line BL-CB develop between time T2 and T3.

! t time T3 the isolation switch 231 is deactivated so that the sense node A is isolated ίϊοοΐ the digit line BL-CB in Figure 5A and the switch 235 is activated by the signal RESTORE to conduct voitage between the sense node B and the digit line BL- CT. As a result, the voltage of sense node A may change without changing the voltage of digit line BL-CB, and vice versa * Wit the switch 235 activated to couple the sense node B to the digit tine BL-CT * the voltage of sense node B changes frorn the third or fourth voltage to the voitage V.RE.AD, which is the voltage of the digit line BL-CT (Figures 5C and 5E). Wit the isolation switch 231 deactivated, the digit line BL-CB remains at the first or second voitage and the sense node A increases relative to die first or second voltages (Figure 5C and 5E),

) The driver circuit 239 is enabled at time T4 to drive the digit line BL-CB to ground, which causes the cell ' bottom 215 to also change to ground. The voltage of the digit line BL-CB may change from the firs voltage (due to the initial charge state of the capacitor 205 corresponding to logic 1} to ground (Figure SB), or from the second voltage (due to ihe initial charge state of the capacitor 205 corresponding to logic 0) to ground (Figure 5D). The change in voltage from the first voltage to groun is greater than the change in voltage from the second voltage t ground. The change in voltage of the digit line BL-CB also causes the voltage of the sense node A to change. Where the sense node is at a voltage increased relative to the first voltage, the voltage of sense node A. (S.ENSEA-.I in Figure 5C) changes to a fifth voltage doe to the digit line BL- CB being driven to ground. Where the sense node A is at a voltage increased relative to the second voltage, the voltage of sense node A (SENSEA-0 is Figure 5 E) changes to a sixth voltage due to the digit line BL-CB being driven to ground.

} The change in voltage of the ceil ' bottom 215 due. to the digit line BL-CB being driven to ground is coupled across the capacitor 205 to cause a change in voltage of the cell top 230. With the sense node B coupled to the cell to 230 through activated selection component 224, digit Sine BL-CT, and activated switch 235, the change in voltage causes the voltage of the sense node B to change as well. The change in voltage of sense node B will depend on the change in voltage of die digit line BL-CB. For example, where the change in voltage of the digit line BL-CB is from the first- voltage to gr und, the voltage of -sense node B changes from the VREAD voltage to a seventh voltage (SENSBB-1. in .Figure 5C-) thai is less than the fift voltage of the sense node A (SENSEA--I is Figure SC). Where the change in voltage of the digit .line BL- CB is from the second voltage to ground, .the voltage of sense node B changes from the VREAD voltage -to an eighth voltage · (SENSEB-0 in Figure 5E) that is greater tha the sixth voltage of the sense node A (SENSEA-0 in Figure SB).

] Prior to time T5 the switch 235 is deactivate by the signal RESTORE to isolate the sense node B from the digit line BL-CT.■ At time T5 the sense component 125 is activated, and a. voltage difference between the sense node A and sense node B is detected and amplified to drive tire sense nodes to complementary ' voltages (e.g., VREAD and ground) ' . The voltage at the sense node A .represents a reference voltage against which the voltage at the sense node B -is compared. The reference voltage at- sense node A is self-provided, and is based on the voltage of the cell bottom 2.15 resulting from driving the voltage VREAD to die cell to 230 over the digit line BL-CT at time. Tl . Where the voltage of sense node B is less than the voltage of sense node A (e,g., sense node B at the seventh, voltage (SENSEB-! in Figure 5C) and sense node A at the fifth voltage (SEMSEA-I in Figure 5C)), the activated sense -component 125 drives d¾e sense node B to ground and the sense node A to voltage VREAD, in 77 contrast, where the voltage of sense node B is greater than the voltage of sense node A (e g., sense node B at the eighth voltage SENSEB-0 in Figure 5E) and sense node A at the sixth voltage (SENSEA-0 ia. ' Figuie 5EJ), Itie activated sense- component S25 drives the seo.se node B to voltage VREA.D and the sense node A to ground. The voltages of the sense node A and sense node B are latched by the sense component .125 after being driven to complementary voltages. The latched voltages of the sense trades A and B .represent a correspondiftg logic value, which may be output, for example, through column decoder 130 as output 135 (figure I).

[067] Also at time T5 or after time T5 the isolation switch 231 is activated to couple the sesise node A to the digit line BL-CB and the switch 235 i activated to couple the sense node B to the digit line BL-C (Figure 5A). Sense node B is coupled to the digit line BL-CT through the activated switch 235. As a result, the driving of the sense nodes A and B to eornplementary voltages b the sense component 125 also, drives the digit Uses BL-CB and BL-CT to the corresponding complementary voltages. Similarly, the driving of the digit lines BL-CB and. BL-CT also drives the cell bottom 215 and cell top 2 0 to the complementary voltages.

[868] For example, dri ving the sense node B to ground and the sense node A to the voltage VREA.D (Figure 5C) also drives the digit line BL-CT and cell top 230 to ground and doves the digit line BL-CB and ceil bottom 215 to the voltage VREAD (Figure 58), Driving the sense node B to voltage VREAD and the sense node A to ground (Figure E) also drives the digit line BL-CT and the cell top 230 to voltage VREAD ' .and drives the digit line BL-CB and the cell bottom 215 to ground ' (figure . 5D), Driving the complementary voltages to the ceil top 230 and the ceil bottom 215 ensures that the read operation does not change Or degrade the original charge state of the capaci tor 205 by restoring the original charge state of the capacitor 205.

[969] The sense component 12.5 is deactivated at time T6. and the voltages of sense nodes A and B, and digit lines BL-CB and BL-CT are driven to ground. The word lines WL-CB and WL-CT are deactivated at time T7 (Figure 5A) to deactivate the selection components 220 and 224 to isolate die capacitor 2:05 from the digit, lines BL- CB and BL-CT. all respectively, to complete the read operation. ø?0) Embodiments of read operations disclosed, for example, the read operations described with reference to Figures 4A-4E and 5A-5E, may increase a sense window for reading ferroelectric Memory cells, and avoids spending additional power to bump a capacitor plate to a higher voltage during, the read operation, in contrast:, power spent on initially driving a capacitor plate (e.g., to die VREAD voltage), may be recycled, to increase the sense window.

071) Figure 6 is a timing diagram of various signals during a write operation 'according to an embodiment of the disclosure. Figure 6 will be described iftt reference to memory array .100 and example circuit 200 of Figures .1 and 2. In die example write operation of Figure 6 a logic <s 0" is written to a memory cell .1 5 that currently stores a logic "i".

072) Prior to lime TA, the word lines WL-CB and WL-CT are activated to activate selection components 220 and 224, respectively. As a result, the digit line BL-CB is coupled to cell bottom 23.5 arid the digit Sine BL-CT is coupled to cell top 230 of the capacitor 205. The voltage of the digit line BL-CB is at the VREAD voltage representing the currently stored logic "I" and the voltage of the digit line BL-CT is at a reference voltage, for example, ground. Also prior to time TA, the digit line BL-CB is coupled to sense node A of die sense component 125 through activated isolation switch. 231., and the digit line BL-CT is coupled to sense node B of the sense component 125 t rough activated switch 235. Thus, prior to time TA, the sense nodes A and B are coupled to cell bottom 21 and cell top 230, respectively,

073) At time A, write ' amplifier (not shown) coupled to sense nodes A and 8 drives the sense node A from the VREAD voltage to groun and drives sense node B from ground to the VREAD voltage. The voltages of sense nodes A and B are latched by the sense component 125. With the sense nodes A and B driven by the write amplifier, the voltage of the digit line BL-CB changes to ground and the voltage of the digit line BL-CT changes to the VREAD voltage. The ground voltage of the sense node A and the digit line BL-CB represents the logic "0" written to the capacitor 205. The ground voltage of the digit line BL-CB and the VREAD voltage of the digit line BL-CT are applied to the ceil bottom 215 and to the cell top 230 through the activated selection components 220 and 224, all respectively. As a result, the capacitor 205 becomes polarized in an opposite polarization to change the stored state data ' from representing a logic "I" to a logic. "0".

[074] By ' time TB the voltages at the sense nodes A and B have been latched by the sense c mpon nt 125 and the voltages of the sense nodes and B are no longer driven by the write amplifier. The sense component 125 is deactivated at time TB and the voltage of the sense node B (and the digit line BL-CT) changes to ground. With both eel! to 23 and the cell bott m 215 at the same voltage, the word lines WL-CB arid WL-CT ar deactivated, at time TC to complete the write operation.

075 Figure 7 is a timing diagram of various signals during a write operation according to an embodiment of the disclosure. Figure 7 will be described wit reference to memory -array 100 and example circuit 200 of Figures I and 2. In the example write operation of Figure 7 a logic "1" is written to a memory cell 105 that currentl stores a logic "CP.

076] Prior to time TA, the word lines WL-CB and WL-CT are -activated to activate

selection components 220 and 224, respectively. As a result, the digit line BL-CB is coupled to ceil bottom 21.5 and the digit line B L-CT is coupled to ceil top 230 of the •capacitor 205. The voltage of the digit line BL-CB is at ground representing the •currently stored logic "0" and the voltage of the digit line BL-CT is at the VREAD voltage. Also prior to time TA : , the digit hoe BL-CB is coupled to sense node A of flic sense component. 125 through activated isolation switch 231, mid the digit line BL-CT is coupled to sense node B of the sense component 125 through activated switch 235. 'Thus, prior to time TA, the sense nodes A and B are coupled to ceil bottom 215 and cell top 230, respecti ely,

[077] At time TA, a write amplifier (not shown) coupled to sense nodes A and B drives the sense node A from ground to the VREAD voltage and drives sense node B from the VREAD voltage to ground. The - voltages of sense nodes A and B are latched by the sense component 125. With the sense nodes A and B driven by the write amplifier, the voltage of the digit line BL-CB changes to the. VREAD voltage and the voltage of the digit line BL-CT changes ground. The VREAD voltage of the sense node A and the digit line BL-CB represents the logic ' ' written to the capacitor 205. The VREAD voltage of the digit line BL-CB and the ground voltage of the digit line BL-CT are applied to the cell bottom 215 and to the cell top 230 through the activated selection components 220 and 224, all respectively. As a result, the capacitor 205 becomes pol rized in an opposite polarization to change the stored state from representing a logic "0" to a logic "1".

|Θ78 By time TB the voltages at the sense nodes A and B .have been latched by the sense component 125 and the voltages of the sense nodes A and B are no longer driven by ihe write amplifier. The sense component 125 is deactivated at time TB and the voltage of the sense node B (and the digit: line BL-CT) changes to ground. With both cell top 23 and the cell bottom 215 at the same voltage, the word lines WL~€B and WL-CT are deacti vated at time TC to complete the write operation.

079| In some embodiments; the write operations described with reference to Figures

6 and 7 may be performed in conjunction with a read operation, for example* read operations described with reference to Figures 4A-4E and 5A-5E, For example., with reference to the example read operation of Figures 4A.-4E and 5A-5.E, the example write operation of Figure .6 ma be performed following the sense component · 125 driving the sense nodes A and B, digit lines BL-CB and BL-CT, and cell bottom 215 .and cell top 230 to complementary voltages (e.g., following time T5 of Figures 4A-4E and 5A-5E) and when the memory ceil 105 stores a logic 1 (e.g., BL-CB and cell bottom 215 at the voltage VREAD aad BL-CT aad cell top 2:30 at ground). la another example, with ..reference to the example read operation of Figures 4A-4E and 5A-5E, the example write operation of Figure 7 may be performed following the sense component 125 driving the sense nodes A and B, digit Sines BL-CB and BL-CT, and cell bottom 215 aad eel! top 230 to complementary voltages (e.g., following time; T5) and when the -memory cell 105 stores a logic 0 (e.g., BL-CB aad cell bottom 215 at ground and BL-CT and cell top 230 at the VREAD voltage). The example- write operations of Figures 6 aad 7 niay be performed in conjunction with, different operations in other embodiments.

080) As previously described with reference to Figures 4 and 5, logic "1" is represented by a voltage on the cell bottom greater than the reference voltage (e.g., the VREF voltage of the reference signal VBL EP, self-provided reference voltage, etc.) and -a logic "0" is represented by a voltage on the eel! bottom less than the reference voltage. As also previously described with reference to the example write operations of Figures 6 and ? a logic "1" is- written by applying the VREAD voltage to the cell bottom and ground to the cell top, and a logic "0" is written by applying groun to die celt bottom arid the VREAD voltage to the cell top, in some examples, die logic values corfespooding to the voltages relative to the reference voltage, and the application of the net positive/negative voltages for writin the logic values may be reversed without departing from the scope of the disclosure.

881] The example voltages and signal timing described with reference to the read and write operations of Figures 4-7 have been provided fo illustrative purposes, and are not intended to limit the scope of the present disclosure. It will be appreciated: that the voltages and relative signal timing may be modified without departing from the scope of the present disclosure.

082] Figure 8 illustrates a portion, of a memory array 100 including an example embodiment of .memo y ceils 105 according to the disclosure.

083j The illustrated region of memory array 100 includes digit lines BL-CT and BL- CB, The digit hues BL-CT and BL-CB are vertically offset relative to another and may be connected to a sense component 125, A pair of adjacent memory cells 105 are shown, with such adjacent memory cells being in a common column as one another within the .memory array (e.g., being alon a common column represented by digit lines BL-CT and BL-CS). msulative material 48 is shown to surround the various • components ' of memory · cells ' 105. In some embodiments the memory cells 105 may ' be referred to as substantially identical memory-' ceils along a column of a memory array, with the term "substantially identical" meaning that the memory cells are identical to one another within reasonable tolerances of fabrication and measurement,

084] The digit line BL-CB is shown to be ove and supported by a base 15. Such base may be a semiconductor material. The memory cells 105 each includes ' selection components 220 and 224 and a ferroelectric capacitor 205. The capacitor 205 is vertically betwee the selection component 220 and 224 o memory cell 105. The capacitor 205 includes a first plate, cell top 230, and a second plate, ceil bottom 215, and a ferroelectric .material 232 disposed between the celi top 230 and the cell bottom 215. Although -the cell top 230 is shown to be container-shaped and the cel.! bottom 215 is shown to extend within such container shape, in other embodiments the cell top a d bottom may have other configurations. For instance, the cell top and bottom may have planar configurations-. Pillar 212 extends from digit line BL-CT to the ceil top 230 of capacitor 205, and the pillar 202 extends from the digit title BL-CB to the ceil bottom 215 of capacitor 205.

[085] The selection component 224 has soiuee/drain region 214 extending to the cell top 230 of capacitor 205, and has source/drain region 216 extending to the digit line BL-CT. The selection component 224 also has channel region 218 between the source/drain regions 214 and 216. Gate 211 is along the channel region 218 and offset f om the channel regions by gate dielectric material 213. The. gate 21 1 may be included in a word line WL-CT.

[086] The selection component 220 has source/drain region 204 extending to the cell bottom 215 of capaci tor 205, and has source/drain region 206 extending to the digit liae BL-CB, The selection component 220 also has channel region 208 between the source/drain regions 204 and 206. Gate 201 is along the channel region 208 and offset from the channel regions by gate dielectric material 203. The gate 201 may be included in a wo d lien WL-C-B,

[087] As shown in the embodiment of Figure 8, the selection components 220 and 224 and capacitor 205 of the memory cell 105 are vertically stacked, which may enable memory cells 105 to be packed to high levels of integration,

[088] In some embodiments, the relative orientations o f digit lines BL-CT and BL-CB are reversed so that the digit line -BL-CT is over a supporting substrate 1.5 and the digit line BL-CB is over the digit line BL-CT. In. such other embodiments the illustrated capacitors 205 would be inverted relative to the shown, configuration of Figure 8 and accordingly container shaped cell tops 230 would open upwardly instead of downwardly.

[089] Figure 9 illustrates a block diagram of a portion, of memory 900 that includes memory array 100 that supports a ferroelectric memory in accordance with various 'embodiments of the present ' disclosure. Memory array 100 may be referred to as an electronic memory apparatus a d includes memory controller 140 and memory cell 105, which may be examples of memory controller 140 and memory cell 105 described with reference to figures 1 , % or 4-7.

[Θ99] Memory controller 140 may include biasing component 905 and timing component 910, and may operate memory array 100 as described in Figrjre 1. Memory controller 140 may be in electronic communication with word lines 11 , digi t lines 1 5, and sense ' mponent 125, which may be examples of word fine 110, digit line 115, and sense component 125 described with reference to Figures 1, 2, or 4-7. Memory controller 140 may also be in electronic corom nication with reference switch 233, isolation switch 231, and switch 235,, which may be -examples of the reference switch 233, isolation switch 231 , and switch 235, respectively, described with reference to Figures 2 or 4-7. In some embodiments, for example, embodiments using a constant reference voltage, the memory controller 140 may provide .a reference signal VBLREF to the sense component 125 through the reference switch 233. The components of memory array 100 may be in electronic communication with each other and may perform the functions described with reference to Figures 1-?.

Memory controller 140 may be configured to. activate word lines 1 10 or digit lines 1 15 by applying voltages to the word and digit lines.. For example., biasing component 905 may be configured to apply a voltage to operate memory ceil. 105 to read or- -write -memory cell 105 as described above, in some- eases, memory controller 140 may include a. row decoder, column decoder, or both, as described with reference to Figure 1. This may enable memory controller .14 to access one or more memory cells 105, Biasing component: 905 may also provide a reference signal VBLREF to sense component 125 in some embodiments. Additionally, biasing component 905 may provide voltage potentials for the operation of sense component 125. The biasing component 905 may include, for example, the driver circuit 237 configured to provide the read voltage VREAD when activated, and/or the driver circuit 239 configured to drive the digit line BL-CB · to .ground, when ctivated.

Memory controller .140 may activate isolation switch 231 based on receiving the access operation request- for the ferroelectric memory cell 105 that is, memory controller 140 may electrically connect memory cell 105 to sense component 125. Memory controller 1.40 may further determine a : logic state of the ferroelectric memory ceil 105 based on activating sense component 125, and write the logic state of the ferroelectric memory cell .105 back to the ferroelectric memor cell 105.

In some eases, memory controller 140 may perform its operations usin -timing component 910. For example, timing component 910 may control the timing of the various word line selections or cell top biasing, including timing for switching and voltage appi.sca.iion to perform, the- memory functions, such as reading and writing. discussed herein, la some cases, timing component 1 may control the operations of biasing com onent 905. For example, the memor controller 140 may control the biasing component 905 t provide a read voltage VREAD to the digit Sine BL-CT to change the -voltage of the memor cell, the digit hoe BL-CB, and sense node A of sense component 125, The memory controller 1 0 may then control the biasing component 905 to drive the digit line BL-CB to ground to change the voltage of the memory cell, tlie digit line BL-CT, and sense node 8. Following the digit Sine BL-CB being driven to ground, the memory controller 140 m control the sensing component 125 to compare the voltage of sense node B to the voltage of sense node A, which is at a self- provided reference voltage.

I Sense component 125 ma compare a signal ftom memory cell 1 5 (through digit line 1 15} with a reference voltage. As previously discussed, in some embodiments the reference voltage may he the voltage of a reference signal VBLREF. The reference signal VBLREF may have a voltage with a value between tlie two sense voltages, as described with reference to Figures 2, 4, and 5, In other embodiments,, the reference voltage may be self-provided, for example, using as a reference voltage the voltage of a sense node resulting from biasing a memory cell 105. Upon determining and amplifying the voltage difference* the sense component 125 may latch the state, where it may be used in accordance with the operations of an electronic device that memory array 100 is a part,

j Figure 10 illustrates a system 1000 that supports a ferroelectric memory in accordance, with various enibodiments of the present disclosure. System 1(300 Includes a device 1005, which may be or include, a printed circuit board to connect or physically support various components. Device 1 05 may be a computer, notebook computer, laptop, tablet computer, mobile phone, or the like. Device 1005 includes a memory arra 100, which, may be an example of memory array 100 as described with reference to Figures 1 and 9. Memory arra 100 may contain, memory controller 140 and memory eeil(s) 1 5, which may be examples of memor controller 140 described wi th reference to Figures :1 and 9 and .memory cells 105 described with reference to FIG. .1 , 2, and 4-9. Device 1005 may also include a processor 1010, BIOS component 1015, peripheral componentfs) 1020, and input%uipBt control component 1025. The components of device 1005 may be In electronic communication with one another through bus 1030.

[096 Processor 1010 ma be configured o operate memory array 100 through memory controller 140. In some cases,, processor 1.010 may perform the functions of memory controller 140 described with reference to Figures 1 and 9. In other eases, memory controller .140 ma be Integrated into processor 10.10. Processor .1010 ma be a general-purpose- .processor, a digital signal processor (DSP), an application-specific integrated circuit (AS C), a f¼!d-prog amma ' b!e gate arra (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware componeHts. or it may be a combination of these tvpes of components.- The processor 1010 may perform, various functions and -operate the memory array 100 as described herein. Processor 1010 may, for example, be configured to execute computer-readable instructions stored in memor array 100 to cause device 1.005. perform, various functions or tasks,

097] BIOS component 1015 may be a software component that includes a basic input/output system (BIOS) operated as firmware, which may initialize and run various hardware components of system 1000. BIOS component 1015 may also manage data flow between processo 1016.and the various components^ e.g., peripheral components 1020, input/output control component 1 25, etc. B OS component 1015 may include a program or software stored, in read-only memory (ROM), Hash memory, or any other non-vola ile memor .

098} Peripheral eomponentC-s) 1020 may be any input or output device, or an interface for such devices, -that is integrated into device 1005. Examples .may include disk, controllers, sound controller, graphics controller, Ethernet controller, modem, 'universal serial bus (USB) controller, a serial or parallel port, or peripheral card slots, such as peripheral component interconnect (PCI) or accelerated graphics port (AGP) slots.

0.99] Input/output control component 102S ma manage data communication between processor 10. H) and peripheral eompo¾ent{s) 1020, input devices .1035, or output, devices 1040. Input/output control component 1025 ma also manage peripherals not integrated into device 3005. in some cases, inpui/oatpot control component 1025 may represent physical connection or port to the external peripheral. [0100] input 1 35 may represent a device or .signal external to device 1005 that provides input to device 1005 or its component. This may include a user interface or interface with or between other devices, la some cases, input 1035 may be a peripheral, thai interfaces with device Ϊ 005 via peripheral com onents) i 020 or may be managed by input/output control -component 1025,

{0101} Output 1040 may represent a device or signal external to device 1005 configured to recei ve output from device 1 05 or any of its cotftponents. Examples, of output 1040 may include a display, audio speakers, a printing device, another processor or printed circuit board, etc. in some cases, output .1040 may be a peripheral that interfaces with device .1005 via peripheral components) 1 20 or may be managed by input'output control component 1025.

f 0:102} The components of memory controller 140, device 1005, and memory array 1.00 -maybe made up of circuitry ' designed to carry out their functions. This may include various circuit elements, for example, conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or inactive elements, configured to carry- out the functions described herein,

[0103] From the foregoing it will be appreciated that,, although specific embodiments of the disclosure have been described herein for purposes of illustration, various modifications- may be made without deviating from the spirit and scope of the disclosure. Accordingly, the disclosure is not limited except as by ' the appended claims.