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Title:
APPARATUSES AND METHODS INCLUDING TWO TRANSISTOR-ONE CAPACITOR MEMORY AND FOR ACCESSING SAME
Document Type and Number:
WIPO Patent Application WO/2018/044510
Kind Code:
A1
Abstract:
Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further includes a first digit line and the first selection component configured to couple a first plate of the capacitor to the first digit line, and also includes a second digit line and the second selection component configured to couple the second plate to the second digit line. A sense amplifier is coupled to the second digit line and is configured to amplify a voltage difference between a voltage coupled to the second digit line and the reference voltage.

More Like This:
JPS59217291MOS DYNAMIC MEMORY
Inventors:
KAWAMURA, Christopher (1778 S. Toluka Way, Boise, Idaho, 83712, US)
DERNER, Scott (5032 E. Sagewood Drive, Boise, Idaho, 83716, US)
Application Number:
US2017/045756
Publication Date:
March 08, 2018
Filing Date:
August 07, 2017
Export Citation:
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Assignee:
MICRON TECHNOLOGY, INC. (8000 South Federal Way, Boise, Idaho, 83716, US)
International Classes:
G11C11/404; H01L27/07; H01L27/108
Foreign References:
US20060221746A12006-10-05
US20060215472A12006-09-28
US20050146918A12005-07-07
US20100165704A12010-07-01
US20020044477A12002-04-18
Attorney, Agent or Firm:
QUECAN, Andrew et al. (Dorsey & Whitney LLP, 701 5th AveSuite 610, Seattle Washington, 98104, US)
Download PDF:
Claims:
CLAIMS

What is claimed is:

1. An apparatus, comprising:

a capacitor having a first plate and a second plate;

a first digit tine supplied operative! with a reference voltage;

a first selection component, configured to couple the first plate to the first digit line responsive to activating the first selection component;

a second digit line;

a second selection component configured to couple the second plate to the second digit line responsive to activating the second selection component; and

a sense amplifier coupled to the second digit line and configured to amplify a voltage difference between a voltage on the second digit line and the reference voltage.

2, The apparatus of claim i whereirt the first selection component is coupled to a first word line and is configured to be activated responsive to activation o the first word line and wherein the second selectio component is coupled' to' a second word line and is configured to be activated responsive to aetivaiion of the second word line,

3., The apparatus of claim i wherein the first selection component is coupled between the first digit line and the first plate of the capacitor and wherein die second selection component is: coupled between the secon digit line and the second plate of the capacitor,

4, An apparatus, comprising:

a memory cell including first and second selection components;

first and second digit lines coupled to the first and second selection components, respectively; and

a capacitor including first and second plates, the first plate coupled to the first selection component and configured to receive a reference voltage from the first digit line when the first selection component is activated; and a sense component coupled to the second digit line.

5. The apparatus of claim 4 wherein the sense component chides a first sense node coupled to the second digit line, the sense amplifier configured to sense a voltage difference between the first sense node and a second sense node, amplify the voltage difference, and latch the voltage difference.

6. The apparatus of claim 5 whe ein the second sense node is coupled to: a first driver that provides the reference voltage to the second sense node,

7. The apparatus of claun 6 wherein the first driver i separate from a second driver thai provides the reference voltage to the first selection component via the First digit line,

.8. The apparatus of claim 4 wherein the. sense component comprises: a first .p-type field effect transistor having a gate;

a first n-type field effect transistor having a gate -coupled t the gate of the first p-type field effect transistor;

a second p-type field effect transistor having a gate;

a second n-type field effect transistor having a gate coupled to the gate of the second p-type field effect transistor;

a first sense node coupled to drains of the fi st p-type and first n-type field effect transistors, and further coupled to the gates of the second p-type and second n- type- field effect transistors; and

a second, sense node coupled to drains of the second p-type and second n-type field effect transistors, and further coupled to the gates of the first p-type and first n~ type field effect transistors.

9, The apparatus of claim 4, farther comprising;

a plu ali ' of memory cells coupled to the first and second digit lines, each of the memory ceils of the plurality of memory cells including respective first and second selection components.

10. The apparatus of claim 9, further comprising:

a plurality of fast word lines each coupled to the first selection component of a respec tive memory cell of the plurality of memory cells; and

a plurality of second word lines each coupled to the second selection component of a respective memory cell of the plurality of memory cells.

11. The apparatus of claim -wherein the••memor cell and the plurality of .memory eells are verticall -stacked relative to a .CMOS. -circuit positioned beneath the plurality of memory cells.

12. An apparatus comprising a first memory array and a plurality of first sense amplifiers,

wherein the first memory array comprises:

a plurality of first pairs of word hoes, each of the plurality of first pairs of word lines including first and second word lines, the first and second word lines being configured to be driven independently of each other

a plurality of first pairs of digit lines, each of the plurality of first pairs of digit lines including first and second digit lines, the. first and -second, digit Sines being configured to be driven independently of each other; and

a plurality of first memory cells, each of the first memory cells being coupled to an associated one of the pluralit of first pairs of word lines -and an' associated one of the■'plurality of first pairs of digit lines, each of the first memory ceils comprising first and second transistors and a first capacitor between the first and second transistors, the first and second transistors and the first capacitor being coupled in series between the first and second digit lines of die associated one of the plurality of first pairs of digit lines, and the first and second transistor having first and second gates, respectively, the first and second gates being coupled respectively to the first and second word lines of the associated one of the plurality of first pairs of digit lines; and' wherein each of first sense amplifiers mcluding first and second sense nodes, the first node being coupled to the first digit line of an associated one of the plurality of first pairs of digit lines.

13. The apparatus of claim 12, wherein the second sense node of eac of the first sense amplifiers is supplied with a refereijce voltage to compare a voltage at the ■first seo.se .node with the reference voltage.

14. T e apparatus of claim 12, further comprising a semiconductor base and an insulating film over the semi conductor base, the first 'memory array - being: formed over the insulating film.

15. The apparatus of claim 14,. wherein each of the first sense amplifiers is formed in the semiconductor base,

16. The apparatus of claim 1-4, wherein each of the first sense amplifier is formed between the memory array and the semicon uc or base.

17. The apparatus of claim 12, further comprising a second memory array and a plurality of second sense ampli fiers;

wherein the second memory array comprises:

a plurality of second pairs of word lines, eac of the plurality of second pairs of word lines including third and fourth word lines, the third and fourth word lines being configured to he driven independentl of each other;

a plurality of second pairs- of digit lines,, each of the -plurality, of second pairs of digit lines including third and fourth digit lines, the third and fourth digit hues being configured to be driven independently of each other; and

a plurality of second memory cells, each of the second memory ceils being coupled to an associated one of the plurality of second pairs of word lines and an associated one of (he plurality of second pairs of digit lines, each of the second memory ceils comprising third and fourth transistors and a second capacitor between the third and fourth' transistors, the third and fourth transistors and the second capacitor being coupled in series between the third and fourth digit lines of the associated one of the plurality of second pairs of digit lines, and the third and fourth transistor having third and fourth gates, respectively, t e third and fourth gates being coupled respectively to the third and fourth word lines of the associated one of the plurality of second of digit lin s.

wherein, each of secood sease amplifiers including third a»d fourth sense nodes, the third node being coupled to the third digit Sine of an associated one of the plurality of second pairs of digit lines; arid

wherein the second digit line of each of the plurality of first pairs of digit lines is coupled to the fourth digit line of an associated one of the plurality of second pairs of digit lines,

18. The apparatus of claim 17, wherein the second sense node of each of the first sense amplifiers is supplied with a reference voltage to compare a voltage at the first sense node with the reference voltage, and wherein the fourth sense node of each of the second sense amplifiers is supplied with die reference voltage to compare a voltage at- the third sense node with the reference voltage.

19. The apparatus of claim 12, wherein the second word lines. of the plurality of first pairs of digit lines are coupled to each other.

20. The apparatus of claim 1 , wherein the first memory array comprises a conductive plate that serves as the second word tiaes of the plurality of first pairs of

Description:
APPARATUSES AND METHODS I CLUDI G TWO TRANSISTOR-ONE

CAPACITOR MEMORY D FOR ACCESSING SAME

CROSS-REFERENCE TO RELATED APPLICATION

] This application claims the filing benefit of U.S.. Provisional Application .No.

62/381 ,M4, filed August 31„ 20 i 6. This application is incorporated by reference- herein in its entirety and for all purposes.

BACKGROUND

] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication, devices, cameras, digital displays, and the like, Information is stored by programing different states of a memor device. For exaffiple s binary devices have two states, often den ted by a logic "1 " or a logic "0." In -other systems, more than two states may be stored. To access the stored information, the electronic device may read, or sense, the stored state in the memory device. To store information, the electronic devic may write, or program, the state in the memory device,

] Various types of memory devices exist including random access memory (RAM), read onl memory (ROM), dynamic RAM (DRAM), synchronous dynamic- RAM (SDRAM), ferroelectric RAM: (FeRAM), magnetic RAM. (MRAM), resistive RAM (RRAM), flash, memory, and others. Memo y devices may be volatile or nonvolatile, ' Hon- volatile memory, e.g., flash .memory, can store data for extended periods of time even in the absence of an external power source. Volatile memory devices, e.g., DRAM, may lose their stored state over time unless the aie periodicall . refreshed by an external power source, A binary memory device may, for example, include a. charged or discharged capacitor. A charged capacitor may, however, become discharged over time through, leakage currents, resulting in the loss of the stored information. While features of non-volatile memory, such as the ability to store data without periodic refreshing,, may -be advantageous, certain features of volatile memory may offer performance advantages, such as fester read or write speeds. SUMMARY

08 1 Example apparatuses are disclosed herein. An example apparatus may include a capacitor having a first plate and a second plate. The example apparatus may also include- a firs digit line supplied operative!y -with a reference voltage and a second digit line. The example apparatus may also include a first selection component configured to couple the first plate to the first digit line responsive t activating the first selection component and a second selection component, configured to -couple the second plate to the second digit line responsive to activating the second selection component. The example apparatus, may also include a sense amplifier coupled to the second digit lice and configured to amplify a voltage difference between a voltage on the second digit line and the reference voltage.

{605} Another example apparatus .may include a memory cell including first and second selection components. The example apparatus may also include first and second dsgit lines coupled to the first and second selection components, respectively. The example apparatus may also include a capacitor including first and second plates, the first plate coupled to the first: selection component: and configured t receive a reference voltage from the first digit line when the first selection component is activated. The example apparatus ma also include a sense component coupled to the second digit Sine,

{006} Another- example apparatus may include a first memory array and- a plurality of first sense ampli fiers. The first memor -array may comprise a pluralit -.of first .pairs of word lines, with each of th plurality of first pairs of word lines including first and second word lines, and with the first and second word lines being configured to be driven independently of each other. The first memory arra ma further comprise a plurality of first pairs of digit lines, with each of the plurality -of first, pairs of -digit lines including- first and second digit lines, and wit the first and Second digit lines being configured to be driven independently of each other. The first memory array ma further comprise a plurality of first ' memory cells, with each of the first memory cells being coupled to an associated one of the plurality of first pairs of word lines and an associated one of the plurality of first pairs of digit lines. Each of the first memory cells may comprise first and second transistors and. a first capacitor between the first and second transistors, with the first and. -second transistors and the first capacitor being coupled in series between the first and second digit lines of the associated one of the plurality of first pairs of digit Khes. In. such first memory cells, the first and second transistor may have first and second gates, respectively, with the first and second gates being coupled respectively to the first and second word, lines of the associated one of the plurality of first pairs of di it lines, in such an apparatus, each of the first sense amplifiers may include first and second sense nodes, with the first node being coiipled to the first digit line of an associated one of the plurality of first pairs of digit lines.

BRIEF DESCRIPTION OF THE DRAWINGS

f067j Figure I illustrates an example memory array that supports vertically stacked memory ceils in accordance with an embodiment of the present disclosure,

fOfiS] Figure 2 is a schematic diagram of an example circuit that includes a column of memory cells according to an embodiment of the present disclosure.

[009 Figure 3 is a schematic diagram of a sense component according to an embodiment of the disclosure.

[010 Figure 4 is a timing di gram of various signals daring ¾ read operation for logic

* 5 data according to an embodiment of the disclosure.

jOllj Figure 5 is a timing diagram, of various signals during a read operation for logic

"0" data according to an embo iment of me disclosure:

1012] Figure 6 is a tliruus diagram of various s gnals during a write operation according to an embodiment o f the disclosure..

[01.3] Figure 7 is a diagram depicting a cross-sectional side view of a memor array showing an example configuratio fo vertically stacked memory cells according to an embodimen t of the disclosure.

|0i4j Figure 8 illustrates an example memory array tha supports vertically stacked memory cells iu accordance w ith an embodiment of the present disclosure. .

jOI S] Figure 9 illustrates an example memory arra that supports vertically stacked memory cells in accordance with an embodiment of the present disclosure.

[016] Figure 1 is a schematic diagram of an example circuit that includes a column of memory ceils according to an embodiment of the present disclosure.

[017] Figure 1 1 is a timing diagram of various signals during read and write operations according to an embodiment of the disclosure. |0ί 8] Figure 12 is a diagram, depicting a cross-sectional side view of a memor array showing au example configuration for vertically stacked memory cells according to an emboduneat of the disclosure.

β19] Figure 13 is a block diagram of a memory chip in. a memory system, in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION

|020| Certain details are set forth below to provide a sufficient understanding of embodiments of the disclosure. However, it will be clear to one skilled in the art that embodiments of the disclosure, may be practiced without these particular details. Moreover, the particular embodiments of the present disclosure described herein are provided by way of example and should not be used to limit the scope of the disclosure to these particular embodiments. Irs other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown ia detail in order to avoid unnecessarily obscuring the disclosure.

j[02:!j A memory ceil ca« ' be vertically stacked as part of an integrated circuit architecture. For example, an example memory cell of a vertically stack configuration may be referred to as 21MC, where each capacitor plate of a capacitor is coupled to a source/drain region of a respective transistor. Vertically -stacking ' metttory cells may have beneficial, properties that may result in improved performance relative to other memory architectures; tor example, improving refresh timing and faster write times to •memory ceil, relative to the respective refresh timing an write time of a traditional memory cell that is placed on a memory arra parallel to CMOS circuitry. In . . . addition, a memory state can be determined based on a comparison of the respective digit lines at tlie top and bottom of the vertically stacked memory cell. However, the vertical stacking of memory cells can introduce structural difficulties when incorporating such vertically stacked memory cells into integrated circuit architectures.

[922] A vertical configuration can introduce structural difficulties such as coupling the memory eel! to various connection nodes of the memory cell. For example- increased connections may be necessary to support a vertically stacked memor cell having a connection at the top that is to be connected t a connection at. the bottom of the vertically stacked memory cell, A digit line at the top of a vertically stacked memory cell may require a connection to a sense' amplifier connected at the bottom of the vertically stacked memor cell (e.g., a lower digit line). A vertical line being routed from the top of the vertically stacked memory cell ' to the bottom may introduce other issues when incorporating that circuitry into an integrated circuit; for example, the vertical line may introduce electrical leakage of a signal applied on that vertical line or it may introduce other noise elements to the memory cell circuitry. Embodiments described i -the present -disclosure eliminate- the need to utilize such vertical lines. As will be described ' herein, a reference voltage applied to a upper digit line can be provided during activation -of a sense amplifier during a read operation of a vertically stacked memory cell. As such, the -embodiments described herein need not utilize ■vertical imes -connecting the top of a vertically -stacked memory cell to. a -connection at the bottom of the memory ceil.

|023| Figure 1 illustrate an example memory array 100 that supports vertically stacked memory ceils in- accordance win) an embodiment of the present disclosure. Memory array 100 may also be referred to as an electronic memory apparatus. Memory .array 1.00 includes memory cells 105 thst, are configured to store different states. Each -memory cell 105 may be configured Jo store two states, denoted as a logic 0 and a logic 3 . In some eases, memory ceil IDS is configured to store more than two logic states. A memory ceil 105 may include a capacitor to store a charge representative of the different states. For example, a charged and uncharged capacitor may represent two logic states, .respectively.

{ ' 024} Operations such as reading and writing may be performed on memory cell 1 5 b activating or selecting the appropriate: access lines 1 1 and digit lines 115. Access lines 1 10 may also be referred to as word lines 1 10. Activating or selecting a word line HQ or a digit line 1 15 ma include applying a voltage to the respective line. Word linos 1.1.0 and digit lines 1 15 are made -of conductive- materials. For example, word lines 1 10 and digit lines 1 15 may be made of metals (such as copper, aluminum, gold, tungsten, etc), metal alloys, doped semiconductors, other conductive materials, or the like. According to the example of Figure 1 , each row of memory ceils 105 is coupled to word lines 110 WL-COMP -and WL-T UE, and each colum of memory cells 105 is coupled to digit lines 115 BL-COMP and BL-TRUE. it should be noted that word line WL-COMP and WL-TR ' UE do not mean the so-called true and complementary word Sines that takes -complementary levels or states to each other, but merely indicates a pair of word lines throughout the disclosure. As will be apparent form the descriptions below, the word lines WL-COMP an WL-TRIJE are indeed drives independently of each other. Similarly, digit lines BL-COMP and BL-TROE merely means a pair of digit lines throughout the disclosure that ma take individual levels o states different from each other.

) By activating the respective word lines 110 and digit Sines ! 15 (e,g„ applying a voltage to the word lines 1 10 or digit lines 115),- a memory cell 105 may he accessed at their intersection. Accessing the memory cell 105 may include reading or writing the memory cell 105. The intersection of a word lines 110 and digit lines 1 15 may be referred to as an address of a memory cell

j In some architectures, the logic storing device of a cell, e.g., a capacitor, may be electrically isolated from the digit lines by selection components. A word line 1 10 may be coupled to and may control a respective selection component. For example, the selection component may be a transisto and the word line 1 10 may be coupled to the gate of the transistor. Activating the word line 1 10 results in a coupling or closed circuit between the capacitor of a memory cell 105 and corresponding digit line 1 15. The digi t lines may then be accessed to either read or write the memory cell 105,

] Accessing memory cells 105 may be controlled through a row decoder 12(1 and a column decoder 130. in some examples, a row decoder 120 receives a row address front the memory controller 140 and activates the appropriate word lines 1 10 based on the -received row address. Similarly, a column decoder 13 receives a column address from the memory controller 140 and activates the appropriate digi lines 1 15. For example, memory array 100 may include multiple word lines ! 10, and multiple digit lines 1 15. Thus, by activating word lines 110 WL-COMP and WL-TEU ' E and digit lines 1 15 BL-CQMP and BL-TRUE, the memory cell 105 at their intersection may be. accessed.

j Upon accessing, a memory cell 105 may be read, or sensed, by sense component 125 to determine the stored slate of the memory ceil 105. For example, after accessing the memory cell 1 5, the capacitor of memory cell 105 may discharge onto corresponding di it lines 1 15. Discharging the capacitor ma be based on biasing, or applying a voltage, to the word lines to couple the capacitor to the digit lines. For example, a memory cell 105 may be coupled to a digit Mac BL-COMF, to which a inference voltage applied. The coupling of the capacitor to. the digit line BL-COMP can cause the capacitor to discharge, which causes a change in voltage to the digit line BL-TRUE, As such, the discharging ma cause a change in the voltage of the digi t line .BL-TRUE 115, which sense component 125 may compare to a reference voltage, (not shown) in order to determine the stored state of the memory cell 165, For example,, if -the digit line BL-TRUE I 15 has a higher voltage than the reference voltage, the -sense component 125 may determine that the stored state in memory celt 105 is a- logic I and vice versa. Sense component 125 may include various transistors or amplifiers in order to detect and amplify a difference in the signals, which ma he referred to as latching. The detected logic state of memory cell 105 may then be output through column decoder 130 as output 135. The above processes will be discussed in more detail later.] A memory ceil 105 may be written by activating the relevant word lines 1 10 and digit lines 115, As discussed above, activating word lines 110 couples the corresponding row of memory ceils 1.05 to their respective digit lines 1 15. By controlling the relevant digit lines- 115 while the word lines 1 10 are activated, a memory cell 105 may be written -e.g., a logic value may be: stored in the memory cell

105. Column decoder 13 ma accept data, for example .input 135, to be written to the memory cells 105. A .memory cell 105 may be written, by applying a voltage across the capacitor. This process is discussed in more detail later.

] In some Memory architectures, accessing the memory ceil 105 may degrade or destroy the stored state, and restore operations may be performed to return the original stored state to memory cell 105. For example, the capacitor may be partially -or completely discharged during a sense operation,, corrupting the stored state. So the stored state may be re-written after a sense operation. Additionally, activating word lines 1 10 may result in. the discharge of ail. memory cells in the row. Thus, several or all memor cells 105 in the row may need to be restored,

} The memory controller 140 ma control the operation (e.g., read, write, restore, etc.) of memory cells 105 through the various components, such as row decoder 120, column decoder 130, and sense component 125. Memory controller 140 may generate row arid column address -signals in order to activate the desired word lines 1 1 and digit lines 115. Memory controller 140 may also generate and control various voltage potentials used during the operation of memory array 1.00. in general, the amplitude, shape, or duration of an applied voltage discussed herein ma be adjusted or varied and may be different for the various operations for operating memory away 100. Fmthermore, one or multipl memory cells 105 within memory array 100 may be accessed simultaneously. For example,, multiple memory cells of memory array 100 may be accessed simultaneously when a word line io which the multiple memory cells are coupled is activated.

j032] Memory controller 140 may include biasing component 144 aid timing component 348, and may operate memory array .100 as described in Figure 1 . Memory controller 140 may be in electronic communication with word lines 1 10, digit lines 115, aid sense component 125. Memory controller 140 may provide a - reference voltage Y EF to the sense component 125. The components of memory array 100 may be in electronic communication -with each other arid may perform the functions that will be described in more detail later.

|033| In some cases, memory controller 140 may perform its -operations using timin component 148, For example, timing component 148 may .control the timing of the various word line selections or biasing, including tuning for switching and voltage application to perform the memor functions, such as reading and writing, discussed herein. In some cases, timing component 1 may control the operations of biasing component 144.

(034) Memory controller .140 may be configured to activate word lines 1 10 or digit lines 1 15 by applying voltages to the word and digit lines. For example, biasing -component 144 may be ' configured to apply a voltage to operate ' memory cell 105 to read or write memory ceil 1.05 as described further ' later. Biasing component 1 4 may also provide a reference voltag YREF to sense- component 125. Additionally, biasing -component .144 may provide voltage potentials for the operation of sense component 125.

f035j Sense component 125 may compare a signal from memory ceil 105 (through digit line 115) with a reference voltage V EF. The reference voltage YREF may have a value between the two sense voltages, as described later, Upon determining the stored state, the sense component 125 may latch the output, where it may be used in accordance with the operations of an electronic device that memory arra 1 0 is a part. |036] The com onents of tnernory controller 140 and memory array 100 may be made up of circuitry designed to cany out their functions. This may include various circuit elements, for example, conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or inactive elements, configured to carr ' out the Amotions described herein.

|β37| Figure 2 illustrates as example -circuit 200 thai includes a column of memory cells according to an embodiment of the present disclosure. Figure 2 illustrates an example circuit 200 that includes memory ceils 105 in accordance with various embodiments of the present disclosure. Circuit 200 includes memory cells 105 MC(0)~ MC(n), where "n" depends on the array size. The circuit 200 farther includes ward lines WL-GOMP{0)-WL-CO F(«) mid WL-TRUE{0 -WL-TRD.E{n digit lines BL- COMP and 8L-TRUE, and .sense component- 125. The word lines, digit lines, and sense component may he examples of memory cells 105. word lines 1.10, digit lines 115, -and sense component 125, respectively, ss described with reference to Figure 1. While one column of memory cells 105 ss shown in Figure 2, a memory array may include a plurality of columns of memor cells as those shown,

[038| Memory cells 105 may include a logic storage component, such as capacitor 205 that: has a first plate 230 and a second plate 215. First plate 230 and second plate 215 may he capaeitively coupled through a dielectric, ' material positioned between mem; The orientation of the first plate 230 and the second plate 215 may he .flipped without changing the operation -of memory cell 105, The memory cells 105 may further include -selection components 220 and 224. The selection: components 220 and 224 may be transistors, for example, n-type field effect transistors, in such an example, each of the memory cells 105 includes two transistors and one capacitor.

[039] Circuit 200 also includes dri ver circuit 235 coupled to sense node A of the sense -component 125: (and thus to digit line .8L-T UB), and driver circuit 23? coupled to digit line BL-COMP. Driver circuit 235 can output -a range of voltages t the digit line BL-TRUB. and thus to the same voltage to its sense node A. Sense component 125 can be a sense amplifier "SA" The driver 237 can drive the voltage of the digit line BL-COMP to a supply voltage, VCC; io ground; or to a reference voltage VREF that is a half of the supply voltage or 1/2 VCC. In some embodiments, these voltages may be referred to as sense voltages for a high and low logic states. For example, a VCC voltage may correspond to a high logic state, while a QND voltage may correspond to a low logic state; or vice versa.

[04ffj Memory cells 105 - may be in electronic communication, with sense component

1.25 through digit line BL-COMP and digit line BL-TRUE. in the example of Figure 2, first plates 230 may be accessed via digit line BL-COMP and second plates 215 ma be accessed via digit line BL-TRUE. As described above, various states may be stored by charging or discharging capacitor 205.

|tt4ij The stored state of capacitor 205 ma be read or sensed b operating various elements represented in circuit 200. Capacitor 205 may be in electronic communication with digit lines BL-TRUE and BL-COMP. For example, capacitor 205 can be isolated f om digit lines BL-TRUE. and BL-COMP when selection components 220. nd 224 are deactivated, and capacitor 205 can be coupled to digit lines BL-TRUE and BL-COMP when selection components 220 and 224 are activated. Activating selection components 220 and 224 may be referred to as selecting memory cell 105. in some cases, selection components 220 and 224 are transistors and the operation is controlled by applying voltages to the transistor gates, where the voltage magnitude is greater Chan the threshold voltage of the transistors. Word line WL-TRUE may activate selection component 220 and word line WL-COMP may activate selection component 224. For example, a voltage applied to word line WL-TRUE is applied to fee transistor gate of selection component. 220 and a voltage applied to word line WL-COMP is applied to the transistor gate of selection component 224. As a result, the respective capacitor 205 is coupled with digit lines BL~TRL r E and BL~€0MF ; respectively. The memor cell 1 5 may be considered in storage mode when both word lines WL-TRUE and WL-COMP are deacti vated.

[042] Word lines WL-TRUE(0 WL-TRUE{n) and WL-COMPi )-WL-COMP(n) are in electronic commu icat on with selection components 220 and 22 of memory cells 105 MC(0)~MC(n). respectively. Thus, activating word lines WL-TRUE and WL- COMP of a respective memory cell 105 may activate the memory ceil 1 5. For exampie s activating WL-TRUE( ) and W ' L~CQMP(0) activates memory cell MC(0), activating WL~TR.UE(1 ) and WL-COMP(l ) .activates memory ceil MC(.l), and so on. In some examples, the positions of selection components 220 and 224 may be switched, such that selection component 220 is coupled betwee digit line BL-COMP and first plate 230, and the selection component 224 is coupled between digit line BL-TRUE and second plate 215.

[Θ43| To sense the stored state of the capacitor 205, a reference voltage (e.g., VREF) may be provided to the digit line Bl,~CQMP, for example,, by driver circuit : 237 } and word lines WL-TRUE and WL-COMP may be biased to select a respective memory cell 105. Biasing the word lines WL-TRUE and WL-COMP couples a plate of the capacitor 205 to a respective digit line. Coupling the plate to die respective digit line may change the c arge store by the, capacitor 205. The change in stored charge may depend on the initial stored state of each capacitor 205— e.g., whether the initial state stored a logic 1 or a logic 0, A change in the charge of a plate of the capacitor may cause a change in voltage at that, plate. The change ' in the voltage may be coupled across the capacitor 205 to cause a voltage change at the other plate. For example, a change in voltage at the first plate 230 may be coupled across the capacitor 205 to cause a voltage change on the second plate 215, When the selection component 220 is activated by the word line WL-TRUE, the change in voltage of the second plate 2 I S may cause a change in the voltage of digit line BL-TRUE. The resulting voltage of digit Sine BL-TRUE may be compared to the reference voltage (e.g., the same reference vol tage VREF provided to the digit line BL-COMP and supplied to the sense node B of the sense amplifier 125) by the sense component 125 in order to determine the stored state its each Memory cell 105.

|044| Sense component 125 may include various transistors or amplifiers to detect and amplify a difference in signals, which may be referred to as latching. Sense component 125 may include a sense amplifier; that receives and compares the voltage of digit line BL-TRUE at node A with tire reference voltage VREF at node B and changes in thai voltage (e.g., an increase or decrease relative to the reference voltage VREF). The sense amplifier utput may drive a sense node A, and the- digit, line BL-TRUE to a higher (e.g., a positive) or lower (e.g., negative or ground) supply voltage based on the comparison. For instance, if digit line BL-TRUE has a higher voltage than the reference voltage VREF, then the sense amplifier output may drive the sense node A and digit line BL-TRUE to a positive supply voltage. Sense component 125 may then latch the outpu t of the sense amplifier and/or the voltage of digit line BL-TRUE, which may be used to determine the stored state in memory cell 105, e.g., logic 0, Alternatively, if digit line BL-TRUE lias a lower voltage than the reference voltage VREF, the sense amplifier output may drive the sense node A and digit litre BL-TRUE to a negative or ground voltage. Sense component 125 may similarly latch the sense amplifier output to determine the stored state in memory ceil 105, e.g., logic 1. The latched logic state of memory cell 105 may then be output, for example, through column decoder 130 as output 135 with reference to Figure 1,

] To restore the logical state after a read .-operation on - the - .memory ceil 105, the digit line BL-TRUE may be driven, to the reference voltage VREF by driver 235. As further described below, along with deactivating the word lines WL-TRUE, L-COMP at particular times, the initial, logic state of the capacitor can be restored to the first plate 230 as the capacitor 205 couples the driven reference voltage from, digit line BL-TRUE to the first plate 230 via the second plate 2.15. During such a restore,, the driver 237 may maintain biasing the reference voltage VREF on the digit line BL-C0 P, Accordingly, operations of the drivers 235, 237 can be used to restore states t the capacitor 205,

] To write memory cell 105, a voltage may be applied across capacitor 205. ' Various methods ma he used. In some examples, selection components 220 and 224 may be activated through, word lines WL-TRUE and ' WL-COMP, respectively, in order to couple capacitor 205 to digit, lines BL-TRUE and B.L-COMF. For a capacitor 205, a voltage may be applied across capacitor 205 by controlling the voltage of first plate 230 (through digit line 8L-COMP) and second plate 215 (through digit line BL-TRUE) to apply a positive or negative voltage across the capacitor 205. In mbodiments, for data writing,, the write: driver 237 may drive die digit line BL-COMP to the suppl voltage VCC or the ground voltage depending on data to be written, and the driver 235 may drive the digit line BL-TRUE to the reference voltage VREF, which will be described late in more detail.

] to various implementations, the selection components 224., 220 of Fig. 2 can be transistors such that the memory ceils 105 may be referred to as 2T !C configurations.

Such, a configuration may be utilized in B.RAM (dynamic random access memory) and/or other types of memory.

] Figure illustrates a sense component 1 5 according to an embodiment of the disclosure. The sense component 125 includes p-type field effect transistors 2.52 and 256 and n-type field effect ' transistors 262 and 266. Gates of the transistor 252 and transistor 262 are coupled to sense node A. Gates of the transistor 256 and transistor 266 are coupled to sense node B. The transistors 252 and 256 and the transistors 262 md 266 represent sense amplifier. A p-type field effect transistor 258 is -configured to be coupled, to a power supply (e.g., V EAD voltage power supply) and is coupled to a common node of the transistors 252 and 256. The transistor 258 is activated by an active PSA signal (e.g., active low logic). An n-type field effect transistor 268. is configured to he coupled to a reference voltage -(e.g., .ground) and is coupled to a common node of the transistors 262 and 266. The ' transistor 268 is activated by an active NSA signal (e.g., active high logic).

[M9] In operation, the sense amplifier is activated by activating the PSA arid NSA signals to couple the sense amplifier to the voltage of the power supply and the reference voltage. When activated, the sense ' amplifier compares the voltages of sense nodes A and B, and amplifies a voltage difference by driving the sense nodes A and B to complementary voltage levels. For example, the sense amplifier drives sense node A to the supply voltage; or -vice versa. The sense amplifier may further dri ve the sense node B to a voltage that is eomplenicntary to the voltage of sense node A (e.g., sense node A driven to VCC and sense node B driven to ground; sense node A driven to ground and sense node 8 driven to VCC). When the sense nodes A and B have been driven to the complementary voltage levels, the states of sense nodes A and B are latched by the sense amplifier and remain latched until the sense amplifier is deactivated,

|05Oj In various embodiments, the sense component 125 may optionally include driver 25! thai can be a driver coupled to sense node B of Fig, 2. For example, with reference to Fig. 2, the driver 251 is separate from the driver 237 coupled to the digit line .BL- ' COMP. Continuing In this example, drivers 25 i and 237 ma be configured to provide the same reference voltage. Driver 251. may be placed at the bottom of a verticall stacked memory array (e.g., formed as part of a CMOS under the array implementation described below later), while driver 23? may be placed at the top of a verticall stacked memory array. Accordingly, in the implementation of Fig. 2, sense node B is not connected to the digit line BL-C0MP. |05i] Figure is a. timing diagram of various signals d rin a read operation according to an embodiment of the. disclosure. Figare 4 will be described with re.fere.ace to memoiy array 100 and example circuit 200 of Figures 1-3 respectively. The state stored by the memory ceil 1.05 in me example read operation of F igure 4 is a logic "I".

{852 j Prior to time TO, the digit lines BL-TRUE and BL-COMP ( ot depicted) are at an inactive voltage. For example, the drivers 235 and 237 preeharge tiie digit lines BL-TRUE and BL-CQ P digit ikes to a reference voltage VREF; Accordingly, sense node A (V A ) of the sense component 125 is set to the voltage VREF of the preeharged digit line BL~TRUE, Sense node B of the sense. component 125 (not depicted in Figure .3) is also set to the reference voltage VREF, The voltage at the first plate 230 (V^) has an initial voltage corresponding to the logic T state. As depicted in Figure 3, that is the supply voltage VCC The voltage at the second plate 215 (\½) has an .initial voltage of the reference voltage VREF,

|0S3| At rime TO, the word line WL-COMP is activated to activate selection component :224 of a memory cell 105 being accessed For example, WL-COMP is driven to a voltage higher than the supply voltage, VCC- , to activate the selection ■component 224. As a. result, the digit line BL-CO P is coupled to first plate 230 of the capacitor 205. Thus the voltage of the first plate 230 changes from the supply voltage VCC to the reference voltage VREF as the driver 23? is continued to be activated to supply the reference voltage VREF to the bit line BL-COMP, The voltage decrease of the first plate 230 is coupled through the capacitor 205 t cause a voltage change at the second plate 215 as the select component 220 is still deactivated at. this moment. For example, the voltage at the first plate 230 changes from the supply voltage VCC to the reference voltage. VREF from time TO t time Tl causing the -voltage of the second plate 215 to change from time TO to- time TL The magnitude of the change In voltage caused at the second plate 215 is based at least in part on the charge state initially stored ' by the capacitor 205. For example, if the capacitor 205 is charged with soeh an amount, mat corresponds a reference voltage VREF (that is 1/2 VCC), the voltage- level ' of second plate 215 is changed approximately to the ground voltage.

[054] Shortly after the voltage at first plate 230 begins to change,, the second plate 215 changes responsive to the voltage change at the first plate 230. The second plate 215 is forced to preserve the -change -in voltage because the selection component 220 is not. et acti vated to couple the second plate 2.15 to die digit Uue BL-TRUE. For example, the voltage of tile second plate 215 may change responsive to a time period that is associated with a voltage change of the first plate 230.. As depicted, voltage- at the first plate 230 first changes exponentially; then the voltage at the second plate 215 begins to change exponentially. The exponential change of the voltage can he based at least In part on the dielectric, material of the capacitor 205 ars!/or the distance between the first plate 230 and the second plate 215. Th second plate 215 ' may change proportionally to the voltage change at the first plate 230. In this example, with the state of the present example of Figure 4 corresponding to a logic L the voltage at the second plate 215 due to the voltage change of the first plate 230 from the supply voltage VCC to the reference voltage V EF causes the second plate 215 to decrease by proportional, voltage. Thus the voltage at the second plate 215 decreases to below the reference voltage VREF.

f055] At time Tl, the word line WL-TRUE is activated to activate selection component 220 of a memory cell 105 being accessed, while deactivating the driver 235. For example, WL-TRUE is driven to voltage higher than the supply voltage, VOCM-, to activate the selection component 220, As a result, the digit line BL-TRIJE is coupled to second plate 215. The voltage of the second plate 215 is coupled to die sense node A of the sense component .125 through selection component 220 over digit line BL-TRUB. The voltage at sense node A (V A ) changes responsive to the voltage at second plate 215, because the driver 235 is being deactivated. As depleted, the voltage at sense node A decreases to less than the reference voltage VREF (eg,, approaches ground),

[056] Shortly before time T2, the sense component 125 (e.g., a sense amplifier) is activated to compare the voltage of sense node A- (the voltage of the second, plate 215 responsive to the change in the voltage at the first plate 230) wit the -voltage of sense node B that is set to the reference vol tage VREF. Due to the voltage of sense node A being less than the voltage of the reference voltage VREF of sense node B, the sense component 125 drives sense node A to ground and sense node B to supply voltage VCC. Accordingly, the sense component 125 amplifies the change in voltage detected at second. . late 215. The ground voltage at sense node A represents the logic I state read from the- memor cell 105, The seme component 125 can latch that logical state. For example, while not shown in Figure 4, the detected state of memory cell 105 xm then be output ' through column decoder 130 and output 135 (Figure 1). Accordingly, the sense component I 25 detects the dee-tease in voltage at sense node A arid thereby drives the voltage of digit fine BL-TRUE to ground.

857] Having read the state at the first plate 230, the circuit 200 restores the initial state to the first plate 23.0. At time T2, the selection component 224 is deactivated with word line. WL-COMF (e.g.,. drivesi to ground) to decouple the digit line Bt-COMP from the first plate 230, As a result, the first plate 230 remains at the reference voltage V EF. if desired, the activation of the WL-COMP word line (and thus activation of select component .224} may be prolonged until at Time 3 as shown by a dotted Sine, At time T3, driver 235 is activated again to drive the sense node A to the reference voltage VREF, .resulting in driving the voltage of digit Hue BL-TRUE to the reference voltage VREF, At this time, as d e selection component 224 is being deactivated, the change ar voltage at the second plate 215 from the ground voltage to the reference voltage causes a voltage change at the first, plate 230 from the reference voltage to the supply voltage VCC. Accordingly, the initial VCC charge can be restored to the first plate 230. la some embodiments, the driver 235 ma drive the voltage of digit line BL-TRUE to a voltage higher than the supply voltage VCC, which may assist in driving the voltage at the first plate 230 to the supply voltage VCC if noises or interference exists in the capacitor 205. .

0S8] At time T4, the selection: component 220 i deactivated with word line WL-TR tJE (e.g., driven to ground) to decouple the second plate 215 from, the digit line BL-TRUE, and to complete the read operation. By decoupling the second plate 215 from digit line BL-TRUE, the voltage in the capacitor at the first plate 230 and sec-end plate 2-15 is: preserved until the next read or write operation for the memory ceil 105,

059] I some embodiments, the timing of the signals may be different than that specifically shown In Figure 4. Other signal timings may be used as well in other embodiments to couple the first plate 230 to the digit line BL-CQMP to cause the voltage of the first plate 230 to change, which in turn causes voltage change at the second plate 215 that i provided to the sense node A of the sense component 125. ] Figure 5 is a. timing diagram of various signals during a read operation according to an embodiment of the. disclosure. Figure 5 will be described with reference to memory arra 10 and example circuit 200 of Figures I and 2. The data state stored by the .memory ceil .1 5 in the example read operation of Figure 5 is a .logic "0".

J Prior to lime TO, die digit lines BL-TRUE and BL-GOM.P (not depicted) are at a refereace voitage. For example,, the drivers 235 and 23? preeharge the digit lines BL-TRUE and .BL-.CO P digit Ikes to s reference voltage VREF. Accordingly, sense node A of the sense component 525 is set to the voltage VREF of the preeharged digit line BL-T IJE. Sense node B of the sense component 125 is also set to the reference voltage VREF. The voitage at the first plate 230 (VJ ) has an initial charge corresponding to the logic ' F state. As depicted in Figure 5, that is ground (e.g., OV). The voltage at the second plate 215 (Vps) has an initial charge of the reference voitage VREF,

] At rime TO, the word line L~COMP is activated to activate selection component 224 of a memory cell 1.05 being accessed. For example, word line WL-COMP is driven to a voltage higher than, the supply voltage,, VCC+, to activate the selection component 224. As a result, the digit line BL-COMP is coupled to first plate 230 of the capacitor 205. Thus voitage of the first plate 230 changes torn ground (e .g., 0V) to the reference voltage VREF, The voltage increase of the first plate 230 is coupled through the capacitor 205 to cause a voitage change at the second plate 215. For example, the voltage at the first plate 230 changes from the ground voltage OV to. the reference voltage VREF from time: TO to time T.S .causing -the voltage -of the second plate 215 to change from time TO to time Tl , The .magnitude of the change is voitage caused at tile second plate .215 is based at least in part on the charge state initially stored by the capacitor 205,

1 Shortly after the voltage a t first plate 230 begins to change, the second plate 215 changes responsive to the voltage change at the first plate 230. ' The second plate 215 is forced to preserve, the change in voltage because the selection component 220 is not vet activated to couple the second plate 2.15 to the digit line BL-TRUE. For example, the voltage of the second plate 215 may change responsive to a time period that is associated with a voltage change of the first plate 230. As depicted, voitage at the first plate 230 first .changes ■■ exponentially; then the voltage at the second plat 215 begins to change exponentially. Tte exponential change of the voltage can. be based at least HI part on the dielectric material of the capacitor 205 and/or the distanc between the first plate 230 and the second plat 2.15. The second plate 2 Ϊ 5 may change proportionally to the voltage change at the first plats 230.- hi this example,: with the state of the present example of Figure 5 corresponding to a logic 0, the voltage at second, plate 215 due to the voltage change of the first plate 23 rfrom the ground voltage 0V to the reference voltage VREF causes tbe second plate 215 to increase by a proportional voltage. Thus the voltage at the second plate 215 increases to the supply vol tage VCC.

At time Tl, the word line WL-TRUE is activated to activate selection component 220 of a -memory cell .105 bein accessed. For example,.- word line WL-TRXJE is driven to a voltage higher than the supply voltage, VCC*, to activate the selection component 220, As a result, the digit line BL-TRUE is coupled to second plate 215. The voltage of the second plate 215 is coupled to the sense node A of the sense component 125 through selection component 220 over digit, line BL-TRUE. As the driver 235is deactivated, the voltage at sense node A (V A ) changes responsive to the voltage at second plate 215. As depicted, the voltage at sense node A increases to more than the .reference voltage VREF (e.g.,. approaches the su l voltage VCC).

Shortly before time T2, the sense component 125 (e.g., a sense amplifier) is activated to compare the voltage of sense node A (the voltage of the second plate 215 responsive t the change in tire voltage at the first plate 230) with the voltage of sense node B that is set to the reference: vol tage VREF. Due to the voltage of sense node A being greate than the voltage of the reference voltage VREF of sense node B, the sense component 125 drives sense node A to the supply voltage VCC and sense node B Co the ground. Accordingly , the sense component 1 5 amplifies the change in voltage detected at second plate 215. The supply voltage VC at sense node A represents the logic 0. state read from the memory cell 105. The sense component 125 can latch that logical state. For example, the detected state of memory cell 105 may then be output through column decoder 130 and output 135 (Figure \), Accordingly, the sense component 125 detects the increase in voltage at sense node A and thereby drives the voltage of digit line BL-TRUE to the supply voltage. [066] Having read the state at the first plate 230, the circuit 200 restores the initial state to the first plate 230, At time T2, the selection component 224 is deactivated with word line WL-COMP (e.g., driven to ground) to decouple the digit line BL-CQMP from, the first p te 230. As a -result, the. first plate 230 remains at the reference voltage VREF. If desired, the activation of she WL-COMP word line (and thus activation of select component 224) may be prolonged ' until at Time .3 as shown fey a dotted line. At time T3, driver.235 is activated again to drive the sense node A and thus the voltage of digit line BL-TRUE to reference voltage VREF. As a result, the coupled second plate 215 is also driven to reference voltage VREF. In turn, the change in voltage at the second plate 215 causes a voltage change at the first plate 230, which is no longer coupled to digit line BL-OO P. Accordingly, the initial ground charge juay he restored to the first plate 230. I.n some embodiments, the driver 235 may drive the voltage of digit line BL-TRUE to a negative voltage (e.g., - VREF), which may assist in driving the voltage at tire first plate 230 to ground if noises or interference exists in. the capacitor 205.

j067] At time T4, the selection component 220 is deactivated, with word line WL-TSUB (e.g., driven t ground) t decouple second plate 215 from the digit line BL-TRUE, and to complete ' the read operation. By decoupling the second plate 215 from digit line BL-TRUE. the voltage in the capacitor at first plate 230 and second plate 215 is preserved until the -next read or write operation for the memory cell 105

(068) As described above in Figures 4 and 5, the voltage at the second plate 215 changes in response: to the: voltage change t the first plate 230 when the word hue WL-COMP is -activated. The initial voltage at the second plate 215 may be any voltage that can be stored at the capacitor 30 and changed responsi ve to the voltage change at the first plate 230. For example. Figures 4 and 5 describe that the initial voltage .may be the reference voltage VREF. However, the voltage at the second plate may also be the supply voltage, ground, or a negative voltage (e.g., -VREF). The memory array 100 and example circuit 200. can be configured to operate with such voltages at the second plate 2.15 for the disclosed configurations and methods described herein, such as providing a reference voltage to the first plate 230 that, changes the voltage across the capacitor 230. ] The example voltages and signal timing described with reference to the read operations of Figures 3-4 have been provided for illustrative purposes, and are not intended to limit the scope of the present, disclosure. It will be appreciated thai the voltages and relative signal timing may be modified without departing from the scope of the present disclosure.

] Figure 6 is a timing diagram of various signals during a write operation according to an embodiment of the -disclosure, it should be noted that Figure 6 shows both of f¾st initial state, in which a memory cell to be written stores initially logic. "! ", and second initial state, m. which -memory cell to be written stores initially logic "0" and further shows both of first write state, in which new data of logic ' ' is written, and second write sate, in which new data of logic . "0" is written. The processes in write operation until ' Time T3 are the same as those of read operation except the word line WL-COMP is continued to be activated during. period between T2 and T3. If desired, however, the word Sine WL-COMP can be deactivated during that period,

] At Time T3, the driver 235 is activated to supply the sense node A an the bit line BL-TRUE with the reference voltage VREP. and the driver 23 is also activated with activating the WL-COMP line (and tints selection component 224). The driver 237 dins drives the BL-COMP line with the supply voltage VCC is case of the data to he written is logic "I " and with the ground voltage in ease of the data to be written is logic "0 , as shown in Fig. 6. At time T4, both the WL-COMP and WL-TRUE are deactivated to complete write operation.

] Figure 7 is a diagram depicting a cross-sectional side view of a memory array showing an example ' configuration for vertically stacked memory cells. The illustrated region of memory array 500 comprises comparative digit lines BL-COMP and BL- TRUE, with such comparative bitiine being vertically offset relative to another and connected to ' various circuitries. Circuitries may include a sense ' component (e.g., a sense amplifier 125) and drivers 235 and.25 ί (Figures 2 and 3) which may be placed in the same layer as digit line BL-TRUE as well as driver 237 (Figure 2) which may be placed in -the same layer as digit line BL-COMP. in some embodiments, these circuities may be between the digit line BL-TRUl and a semiconductor base 15 or may be incorporated into the semiconductor base 15. Although not shown, an iiiterlayer insulating film intervenes between digit line BL-TRUE of the memory array 500 and the semiconductor base 15, In ease where -the circuities 125, 235, 237 and 251 are incorporated or formed into the emicond ctor base 1 , a plurality of vias are forme in the interlayer insulating film to electrically connect: word lines and digit lines of the array 500 to the circuities.

f873j A pair of adjacent memory cells 12 and 12a are shown, with such adjacent memory cells being in a common column as one another within the memory array (i.e., being along a common hiiiine, with such bit!ne being comprised fey the comparative digit line BL-CQMP and BL-TRUB in combination). In some embodiments the memory cells 12 and 12a ma be referred to as substantially identical memory cells along a column, of a memory array, with die term "substantially identical" meaning that the memory ceils are identical to one another within reasonable tolerances of fabrication and measurement,

|07 j The memory cell 12 comprises transistors Ti and T2, with such transistors being along a first pair of wardlnies WL-COMP and WL-TRIJE. The adjacent memory- cell 12a comprises transistors Tla and T2a, with suc transistors being along a second pair of wordlin.es WL-CO P and Wt-TRl!B, A capacitor 38 is vertically between the transistors Tl and T2 of memory cell 12, and a similar capacitor 38a is vertically between t he transistors T l a and T2a of memory ceil 12a.

j075| The capacitors comprise first nodes 40/4Oa, second nodes 42/42a and capacitor dielectric materials 44/44a. Although the first nodes 40/40a are shown to be container- shaped and the second nodes 42/42a are shown to extend within such container shapes, in other embodiments the first and second nodes may have other configurations. For instance, the first and second nodes may have planar configurations:. In. the illustrated configuration the first nodes 40 40a may be referred to a outer nodes and the second nodes 42/42a -may be referred to as inner nodes.

[076] The semiconductor (for example, silicon} pillars -18/ 1 :8a extend ftoni comparaiive digit line BL-GOMP to the outer nodes 40/40a of capaci tors 38/38a,. and the semiconductor (for example, silicon) pillars 2Q/20a extend from the comparative digit line BL-TRUE ' to the inner nodes 42/42a of capacitors 38 3¾a.

10 7] The transistors Tl /Tla have first source/drain regions 28/28a extending to the outer nodes 4040a of capacitors 38 38a, and have second source drain regions 3O/30a extending to the comparative digit Sine BL-COMP. The transistors Tl/Tla. also have channel regions 26726a between the first and second source drain regions,. Gates 14/14a are along the channel regions aad offset from the channel regions by gate dielectric materials 22 22a. The transistors T27T2& have third source/drain regions 34/34a extending to the inner nod.es 42/ ' 42a of capacitors 38/38a > and ave fourth source/drain regions 36/36a extending to the comparative digit lin BL-THUE. Hie transistors T2 T2a also have channel regions 32/32a between, the third and fourth source/drain regions. Gates Ι6/Ί 6a .are along the channel regions and offset from the channel .regions by gate dielectric materials 24 24a, Gates 14 and 16 serve- as WL-COMP and WL~ TRUE of the first pair of wo.rd.li.nes, respectively,, and Gates 14a and 1 a .serves as WL- COMP and WL-TRUE of the second pair of wordlhies, respectively.

I The embodiment of FIG, 7 advantageous!? ena bies th transistors and capacitor of a 2T-1C memory cell to all be vertically slacked, which may enable the memory cells to be packed to high-levels of integration.

As has been discussed with reference to Figures 2-6, dat is read oat of from a selected memory cell through the BL-TRUE digit line and data is written into a selected memory cell through the BL-COMP digit line write data, signal. Accordingly, the BL~ CGMP digit line can be shared wi th a plurality of column ' blocks of memory array as shown in Figure 8, if these column blocks are subject to data read and -write operations exclusively. In figure 8, the BL-COMP digit line of. column block 80.1 is elongated over one or more oilier column blocks 802 to serve a its or their BL-COMPs. Further, the driver 23? {Figure 2) is used in common for ' those column blocks. Other components- re the same as those shown in Figure 2 and are thus indicated by the same reference numerals to. omit: their further descriptions ,

Figure 9 illustrates an example memory array 101 that supports vertically stacked memory cells in accordance with an embodiment of the present disclosure. The same constituents as: those of Figure 1 are denoted by the same reference numerals to omit further descriptions thereof hi Figure , th BL-COMP digit Sines are coupled in common to each other to receive a. bias voltage (a reference voltage VREF in this embodiment) from biasing component 144,. differently from figure 1. The BL-COMP lines may be thus formed as a plate instead of fomring them as indi vidual stripe lines.

Figure Ϊ 0 illustrates an example circuit 250 that includes a column of memory cells according to an embodiment of the disclosure, that may correspond to Figure 9, In Figure 10, the same constituents as those shown in Fi ure 2 are denoted by the same reference numerals to omit their further descriptions. The BL-COMP digit line of she Circuit 250 is coupled io driver 903 included, in the biasing component 144 (Figure 9). to receive the reference voltage VREF, differently ffom the circuit 200 of Figure 2. The BL-TRUE digit line and the sense node A of the circuit 250 are coupled to driver 901 generating the supply voltage VCC, or the ground voltage, or the reference voltage VREF, differently further froth the- circuit : 200 of Figure 2.

ji ' 79] With the configurations discussed with reference- to Figures 9 and Ϊ0, read and write operations are performed in accordance with a timing diagram of various signals shown in Figure 11.

j080j Prior to time TO, the drivers 901 and 903 precharge. the digit lines- BL-TRUE and BL-COMP digit lines to a reference voltage VREF. Accordingly, sense node A the voltage VREF of the precharged digit line BL-TRUE. Sense node B of the seme component 12S (not depicted in Figure 9) is als set to the reference voltage VREF, Although discussed in more detail later, the voltage .at the first plate 230 (W of memory ceil. 105 has the reference voltage VK.BF •irrespective of data stored therein. On the other hand, the second plate 215 (Vp?.) of the memor ceil 205 lakes the supply voltage in case of storing logic "0" and the ground in case of storin logic ** .1".

|08.ij At tints TO, the word line WL-COMP is activated to activate selection component 224 of a memory eel! 105 being accessed, while contmnaig to activate the driver 903. As a result, the digit line BL-COMP is coupled to first plate 230 of the •capacitor 205. As the voltage on the BL-COMP line and the first plate 230 are the 'substantially same as each other, no change occurs substantially at the second plate 215.

[082] At time T i„ the word line WL-TRUE is activated to activate · selection component 220 of a memory cell 105 being accessed, while deactivating the driver 901. As a result, the digit line BL-TRUE and the sense node A are coupled to second plate 215. The voltage of the second plate ' 2. " is coupled, to the sense node A of the sense component 125 through selection component 220 over digit line BL-TRUE. Because the sense node A {V A > had been precharged at the reference voltage VREF, the voltage at the second plate 215 is decreased from the supply voltage VCC and the voltage at the sense node A is increased from the reference voltage VREF in ease where the selected memor celt 105 stores the logic "I". hi case where fee selected memo cell stores logic "0", oa the contrary, the voltage at the second plate 215 is increased from the .ground and the voltage at the sense node A is decreased from the inference voltage VREF.

883 j Shortly before time T2, the sense component 125 (e.g., a sense amplifier) is activated to compare the voltage of sense node A (the voltage of the second plate 215) with the voltage of " sense node 8 that is set to the reference voltage VREF, Accordingly, the sense amplifier 125 changes the sense node A and the BL-TRUE digit hue up to the supply voltage VCC hi case of the logic *T S date, and up to the ground in case of the logic "0". Thus, the sense component 125 reads the data from the selected memory cell .and restores it to the same,

08 j In the data read operation, at time T3, the WL-COMP and WL-TRUE word 'lines are both deactivated to deactivate the select components 220 and 224. The read operation is thus completed.

085] In the data write operation, on the other hand, the driver 901. is activated again at time T3 to write new data into the selected memory cell. The driver 901. thus acti vated drives the BL-TRUE line to the supply voltage VCC is case of the new data being logic "1" or to the -ground i case of the - ' new data being logic "(Γ, At time T4, the WL-CQMP and WL-TRUE word lines are both deacti vated to deactivate the select components .220 and 224. The write operation is thus completed.

086} Figure 12 is diagram -depicting a cross-sectional side view of a memory array 550 showing an example configuration for -verticall -stacked memory cells according to an embodiment Of the- disclosure, in which the same constituents as those of Figure ? are denoted by the same reference numerals to omit their further descriptions. As shown and discussed wit reference to figures and 1.0, the BL~CQMP digit line is provided with VREF. Because the BL-COMP digit line is free from supplied with variable voltage, this line i formed as a conductive plate that serves as a plurality of BL-COMP lines. On the other hand, the BL-TRUE line is coupled to the sense component 125 including the sense amplifier 125 and the driver 901.

Θ87] The -methods and system described with reference to ' Figures 9 to 1 may allow for very short length for each dtgithne BL-TRUE, resulting in reducing total, digitiine capacitance and ' t u increasing the vo!atge swing obtained ftom the ceil ' capacitor during a ceil charge share with the digitlhie,

Θ88| Utilizuig the methods and system described herein, further. Figur 12 can include a driver that provides a reference voltage to digit line BL-COMP that eliminates the need for a vertical connection, along the vertically stacked memory ceils 12 and 12a. Accordingly, the configuration depicted in Figure 12 may be utilized to couple -the first plate to the digit line BL-COMP to provide a reference voltage to me first nodes 40/40a of the capacitor 38/3% and cause a voltage change at the second nodes 42/42a of the capacitor 38.eSa that is provided to a sense component 125 via the digit line BL-TRUE. The sense component may he formed ' in the semiconductor base 15 or between BL-T U ' E line and the base 5..

089] Figure 13 is a block diagram of a memory chip in a memory system, in accordance with an embodiment of the present disclosure. The memory chip 600 may be DRAM or non-volatile RAM integrated into a single semiconductor chip, for example, however, other devices may also he the memory chip 600 of the present disclosure. The memory chip 600 may be mounted on a memory module substrate, a mother board or the like (not shows). The memor chi includes a memory ceil array region 81 and a peripheral circuit region 82.

' 890} The memory cell array region 8.1 includes .a ' memory ceil array 83 including a plurality of batiks, each batik including a plurality of word lines, a plurality of digit lines, and a pluralit of memory cells arranged at intersections of the plurality of word lines and the plurality of digit lines. The memory cell array 83 may include, tneraory cells aa that previously described. Fo example, the memory cells of the memory' cell array 83 may include two transistors and a capacitor as previously described with reference to Figures 2A and 2B, and Figures 5 A and SB. The plurality of word lines and the plurality of digit lines may be as previously described, for example, -word, lines WL » COMP and WL-TROE, and the digit lines BL-COMP and BL-TRIIE. The selection of the digit line is performed by a plurality of column decoders 84 and the selection of the word line is performed by a plurality of row decoders 85. An array control circuit 86 is provided for selecting a bank of the memory cell array 83.

' 091] The peripheral circuit region 82 includes clock terminals 88, address terminals 89, command terminals 90, and data input/output (I/O) terminals (DQ) 99, For example, the data I/O terminals may handle eight-bit data, communication. Data input Output (I O) bufes 98 are coupled to the data input outpst terminals (DQ) 99 fe data accesses, such as read accesses and write accesses of memories. The data accesses between, the data I O buffer 98 and the memor cell array 83 may be executed by an amplifier circuit 97, For example, the amplifier circuit may include the sense components 125 previously described in Fig. 1. Thus,, the data is transferred between the amplifier circuit 97 and the data I/O buffer 98.

§92 j The address terminals 89 are supplied with address signals Α1.5-ΑΘ, bank address signals BA0-BA2, and column, address signals YL5-Y0, The hank address signals may he used for selecting a hank among the plurality of banks. The bank address signals are pro vided to an array control circuit 86 for selecting a bank as a bask selection signal.

093 j The command terminals 90 ma include chip select (7CS) pin for receiving a complementar CS signal, a row address, strobe (/EAS) pin for receiving a RAS signal, a column address strobe (CAS) pin for receiving CAS signal, a write enable (/WE) pin for receiving a WE signal and the like, A command decode 1 decodes command signals from the comman terminals 90 to receive various commands including a read -command and. a write command, and provides control signals responsive to the received commands to a chip control circuit 92. The command decoder 91. and/or chip control circuit. 92 may include the memory controller 1 0 previously described in Fig, 1 , and control the operation of the memory circuits.

094 j Accordingly, read data is read from a memory eel! In the memory cell array 83 designated by a row address and a column address, when the read command is issued and tile row address and the column address are timel supplied with the read command. The read data DQ is output from the data I/O terminals 99 via die amplifier circuit 97 and the dat I/O buffer 98. Similarly, write data. DQ is supplied to the data I/O terminals 99 via the data I/O buffer 98 and the amplifier circuit 97 to the memory cell array 83 and is written to the memory cell designated by a row address and a column address when the write command is issued and the row address and the column address are timel supplied with the write command.

Θ95] The clock terminals 88 may include clock pin CK and a clock enable (CKE) pin. An externa! clock signal CK can be supplied at the CK pin; and a clock enable (CKE) signal can be supplied at the CKE pin. The CKE signal may activate or deactivate internal clock circuits, input buffers and output dri vers, thus the CKE signal is part of a. command. The dock generator 87 reeei ves ike external clock signal CK and may -execute phase control to generate an internal clock signal based on the received external clock signal and the CKE signal Although not limited thereto, a DLL circuit can be used as the clock generator 87. The internal clock signal may be supplied various circuits., including the command decoder 91, the chi control circuit 92, the data I/O uffer 98, or the. like. The various circuits ma use the internal clock signal as a timing signal

[Θ96| The structures and architectures described above ma he incorporated into memory (e.g.. ? DRAM, SRAM., etc,) and/or otherwise may be utilized in ' electronic systems. Such electronic systems may be any of a broad range of systems, such as, for example, docks, televisions, ceil phones, personal computers, automobiles, industrial control systems, aircraft, etc .

| 97] From the foregoing it will be appreciated that, although- specific embodiments of the disclosure have been described herein for purposes of illustration, various modifications ' may be made without deviating from the spirit and scope of the disclosure. Accordingly, the disclosure is not limited except as by the appended claims.