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Title:
APPARATUSES AND METHODS FOR INTERLEAVED BCH CODES
Document Type and Number:
WIPO Patent Application WO/2018/022269
Kind Code:
A1
Abstract:
An example methods for interleaved BCH codes can include encoding a first plurality of portions of data using a first generator polynomial to obtain a plurality of respective BCH codewords. The method can include encoding an additional BCH codeword based at least in part on a second plurality of portions of data and the plurality of BCH codewords using a second generator polynomial. The method can include outputting the plurality of respective BCH codewords and the additional BCH codeword.

Inventors:
WU, Yingquan (825 Altaire Walk, Palo Alto, California, 94303, US)
Application Number:
US2017/040837
Publication Date:
February 01, 2018
Filing Date:
July 06, 2017
Export Citation:
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Assignee:
MICRON TECHNOLOGY, INC. (8000 SOUTH FEDERAL WAY, P.O. BOX 6BOISE, Idaho, 83707-0006, US)
International Classes:
H03M13/15; H03M13/27
Attorney, Agent or Firm:
GALLUS, Nathan J. (Brooks, Cameron & Huebsch PLLC,1201 Marquette Avenue South, Suite 40, Minneapolis Minnesota, 55403, US)
Download PDF:
Claims:
What is claimed is:

1. A method for interleaving BCH codewords, comprising:

encoding a first plurality of portions of da ta using a first generator polynomial to obtain a plurality of respective BCH codewords;

encoding an additional BCH codeword based at least in part on a second plurality of portions of data and the plurality of BCH codewords using a second generator polynomial; and

outputting the plurality of respective BCH codewords and the additional BCH codeword.

2. The method of claim 1 , wherein the plurality of respective BCH codewords and the additional BCH codeword are encoded by substituting an integrating coefficient with a polynomial of

3. The method of claim 1 , wherein encoding the plurality of respective BCH codewords comprises encoding a plurality of integrated interleaved BCH codewords.

4. The method of claim 1 , wherein encoding the additional BCH codeword comprises encoding a generalized integrated interleaved (GII) codeword.

5. The method of claim 4, wherein encoding the plurality of respective BCH codewords comprises encoding the plurality of respective BCH codewords in a first encoding layer and encoding the additional BCH codeword comprises encoding the additional BCH codeword in a sub-layer of the first encoding layer.

6. The method of claim 1 , wherein encoding the plurality of respective BCH codewords comprises encoding the plurality of respective BCH codewords in a first encoding level and encoding the additional BCH codeword comprises encoding the additional BCH codeword in a second encoding level.

7. The method of any one of claims 1 to 6, comprising generating a second additional BCH codeword and a third additional BCH codeword associated with the second encoding level, wherein the additional BCH codeword is a first additional BCH codeword.

8. The method of claim 7, comprising correcting a number of interleaves of codewords, wherein the first additional BCH codeword is configured to correct a greater number of errors in at least one of the number of interleaves than the plurality of respective BCH codewords.

9. The method of claim 8, wherein the second additional BCH codeword is configured to correct a greater number of errors in at least one of the number of interleaves than the plurality of respective BCH codewords and the first additional BCH codeword.

10. The method of claim 9, wherein the third additional BCH codeword is configured to correct a greater number of errors in at least one of the number of interleaves than the plurality of BCH codewords, the first additional BCH codeword, and the second additional BCH codeword.

11. A method for decoding, comprising:

determining a number of BCH code syndromes of a plurality of nested integrated interleaved (II) BCH codewords;

locating at least one interleave of the plurality of nested II BCH codewords based on a generated error locator polynomial; and

correcting the at least one interleave.

12. The method of claim 11, comprising, prior to determining the number of BCH code syndromes of the plurality of nested II BCH codewords:

determining a number of BCH code syndromes of a plurality of II BCH codewords;

generating a prior error locator polynomial;

locating at least one interleave of the plurality of II BCH codewords based on the prior error locator polynomial; and

in response to a number of interleaves of the plurality of II BCH codewords being uncorrectable independent of using the plurality of nested II BCH codewords, performing the determination of the number of BCH code syndromes of the plurality of nested II BCH codewords.

13. The method of claim 12, comprising, in response to the number of interleaves of the plurality of II BCH codewords being correctable:

correcting the number of interleaves that include an error; and saving the corrected number of interleaves that include the error.

14. The method of claim 11, comprising generating the error locator polynomial.

15. The method of claim 11, wherein the error locator polynomial is generated using a Ber!ekamp method and additional syndrome inputs.

16. The method of any one of claims I I to 15, comprising determining higher order syndromes through a recursive linear-feedback shift registry (LFSR).

17. The method of claim 16, comprising updating at least one of the higher order syndromes based on the determined higher order syndromes determination.

18. An apparatus, comprising:

a controller; and

an encoder, wherein the encoder is configured to:

encode a plurality of portions of data using a first generator polynomial to obtain a first plurality of respective BCH codewords of a first encoding layer;

encode a second plurality of nested BCH codewords based at least in part on an additional plurality of portions of data and the first plurality of respective BCH codewords using a second generator polynomial, wherein the second plurality of nested BCH codewords are a sub-layer of the first encoding layer.

19. The apparatus of claim 18, wherein the encoder empoys a polynomial of to encode the first plurality of respective BCH codewords and the second plurality of nested BCH codewords.

20. The apparatus of claim 18, wherein the encoder is further configured to encode the second plurality of nested BCH codewords with fewer codewords than the first plurality of respective BCH codewords.

21. The apparatus of any one of claims 18 to 20, wherein the encoder is further configured to encode the first and the second plurality by applying a linear-feedback shift registry encoding.

22. The apparatus of claim 21 , wherein the encoder is further configured to determine a parity polynomial

23. An apparatus comprising:

a controller; and

a decoder coupled to the controller, wherein the controller is configured to operate the decoder to:

determine a plurality of syndromes associated with a plurality of integrated interleaved (II) BCH codewords;

locate at least one interleave of the plurality of II BCH codewords based on a generated first error locator polynomial; and

in response to a number of interleaves of the plurality of II BCH codewords being uncoiTectabie, determine a number of BCH code syndromes of a plurality of nested integrated interleaved (II) BCH codewords;

generate a second error locator polynomial;

locate at least one interleave of the plurality of nested II BCH codewords based on the second error locator polynomial; and

correct the at least one interleave.

Description:
Apparatuses and Methods for Interleaved BCH Codes

Technical Field

[0001] The present disclosure relates generally to semiconductor memory and methods, and more particularly, to apparatuses and methods related to interleaved BCH codes.

Background

[0002] Memory devices are typically provided as internal,

semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data (e.g., host data, error information, etc.) and includes random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, read only memory (ROM), Electrically Erasable Programmable ROM (EEPROM), Erasable Programmable ROM (EPROM), and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), among others.

[0003] Memory devices can be combined together to form a storage volume of a memory system such as a solid state drive (SSD). A solid state drive can include non-volatile memory (e.g., NAND flash memory and NOR flash memory), and/or can include volatile memory (e.g., DRAM and SRAM), among various other types of non-volatile and volatile memory.

[0004] An SSD can be used to replace hard disk drives as the main storage volume for a computer, as the solid state drive can have advantages over hard drives in terms of performance, size, weight, ruggedness, operating temperature range, and power consumption. For example, SSDs can have superior performance when compared to magnetic disk drives due to their lack of moving parts, which may avoid seek time, latency, and other electromechanical delays associated with magnetic disk drives. [0005] Memory is utilized as volatile and non-volatile data storage for a wide range of electronic applications. Non- volatile memory may be used in portable electronic devices, such as laptop computers, portable memory sticks, digital cameras, cellular telephones, portable music players such as MP3 players, movie players, and other electronic devices. Memory cells can be arranged into arrays, with the arrays being used in memory devices.

[0006] To ensure data integrity, error correction codes can be used to detect and correct certain numbers and/or types of errors in the data. One type of error correction involves integrated interleaved codes. Integrated interleaved codes can be systematic codes (i.e., input data is included or otherwise embedded in the encoded data) and can generate multiple codewords, each of which can be at a particular level. Powerful error correction may be desired but balanced against latency, throughput, and/or power constraints such as those imposed by portable electronic devices.

Brief Description of the Drawings

[0007] Figure 1 is a block diagram of a system for implementing interleaved BCH codes in accordance with a number of embodiments of the present disclosure.

[0008] Figure 2 illustrates an example of a diagram for integrated interleaved encoding in accordance with a number of embodiments of the present disclosure.

[0009] Figure 3 illustrates an example of a diagram for generalized integrated interleaving of BCH codes in accordance with a number of embodiments of the present disclosure.

Detailed Description

[0010] The present disclosure includes apparatuses and methods related to interleaved BCH codes. A number of methods can include encoding a first plurality of portions of data using a first generator polynomial to obtain a plurali ty of respective BCH codewords. The number of methods can include encoding an additional BCH codeword based at least in part on a second plurality of portions of data and the plurality of BCH codewords using a second generator polynomial. The number of methods can include outputting the plurality of respective BCH codewords and the additional BCH codeword.

[0011] In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how one or more embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure. As used herein, "a number of a particular thing can refer to one or more of such things (e.g., a number of memory devices can refer to one or more memory devices).

[0012] The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, 220 may reference element "20" in Figure 2, and a similar element may be referenced as 320 in Figure 3. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, as will be appreciated, the proportion and the relative scale of the elements provided in the figures are intended to illustrate certain embodiments of the present invention, and should not be taken in a limiting sense.

[0013] Figure 1 is a block diagram of an apparatus in the form of computing system 101 for implementing interleaved BCH codes in accordance with a number of embodiments of the present disclosure. As used herein, the computing system 101 can include a host 102 and a memory device 104. The memory device 104 can include a host interface 106, a controller 108, and a memory array 1 10.

[0014] The host 102 can be coupled (e.g., connected) to memory device

104, which includes the memory array 1 10. Host 102 can be a host system such as a personal laptop computer, a desktop computer, a digital camera, a smart phone, or a memory card reader, among various other types of hosts. Host 102 can include a system motherboard and/or backplane and can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry). The system 101 can include separate integrated circuits or both the host 102 and the memory device 104 can be on the same integrated circuit. The system 101 can be, for instance, a server system and/or a high performance computing (HPC) system and/or a portion thereof. Although the example shown in Figure 1 illustrates a system having a Von Neumann architecture, embodiments of the present disclosure can be implemented in non-Von Neumann architectures (e.g., a Turing machine), which may not include one or more components (e.g., CPU, ALU, etc.) often associated with a Von Neumann architecture.

[0015] For clarity, the system 101 has been simplified to focus on features with particular relevance to the present disclosure. The memory array 1 10 can be a hybrid memory cube (HMC), processing in memory random access memory (PIMRAM) array, DRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash array, and/or NOR flash array, for instance. The array 110 can comprise memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines. Although a single array 110 is shown in Figure 1, embodiments are not so limited. For instance, memory device 104 may include a number of arrays (e.g., a number of banks of DRAM cells).

[0016] The controller 108 can be coupled to the host interface 106 and to the memory 1 10 via a plurality of channels (not shown) and can be used to transfer data between the memory system 104 and a host 102. The host interface 106 can be in the form of a standardized interface. For example, when the memory system 104 is used for data storage in a computing system 101 , the host interface 106 can be a serial advanced technology attachment (SAT A), peripheral component interconnect express (PCIe), or a universal serial bus (USB), among other connectors and interfaces. In general, however, the host interface 106 can provide an interface for passing control, address, data, and other signals between the memory system 104 and a host 102 having compatible receptors for the host interface 106. [0017] The controller 108 can include write logic 112 and read logic 114.

Controller 108 can cause data to be written to memory array 110 and/or additional memory locations and can cause data to be read back from the memory array 1 10. Prior to storing data in the memory array 1 10, data can be encoded using an integrated interleaved encoder 1 16. When the data is read from the memory array 1 10, the data can be read from the memory array 1 10 and decoded using an integrated interleaved decoder 1 18. In some examples, a read back from the memory array 1 10 can have noise or errors in the data and using an integrated interleaved code can allow the read-back errors to be corrected.

[0018] To achieve better error protection over an array of interleaves within a single cluster or block of data, a two-level interleaved scheme can be used and a generalized interleaved scheme can provide nonuniform redundancy (see Figure 3). An array of interleaves refers to data arranged in a

noncontiguous manner. Interleaving can refer to dividing memory into small chunks and used as a high-level technique to solve memory isssues for motherboards and chips. In this way, interleaving can control errors with particular methods. The nonuniform redundancy is provided by using extra check symbols that are shared among all the interleaves and used by interleaves with errors beyond their decoding distance. However, this construction may not provide protection to the shared redundancies. Instead, another code can be required to protect these shared check symbols from errors. The integrated interleaving (II) coding scheme can provide an improvement of error correction by creating shared redundancy that is protected by the first-layer code.

Specifically, the II coding scheme nests a set of m equally protected interleaves with v (v < m) more powerful codewords in the nested layer which is a subcode of the first layer. Specifically, let be defined over the Galois field GF(q) such that An II code is defined as follows:

where v < m < q. The above defined II code enables correction of up to v interleaves that are failed by self-decoding. Self-decoding refers to a decoding that is performed using codewords associated with a particular portion of data without referencing codewords at a higher level. For example, a lower level codeword (e.g., codeword 334-0 in figure 3) can decode a portion of data (e.g., data aox 320-0) without referencing higher level codewords (e.g., such as codeword Co 342 and/or codeword C3 346-3).

[0019] A generalized two-layer II coding scheme allows unequal protection in the nested layer. Specifically, let o be defined over

the Galois field such that

A generalized integrated interleaved (GII) code is defined as

[0020] where v < m < q.As described further below r , the proposed definition illustrates an implementation for both encoder and decoder. Some benefits can include a GII codeword exhibiting larger minimum distance and more powerful performance. When up to v component words are failed by self- decoding, it can be highly unlikely that all failed words have equal number of errors. Instead, the worst corrupted word can entail the largest correction power, whereas the least corrupted word can entail the smallest correction power.

[0021] The GII scheme is similar to a generalized concatenated (GC) scheme in view of theoretical performance and shared redundancies on top of the first layer self-correction. The main difference and advantage of GII codes can bethat their shared redundancies are also embedded in, and thus protected by, the first-layer interleaves, whereas for GC codes, the shared redundancies may not be. The nested layer codes form a subcode order and are subcodes of the first- layer code (see Equation (2)) in GII codes, whereas the inner (but not outer) codes forms a subcode order and are used to encode each symbol of outer codes in GC codes. The nested layer codes and the first-layer code can share the same field and code length in GII codes, however, the outer codes can be defined in a larger field and thus have much larger length than the inner codes in GC codes. As a consequence, the implementation and architecture of GII codes can be different from the schemes of the GC codes.

[0022] In some embodiments, the size of a flash page is 16 kilobyte

(KB) + 8—12% overhead, and can continue increasing in order to increase capacity while maintaining throughput (note data for a flash page is programmed altogether). On the other hand, a data sector size is currently 4KB, therefore, multiple sectors must be buffered until a page is filled before programming. Binary b (BCH) codes have been extensively employed to tackle bit corruptions caused by retention. The GII-BCH scheme does not cause write latency, and moreover, each sector can be read out independently under normal conditions (meaning each sector is correctable by the first layer self-decoding). In some embodiments, formal efficiency can be traded off with power consumption. In previous approaches, a data sector was in the form of 512B initially, then shifted to 4KB, and is gradually moving to 8KB. The format efficiency found in longer code lengths diminishes after 2KB for prevalent coding schemes, while circuit complexity and power consumption roughly increases linearly with code length. To this end, GII codes serve as an alternative to be more complex but also more efficient than simple interleaves, on the other hand, less complex but also less efficient than a single code.

[0023] For various potential applications of II/GII codes, it can be beneficial to make the miscorrection negligible for the interleave self-decoding, since it enables decoding of each interleave independently under normal operation where the noise level is below the error correction capability. On the other hand, this may not be a stringent condition to meet. For Reed Solomon (RS) or BCH codes with relatively large minimum distances, the miscorrection probability is below the level of practical tolerance. This also significantly simplifies the nested decoding and the corresponding performance analysis. Also, in some approaches, decoding methods proposed for II/GII codes are can be computationally inefficient, in two perspectives, where the two perspectives include a syndrome computation and key-equation-solver. A syndrome refers to multiplying a parity check matrix times a particular vector. For example, codewords of a code have a syndrome of zero when the codeword include no errors and if all syndromes are zero, decoding can be completed. The previous method approaches can rebuild corrupted nested interleaves and then compute their syndromes. This can be more efficiently achieved by computing syndromes on the constructed nested (corrupted) interleaves only on the first time while updating syndromes by removing contributions from the corrected interleaves at each iteration of decoding attempt. Moreover, syndromes for existing uncorrectable interleaves can remain valid and each subsequent attempt will incrementally add high order syndromes in order to correct the previously uncorrectable interleaves. Additionally, when the method is deployed to decode interleaves, the output of the BM method can be readily reused in the next iteration by incorporating extra syndromes.

[0024] Figure 2 illustrates an example of a diagram 203 for integrated interleaved encoding in accordance with a number of embodiments of the present disclosure. The diagram 203 includes a plurality of data polynomials such as ao(x) 220-1 , a 5 (x) 220-2, a 2 (x) 220-3, and a 3 (x) 220-4 (herein referred to in combination as 220). The diagram 203 includes a plurality of encoders 222-1, 222-2, 222-3, 226 (herein referred to in combination as 222, 226), and a plurality of codewords 234-1, 234-2, 234-3, 236 (herein referred to in combination as 234, 236). Encoders 222-1, 222-2, 222-3 use a plurality of generator polynomials (e.g., g(x)) to encode the plurality of data polynomials 220. Cyclic codes, including BCH codes, can be systematically encoded by a simple linear- feedback-shift-register (LFSR) circuit. Specifically, an LFSR encoder systematically encodes a data polynomial a(x) 220 to a systematic codeword c(x) 234, 236 through iteratively dividing -x r a(x) by corresponding generator polynomials g(x). In the equation -x r a(x), r denotes parity length, and a(x) denotes a message polynomial. A systematic codeword includes an original data polynomial a(x) 220 (e.g., input data or data prior to encoding) and a resulting remainder polynomial p(x), where the LFSR encoding is illustrated by:

A systematic codeword can be indexed in the reverse in a polynomial representation illustrated by

[0025] In at least some embodiments, systematic encoding includes input data being embedded in encoded data (e.g., as codewords) and becomes output data. In at least some examples with a single nested word, i.e., v=l, input data can be in a beginning portion of a codeword. Redundant data (e.g., bits, bytes and/or symbols) can be added by systematically encoding using generator polynomials go(x) and gi(x), where go(x) divides gi(x). As illustrated in Figure 2, the encoders 222-1 , 222-2, 222-3 are configured to to respectively input and systematically encode input data ai(x), a2(x), as(x) using go(x). Codewords are correspondingly output by systematic encoders 222-1 , To obtain the remaining codewords, a systematic encoding with respect to generator polynomial gi(x) is performed. Data polynomials a o(x) 220- 1 through are correlated with a n-ro delay 229 and input to

adder 224 which outputs a sum of the input. The n-ro delay 229 refers to deferring encoding until a clock number n-ro, which is related to a delay unit of n-ro. The delay unit refers to a shift-align of ao(x) with remaining input data

, noting that ao(x) is shorter by n-ro bits. The sum in turn

becomes input to a multiplexer 232- 1. In addition, additional data (e.g., multiplexing with "0") 231 is input into multiplexer 232- 1. Output data of multiplexer 232- 1 becomes input data for encoder 226 which systematically encodes the sum using gi(x) and outputs an intermediate portion of data.

[0026] In at least one embodiment, data polynomial a0(x) 220-1 is received by a multiplexer 232-2 as a first input of data. A second input of data into the multiplexer 232-2 is from adder 230. Adder 230 receives as input redundant data output from encoder 226, and inverted or negative redundant data that are output data from encoders 222- 1 , 222-2, 222-3, respectively. A select signal (not illustrated) is configured to select an appropriate input at an appropriate time from each correponding encoder. Although some of the equations and/or descriptions are associated with a particular number of encoders and/or data inputs and outputs, embodiments are not so limited.

[0027] In some previous approaches, a systematic encoding method can be implemented for binary BCH code for a particular case where This is due to coefficients given in equation 3 being valid only with b = 0. In the following description, a generalized integrated interleaving encoding method for BCH codes is described (where In some embodiments, an integrating coefficient is substituted, say , by its associated binary polynomial

where a denotes a primitive element in that is defined by a primitive

polynomial

A primitive element refers to a generator of a multiplicative group of a finite field GF(q). For example, a in the set of GF(q) is called a primitive element if it is a primitive (q-1) root of unity in GF(q). This means that all non-zero elements of GF(q) can be written as a 1 for some (positive) integer /.

[0028] A t—correcting BCH code defined over the Galois

field has the following generator polynomial

where LCM denotes "the least common multiple", and m^x) denotes the minimal (binary) polynomial to contain the root be binary BCH codes satisfying

Since the connection matrix is non-singular, the above equality indicates

Therefore, ( ) 0 1 ll di id ( ) We note from the above

proof that, unlike a GII- Reed Solomon (RS) code whose minimum distance is precisely determined, the minimum distance of a GII-BCH code is loosely bounded. Following the convention of BCH characterizations, w e define the designed minimum distance, denoted by for a GII-BCH code as

[0029] In at least one embodiment, a systematic encoding method which is modified is described below. For example,

satisfying:

truncates a polynomial a(x) to keep its upper terms starting with power

[0030] An example encoding method can include the following:

[0031] Figure 3 illustrates an example of a diagram for generalized integrated interleaving of BCH codewords in accordance with a number of embodiments of the present disclosure. Figure 3 illustrates an example of GII- BCH codewords in an example flash memory. A plurality of data portions ao(x) 320-0 to a7(x) 320-7 are each 2 KB in length. Each of the plurality of data portions ao(x) 320-0 to a7(x) 320-7 are associated with a plurality of portions of parity data po(x) 340-0 to ρ7(χ) 340-7. The plurality of portions of parity data po(x) 340-0 to p7(x) 340-7 can each be a particular length. For example, a 0 th parity data po(x) 334-0 can be 204B in length, a 1 st partly data pi(x) 340-1 can be 166B in length, a 2 nd parity data p 2 (x) 340-2 can be 150B in length, and a 3 rd through 7 th parity data p:,(x) 340-3 to p7(x) 340-7 can each be 138B in length. While, in this example, the 0 th parity data po(x) 340-0 is 204B in length, embodiments are not so limited. For example, any of the illustrated portions of parity data could be 204B in length with at least one of the portions of parity data being the particular length and so forth for each of the illustrated lengths. A plurality of codewords co(x) 334-0 to c 7 (x) 334-7 include the plurality of data portions ao(x) 320-0 to a 7 (x) 320-7 and the plurality of portions of parity data po(x) 340-0 to p 7 (x) 340-7.

[0032] As illustrated at the bottom of Figure 3, a 4KB user data sector

(e.g., user data sector) 335 can be divided into 2 BCH codewords and a 16KB (with additional parity overhead) flash page contains 8 BCH codewords. For example, codeword and c 6 (x) are 4KB in length and make up one user data sector 335 and codewords C to co(x) are 16KB in length and include 8 BCH codewords. The 16KB section includes 4 user data sectors. To use a 4KB data portion, each BCH interleave encodes 2KB data with different parity length. This results in different interleave length. In this regard, GII-BCH coding allows for different interleave length without affecting the proposed encoder and/or decoder.

[0033] A first layer (e.g., first level) integrated interleaved (II) codeword (described above and also referred to herein as interleaves) Co 342 (illustrated as to illustrate that the II codeword corresponds

to each codeword 334-0 to 334-0 being in the set of Co 342) includes an

integrated interleaving (II) of the plurality of codewords co(x) 334-0 to c 7 (x) 334-7. The II codeword Co 342 has an error-correction ability indicated by t corresponding to each codeword 334. For example, the II codeword Co has a 1=13 for each of the plurality of codewords co(x) 334-0 to c 7 (x) 334-7. This t=73 indicates that the II codeword Co 342-0 can correct up to 73 errors for codewords co(x) 334-0 through c 7 (x) 334-7. Since the II codeword Co 342 includes an integrated interleaving of the plurality of codewords co(x) 334-0 to c 7 (x) 334-7, a redundancy is created. In this way, the II codeword Co 342 can protect any of the plurality of codewords co(x) 334-0 to c 7 (x) 334-7, as long as none of the errors per codeword exceeds 73 (as /=73 for the II code).

[0034] In response to at least one of the plurality of codewords co(x)

334-0 to c 7 (x) 334-7 including more than 73 errors, in this example, a nested generalized integrated interleaved BCH code from a plurality of nested generalized integrated interleave (GII) BCH codewords Ci 346-1, C2 346-2, C3 346-3 can be used to correct the errors. The plurality of nested generalized integrated interleave (GII) BCH codewords C1 346-1 , C 2 346-2, C 3 346-3 are generated by a corresponding adder 344-1, 344-2, 344-3 that sums the II code including interleaved data from each of the plurality of codewords co(x) 334-0 to c 7 (x) 334-7. The plurality of GII codewords Ci 346-1 , C 2 346-2, C 3 346-3 are a second layer or a sub-code of the first layer of code (e.g., II codeword Co 342).

[0035] Nested GII BCH codeword refers to a codeword that is part of a nested layer, as described above. The nested codeword is generalized in that it includes data from each of the plurality of codewords co(x) 334-0 to c7(x) 334-7 and not just a portion of them. For example, in response to a codeword including up to 79 errors, nested GII BCH codeword C i 346-1 can correct the up to 79 errors (e.g., t=79) within an interleave and therefore can correct the 78 errors. Similarly, nested GII BCH codeword C 2 346-2 can correct up to 88 errors (e.g., t=88) within an interleave and nested Gii BCH codeword C3 346-3 can correct up to 108 errors (e.g., t=108) within an interleave. Therefore, the II BCH codeword 342 can correct up to 73 errors for each of the plurality of codewords co(x) 334-0 to c 7 (x) 334-7 and at least one of the plurality of nested GII BCH codewords can correct each of 79 errors, 88 errors, and 108 errors, respectively. In response to an interleave including more than 108 errors, a failure would occur. For example, nested GII BCH codeword C i 346-1 could correct 108 errors and any errors over that would cause the failure. In response to two or more interleaves including more than 88 errors, a failure would occur. For example, nested GII BCH codeword C i 346-1 could correct one interleave including more than 88 errors (and up to 108 errors) but a second interleave with more than 88 errors could not be corrected. Further, in response to three or more interleaves including more than 79 errors, a failure would occur. Furthermore, in response to four or more interleaves including more than 73 errors, a failure would occur.

[0036] In some previous approaches, each portion of user data that is

2KB in length can be protected by a BCH code with t ranging from 60 to 100. If a t of 80 is assumed, the code length lies between 2 14 to 2 15 , therefore, the code is defined in the field of GF(2 15 ). The length of parity overhead is 15 x 80 = 1200 bits. In at least one embodiment described herein, a sector failure rate can be maintained below l e-12. Herein, this criterion can be used such that the (flash) page failure rate is below le-12. With simple interleaved 8 BCH codewords, a raw bit-error-rate (RBER) of 1.7e-3 can be achieved. Note the length of a user data sector is fixed to 4KB, therefore, each interleave within a codeword varies slightly due to different parity length. Therefore, v = m— 1 = 7 achieves the lowest RBER of 2.9e-3. However, it also suffers the highest and non-negligible invocation rate of 0.234, that is, nearly one out of four reads fails by self-decoding and reads an extra three sectors for nested decoding. Its random read throughput is degraded to , which can be undesirable. In

contrast, having v = 3 can achieve a great trade-off. It enables a tolerance

RBER of lower than a previous interleaved method,

while suffering merely in random read throughput.

[0037] A method for decoding binary BCH codes by incorporating a special syndrome property can include:

which yields zero discrepancies at even iterations of the method. One example of a method for decoding binary BCH codes by incorporating a special syndrome property can include a simplified version of a Berlekamp-Massey method referred to as a simplified Berlekamp method. The method can perform t iterations. Similarly, the following updating method can be used to

incrementally update the error locator polynomial utilizing the preceding results:

[0038] In existing decoding methods, those syndromes can be computed from scratch. The following lemma demonstrates an alternative, and much more efficient approach.

Lemma 2 Let c be a transmitted codeword and y the received word. If there are e < t errors and let A(x) be the corresponding error locator polynomial, then the higher order syndromes can be computed

recursively through the follo wing LFSR

The decoding method is described below.

(b) Apply the updating method with extra inputs to produce

new error locator polynomial

(c) Let /' be the index set of newly corrected interleaves

(no interleave is newly corrected) or

(it fails to produce extra higher order syndromes) then declare failu re.

(all remaining interleaves are corrected) then return the corrected codeword. (d) For each compute higher order syndromes through the recursive LFSR (25). Update higher order nested syndromes through

[0039] The generalized integrated interleaving scheme for binary BCH codes described herein can provide a lower bound on the minimum distance. The encoding and decoding methods described herein provide for an improved distributed enviromnents where interleaves are distributed into different physical units and self-decoding is sufficient under normal operation condition.

[0040] Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure, it is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combination of the above embodiments, and other embodiments not specifically described herein will be apparent to those of skill in the art upon reviewing the above description. The scope of the one or more embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.

[0041] In the foregoing Detailed Description, some features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.