APPARATUSES AND Mjm OPS FOR SETTING A IIX C O ADJESTERTOlTMPiWViNC CLOCK Di - C Y<;i .E

CE0S -REFEKENCE.T0_RELATED _:, APPyCA.XiON

0011 This application claims the filing benefit of CIS. Provisional Application No.

62/677,585, filed Ma 29, 2018. This application is incorporated by reference herein in its entirety and for all purposes.

BACKGROUND

[662] Semiconductor memories are used in many electronic systems to store data that may be retrieved at a later time. As the demand has increased for electronic systems to fee faster, have greater data capacity, and consume less power, semiconductor memories that may be accessed faster, store more data, and use less power have been continually developed to meet the _: changing needs. Part of the development includes «seating new specifications for controlling and accessing semiconductor memories, with the changes in the specifications from one generation to the next directed to improving performance of the memories in the electronic systems

{#03} Semiconductor memories are generally controlled by providing the memories with commands, memory' addresses, and clocks. The various commahds, addresses, and clocks may he provided by a me ory' controller, for example. The commands may control the semiconductor memories to perform various memory operations, for example, a read operation to retrieve data from a memory, and a write operation to store data to the memory. Data may be provided between the controller and memories with known timing relati ve to recei pt by the memory of an associated command.

j®04| With newly developed memories, the memories may be provided with system clocks that are used for timing the commands an addresses, for example, and further provided wi th defer clocks that are used for timing of read data provide by the: memory and for timing of write data provided to the memory. The memories may also provide clocks to the controller for timing provision of data provided to the controller.

|lRi5f The external clocks provided to the memories are used to provide internal clocks that control the timing of various internal c ircuits during a memory operation. The timing of the interna! circuits during memory operation may he critical, and deviations in the timing of the clocks may cause erroneous operation. An example deviation in the timing of the clocks may be duty cycle distortion _» that is, deviation from a 50% duty cycle,

[006] Memories may includ duty cycle adjuster circuits that can be used to adjust: duty cycle of internal clocks that are generated front the external docks. The duty cycle adjuster circuits may be set to a seting that adjusts the duty cycle of the internal clocks to improve duty cycle. However, the duty cycle adjustment provided by the duty cycle adjuster circuits may not improve duty cycle sufficiently unless the duty cycle adjuster circuits are set accurately.

SUMMARY

{#07} Apparatuses and methods for setting a duty cy er adjuster for improving ock duty cycle am disclosed . I an aspect of the disclosure, a method includes issuing a first plurality of commands to a memory to perform a first plurality of duty cycle monitor sequences and issuing a second pluralit of "commands: to the memory to perform a second plurality of duty cycle monitor sequences. The first plurality of duty cycle monitor sequences are to identify a first duty cycle adjuster code having first duty cycle results that are indeterminate and to furt er identify a second duty cycle adjuster code having second duty cycle results that are determinate, wherein ihe second duty cycle adjustor code is one step greater than the first duty cycle adjuster code. The second plurality of duty cycle monitor sequences are to identify a third duty cycle adjuster code having third duty cycle results that are indeterminate and to further identify a fourth duty cycle adjuster code having fourth duty cycle results that are determinate, wherein the fourth duty cycle adjuster code is one step less than the third duty cycle adjuster code. The duty cycle adjuster code is set to an intermediate step between the first duty cycle adjuster code and the third duty cycle adjuster code.

[008] in another aspect of the disclosure, a method incl udes issuing' a first plurality of commands to a memory t perform a first plural it of duty cycle moni tor sequences and issuing a second plurality of commands to the memory to perform a second plurality of duty cycle monitor sequences. The first plurality of dut cycle monitor sequences ate to identify a first du ty cycle adjuster code having first duty cy cle re u Its that are determinate and that border a first indeterminate duty cycle adjuster code having first indeterminate duty cycle results. The second plurality of duty cycle monitor sequences are to identify a second duty cycle adjuster code having second duty cycle results that are determinate and that border a second indeterminate duty eyeie adjuster code haying second indeterminate duty cycle: results. The duty cycle adjuster code is set to an intermediate step between the first duty s> cSe adjuster code and the second duty cycle adjuster code. jjtKblj In another aspect of the disclosure a method includes adjusting a value of a duty cycle adjuster circuit setting until an upper boundary and a lower boundary of an duty cycle monitor offset is identified, and setting the duty cycle adjuster circuit setting to an intermediate circuit setting in the duty cycle monitor offset

jMOj in -another aspect of the disclosure _* an appar tus includes a memory, a co mand/addfess bus, a data bus, a clock bus, and a memory controller coupled to the memory through the command/address bus, the data bus, and the clock bus. The memory controller is configured to issue a first plurality of commands to a memory to perform a first plurality of duty cycle moni tor sequences and issue a second pl urality of commands to the memory to perform a second plurality Of duty cycle monitor sequences. The first luralit ' of duty cycle monitor sequences are to identi ty a first duty cycle adjuster code having first doty cycle results that are indeterminate and to further identit a second duty cycle adjuster code having second duty cycle results tha are determinate, wherein the second duty cycle adjuster code is one step greater than the first doty cycle adjuster cede. The second plurality of duty cycle monitor sequences are to identify a third dut cycle adjuster code having third duty cycle results that are indeterminate and to further identify a fourth duty cycle adjuster code having fourt duty cycle results that are determinate, wherein the fourth duty cycle adjuster code is one step less than the third duty cycle adjuster code. The duty cycle adjuster code is set to an intermediate step between the first duty cycle adjuster code and the third dut cycle adjuster code,

jtl l j In another aspect of the disclosure, an apparatus includes a memory, a command/address bus, a data bus, a clock bus, and a memory controller coupled to the .memory through the com an /address bus, the data bus, and the clock bus. The memory controller is configured to issue a first plurality of commands to a memory to per form a first plurality of duty cycle monitor sequences and issue a second plurality of commands to the memory to perform a second plural tty of dut cycle monitor sequences. The first pluralit of duty cycle monitor seq ences are to identify a first duty cycle adjuster code having first uty cycle results that are determinate and that border a first indeterminate duty cycle adjuster code having first indeterminate duty cycle results. The second plurality of duty cycle monitor sequences are to identify a second duty cycle adjuster code having second duty cycle results that are determinate _. and that border a second indeterminate duty cycle adjuster code having second indeterminate duty cycle results. The duty cycle adjuster code is set to an intermediate step between the first duty cycle adjuster code and the second duty cycle adjuster code.

|012} In another aspect of the disclosure, an apparatus includes a memory, a command- ^' address bus, a data bus, a clock bos, and a memory·’ controller coupled to the memory through the commasd/address bos, the data bus, and the dock bus. The memory controller is configured to adjust a value of a duty cycle adjuster circuit setting until an upper boundary and a lower boundary of an duty cycle monitor offset is identified, and set the duty cycle adjuster circuit setting to an intermediate circuit setting in the duty cycle monitor offset.

|®U} in another aspect of the disclosure, a method includes issuing commands to a memory to perform a first doty cycle monitor sequence to determine a first duty cycle result and changing a duty cycle adjuster code of the memory by a first step size to change a duty cycle based on the first duty cycle result. The method further includes issuing commands to a memory to perform a second duty cycle monitor sequence to determine second duty cycle result and changing the duty cycle adjuster code of the memory’ by a second step size to change a duty cycle based on the second duty cycle result, wherein the second step size is less than the first step size.

j®14] In another aspect of the disclosure, a method includes performing a first duty cycle monitor sequence to determine a first duty cycle result with a first duty cycle adjuster code, performing a second duty cycle monitor sequence to determine a second duty cycle result with a second duty cycle adjuster code, and performing a third duty cycle monitor sequence to determine a third duty cycle result with a third: duty cycle adjuster code. The second duty cycle adjuster code is a first number of steps from the first duty cycle adjuster code and the third duty cycle adjuster code is a second number of steps from the second duty cycle adjuster code, the second number of steps less than the first number of steps.

jfiSf In another aspect of foe disclosure, a method includes issuing a plurality of commands to a memory to perform a plurality of duty cycle monitor sequences, changing the duty cycle code for a duly cycle adjuster of the memory following each of ie plurality of duly cycle monitor sequences, and evaluating duty cycle results from each of the plurality -of duly cycle monitor sequences. The duty cycle code is changed using at least two ifferent amounts of adjustment for the plurality of duty cycle monitor sequences.

fei.6| In another aspect of the disclosure, a method includes controlling a duty cycle adjuster of a memory·' to adjust a duty cycle of an internal dock according to a first speed adjustment after evaluating respective duty cycle results tor a plurality of duly cycle monitor sequences. The metho further includes controlling the duty cycle adjuster of the memory to adjust the duty cycle of the internal clock according to a slow speed adjustment after evaluating duty cycle results for a previous duty cycle monitor sequence of the plurality of duty cycle monitor sequences.

In another aspect of the disclosure, an apparatus includes a memory, a command/address bus, a data bus, a clock bus, and a memory controller coupled to the memory through the command/address bus, the data bus, and the clock bus. The memory controller is configured to issue commands to a memory to perform a first duty cycle monitor sequence to determine a first duty cycle result and change a duty cycle adjuster code of the memory by a first step size to change a duty cycle based on the first duty cycle result. The memory controller i further configured to issue commands to a memory to perform a second duty cycle monitor sequence to determine a second duty cycle result and change the duty cycle adjuster code of the memory by a second step size to change a duty cycle based on the second: duty cycle result, wherein the second step size is less than til first ste size.

j lftf In another aspect of the disclosure, an apparatus includes a memory', a command/address bus, a data bus, a clock bus, and a memory controller coupled to the memory through the command/address bus, the data bus, and the clock bus. The memory controller is configured to issue a plurality of commands to a memory to perform a plurality of daty cycle monitor sequences, change the duty cycle code for a duty cycle adjustor of the memory following each of the plurality of duty cycle monitor sequences, an evaluate duty cycle results from each of the plurality of duty cycle monitor sequences. The duty cycle code is changed using a least two different amounts of adj ustment for the plurality of duty cycle monitor sequences. {919) In another aspect of the disclosure, an apparatus includes a memory, a eommaud/address bus, a data bus, a Clock, bus, an a memory controller coupled to the memory through the command/address has, tire data bus, and the dock bus. The memory controller Is configured ro perform a first duty cycle monitor sequence to determine a first duty cycle result with a first duty cycle adjuster code, perforin a second duty cycle monitor sequence to determine a second duty cycle result with a second duty cycle adjuster code, and perform a third duty cycle monitor sequence to determine a third duty cycle result with a third duty cycle adjuster code. The second duty cycle adjuster code is a first numbe of steps if ora the first dut cycle adjuster code and the third duly cycle adjuster code is a second number of steps from the second duty cycle adjuster code. The second nu mber of steps less than the first number of steps,

[1 ⁾ 201 In another aspect of the disclosure, an apparatus include a memory, a command/address bus, a data bus, a clock bus, and a memory controller coupled t the memory through thecommand/address bus, the data bus, and the clock bus, The memory controller is configured to control a duty cycle adjuster of a memory to adjust a duty cycle of an internal clock according to a fast speed adjustment alter eval uating respective duty cycle results for a plurality of duty cycle monitor sequences. The memory controller is further configured to control the duty cycle adjuster of the memory ¹ to adjust the duty cycle of the internal clock according to a slow speed adjustment alter evaluating duty cycle results for a previous duty cycle monitor sequence of the plurality of duty cycle monitor sequences.

j 921 ) In another aspect of the disclosure, a method includes changing a dut cycle adjuster code by a first step size to set a duty cycle adjuster circuit to a first duty cycle adjuste code, issuing commands to perform a first duty cycle monitor sequence with a setting of the first dut cycle adjuster code, and evaluating first duty cycle results from the first dut cycle monitor sequence, The method further includes changing the duty cycle adjuster code by the first step size to set the duty cycle adjuster circuit to a second duty cycle adjuster code, issuing commands to perform a second duty cycle monitor sequence with a setting of the second duty cycle adjuster code, and evaluating second duly cycle results from the second duty cycle monitor sequence. The method further includes determining whether to change the duty cycle adjuster code by the first step size or by a second step size, wherein the second step size is less than the first step size and changing the duty -cycle adjuster code based at least in part car the determination.

j¾22j In another aspect of the disclosure, a method includes evaluating first duty cycle results for tt first duty cycle code fur a duty cycle adjuster of a memory and changing the first duty cycle code to a second duty cycle code based at least in part on the evaluation of the first duty cycle results. The method further includes evaluating second duty cycle

duty cycle code to a third duty cycle code based at least in part on the evaluation of the second duty cycle results. The first duty cycle results indicate a fust duty cycle condition and the secon duty cycle results indicate a second duty cycle condition that is different than the first du y cycle condition. An adjustment of the duty cycle adjuster than for the change from the second duty cycle code to the third duty cycle code is less than for the change from the firstduty cycle code to the second duty cycle code

| ©23} lo another aspect of the disclosure, a method includes adjusting a duty cycle adjuster of a memory and evaluating duty cycle results for each adjustment, wherein the duty cycle results indicate a duty cycle condition for die respective adjustment, and switching to a smaller adjustment size when the duty cycle results indicate a change in duty cycle condition for a current adjustment relative to a previous adjustment

|¾24| I another aspect of the disclosure, an apparatus include a memory, a command/address bus, a data bus, a clock bus, and a memory controller coupled to the memory through the eommand/address bus, the data bus, and the clock bus. The memory controller is configured to change a duty cycle adjuster code by a first step size to set a duty cycle adjuster circuit to a first duty cycle adj ster code, issue commands to perform a first dut\ cycle monitor sequence with a setting of the first duty cycle adjuster code, and evaluate first duty cycle results from the first duty cycle monitor sequence. The memory controller is further configured to change the duty cycle adjuster code by the first step size to set the duty cycle adjuster circuit to a second duty cycle adjuster code, issue commands to perform a second dut cycle -monitor sequence with a setting of the second duty cycle adjuster code, and evaluate second duty cycle results from the second duty cycle monitor sequence. The memor controller is further configured to determine whether to change the duty cycle adjuster code by the first step size or by a second step size, wherein the second step size is less than the first step size, and change the duty cycle adjuster code based at feast in part on the determination,

|¾25f In another aspect of the disclosure, an apparatus includes a memory, a command/address bus, a data bus. a clock bus, and a memory controller coupled to the memory through the command/address bus, the data bus, and the ock bus. The memory controller is configured to evaluate first duty cycle results for a first duty cycle code for a duty cycle adj uster of a memory and change the first duty cycle code to a second duty cycle code based at least in part on the evaluation of the first duty cycle results. The memor controller is further configured to evaluate second duty cycle results for the second duty cycle code for the duty cycle adjuster and change foe second duty cycle code to a third duty cycle code based at least in part on the evaluation of the second duty cycle results. The first duty cycle results indicate a first duty cycle condition and the second duty cycle results indicate a second duty cycle condition that is different than foe first duty cycle condition. An adjustment of the duty cycle adjuster than for the change from the second: dut cycle code to the third duty cycle code is less than for foe change from th first duty cycle code to the second duty cycle code.

Ii26| In another aspect of the disclosure, an apparatus includes a memory, a command/address bus, a data bus, a clock bus, and a memory ¹ controller coupled to the «ternary through foe command/address bus, foe data bus, and _. the clock bus. The memory controller is configured to adjust a dut cycle adjuster of a memory and evaluate duty cycle results for each adjustment, wherein the duty cycle results indicate a duty cycle condition tor the respective adjustment, and switch to a smaller adjustment size when the duty cycle results indicate a change in duty cycle condition for a current adjustment relative to a previous adjustment.

j# 7j Figure 1 is a block diagram of a system according to an embodiment of the disclosure.

jl28 j Figure 2 is a block diagram of an apparatus according to an embodiment of foe disclosure.

j029j Figure 3 is a block diagram of a data clock path according to a embodiment of foe disclosure. 1030) Figure 4 is a diagram of a mode register related to a duty cycle monitor (DCM) feature; according to an embodiment of fee disclosure.

10311 Figure 5 is diagram of opcode definitions for a mode register related to a DCM feature according to an embodiment of the disclosure,

|032j Figure 6 is a flow diagram of DCM sequence according to an embodiment of the disclosure.

|{*33) Figure 7 is a timing diagram for a DCM sequence according to an embodiment of the d isclosure.

[034j Figure S is an example timing diagram of a duty cycle adjuster (DCA) circuit for an adjuster rang according to an embodiment of the disclosure.

[ ^§ 3Sf Figure 9 is an example timing diagram of data clock signals that are adjusted using a DCA feature according to an embodiment of foe disclosure .

(0361 Figure 10 is a diagram of an operation for setting a DCA circuit according to an emtxxli merit of the disclosure.

[037) Figure 1 1 is a diagram of an operation for setting a DCA circuit according to an embodiment of the disclosure.

[03§| Figure 12 is a diagram of an operation for setting a DCA circuit according to an embodiment of the disclosure.

[039j Figure 13 is a diagram of an operation for setting a DCA Circuit according to an embodiment of the disclosure.

[040) Figure 14 is a diagram of an operation for setting a DCA circuit accordin to an embodiment of the disclosure.

[0411 Figure 15 is a diagram of an operation for setting a DCA circuit according to an embodiment of the disclosure.

[042) Certain details are set forth below to provide a sufficient understanding of examples of the disclosure. However, it will be dear to one havin skill in the art that examples of the disclosure may be practiced without these particular details. Moreover, the part icular examples o f the present disclosure described herein should not be construed to limit the scope of the disclosure to these particular examples. In other Instances, well- known circuits, control signals, timing protocols and software operations have not been shown in detail in order to avoid unnecessarily obscuring the disclosure. Additionally, teens such as“couples” and“coupled” mean that two components may he directly or indirectly electrically coupled. Indirectly coupled may imply feat two components are coupled through one or more intermediate components.

[043} Figure I is a block diagram of a system 100 according to an embodiment of fee disclosure. The system 100 includes a controller 10 and a memory system 105. The me ory' system 105 Includes memories P0(0)-ί10(r) (e,g,, “Device-O” through “Devieep j, where p is a non-zero whole slumber. The memories 110 may be dynamic random access memory (DRAM), such as low power double data rate (LPDQRfDRAM in some embodiments of the disclosure. The memories 110(0)- 1 10(p) are each coupled to the command-address, data, and clock busses. The controller 10 and the memory system 105 are in communication over several busses. For example, commands and addresses are received by the memory·· system 1,05 on a commaftd/address bu 1 15, and data is provided between the controller 10 and the memory system 05 over a data bus 125, Various clock signals ma be provided between the controller and memory system 105 over a clock bus 130. The clock bu 130 may include signal lines for providing system clocks CKJ and CK c recei ved by the memory' system 105, data clock WCK t and WCK. c received by the memory' system 1-05, and access data clocks RjDQSj and KpQS _jC provided by the memory' system 105 to the controller 10. Each of the busses may include one or more signal lines on which signals are provided.

{044} The CKJ and CK c clocks provided by the controller 10 to the memory system 105 are used for timing the provision and receipt Of the commands and addresses. The WCK land WCK c clocks and the RDQS t an RDQS c clocks are used for timing the provision of data. The CKJ and CK c clocks are complementary, the WCK t and WCK c clocks are complementary, and the RDQS t and RDQS c clocks are complementary. Clock signals are complementary ^· when a rising edge of a first clock signal occurs at the same time as a falling edge of a second clock signal, and when a rising edge of the second clock signal occurs at the same time as a falling edge of the first clock signal. The WCK j and WCK c clocks provided by the controller 10 to the memory ¹ system 105 may be synchronized to the CK J and CK _j c clocks also provided by the controller 10 to the memory system 105, Additionally, fee WCK t and WCK_ c clocks may have a higher clock frequency than the CKJ and CK_c clocks. For example, in some embodiments of the disclosure, the WCKjt and WCK, c clocks have a clock frequency that is four times the clock frequenc of the CK t and QC e docks,

|¾45f The controller 10 provides commands to the emory system 105 to perform memory operations. Nonriiroifmg examples of memory commands include timing commands for controlling the timing of various operations, access commands for accessing foe memory; such as read commands for performing read operations and write commands for performing write operations, mode register write and read commands for performing mode register write and mad operations, as well as other commands and operations. The command signals provided by the controller 10 to tire memory system 105 further include select signals (e.g;, chip select CS signals CS0, CS1 , CSp). While all of the memories 110 are provided the commands, addresses, data, and clock signals, the select signals provided on respective select signal lines are used to select which of the memories 110 will respond to the command and perform foe corresponding operation. In some embodiments of the disci osure, a respective select signal is provided to each memory 1 10 of the memory system 105. The controller 10 provides an active select signal to select the corresponding memory 1 10. While the respective select signal k active, the corresponding memory 100 is selected to receive the co mands and addresses provided on the command/address bus 115.

|04d| In operation, when a read command and associated address are provided by the controller 10 to foe memory system I OS, the memory 1 10 selected by foe select signals receives the read command and associated address, and performs a read operation to provide foe controller 10 with read data from a memory location corresponding to foe associated address. The read data is provided by foe selected memory 110 to the controller 10 according to a timing relative· to receipt of the read command. For example, the timing may be based on a read latenc y <R ) value that indicates the number of clock; cycles of foe QC and GKLj? clocks (a clock cycle of the CK_t and C c clocks is referenced as tCK) after the read command when the read data is provkied by the selected memory 1 !ø to the controller K). The RL value is programmed by the controller 10 in the memories 1 10. For example, foe RL value may be programmed in respecti ve mode registers of the memories l it) A known, mode registers included in each of the memories .110 may be programmed with information lor setting various operating modes and/or to select features for operation of the memories. One of the settings may be for the RL value.

| 7f In preparation of the selected memory I Hi providing the read data to the controller 10, the controller provides active WCK t and WCK c ocks to the memory system .105. The WCK ; and WCK c clocks may be used by the selected memory 1 10 to generate an access data clocks RDQS t an RDQS e. A clock signal is active when the clock signal transitions between low and high dock levels periodically. Conversely, a clock signal is inactive when the clock signal maintains a constant clock level and does not transition periodically:. The RDQS t and RDQS _„ c clocks' are provided by the memory 110 performing the read operation to the controller 10 for timing the provision of read data to the controller 10. The controller 10 may use the RDQS t and RDQS c clocks for recen mg the read data.

[048] I operation, when a write command and associated address are provided by the controller 10 to the memory system 105, the memory 1 10 selected b the select signals receives the write command and associated address, and performs a write operation to write data from the controller 10 to a memory location corresponding to the associated address. The write data is provided to the selected memory 1 10 by the controller 10 according to a timing relative to receipt of the write command. For example, the ti ing may he based on a write latency t WL) value that i ndicates the number of clock cycles of the Clj and CR c clocks after the write command when the write data is provided to the selected memory .1 10 by the controller 10. The WL value is programmed by the controller 10 in the memories 110 For example, the WL value may be programmed in respective mode registers of the memories i 10.

j¾49| In preparation of the selected memory 1 10 recess lug the write date from the controller 10, the controller provides active WCK t and WCK c clocks to the memory system 105, The WCK J and WCK y clocks may be used by the selected memory 110 to. generate internal clock signals for timing the operation of circuits to receive the write data. The data is provided by the controller 10 and the selected memory 1 10 receives the write data according to the WCK t and WCK c clocks, which is written to memory corresponding to the memory addresses.

|¾501 Figure 2 is a block diagram of an apparatus according to an embodiment of the disclosure. The apparatus may he a semiconductor device 200, and will be referred to as such. I» some embodiments, the semiconductor device 200 may include, without limitation, a DRAM device, such as low power DDR (LPDDR) memory integrated into a single semicon uctor chip, for example,

J8SJ j The semiconductor device 200 includes a memory array 250. The memory array 250 is shown? as including a plurality of memory hanks, in the embodiment of Figure 2, the memory array 250 is shown as including eight memory banks 8A K.0-BA K7. Each memory bank includes a plurality of word lines WL, a plurali ty of bit lines BL and /BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bi t lines BL and /BL The selection of the word line WL is performed by a row decoder 240 and the selection of the bit lines BL and /BL i performed by a column decoder 245. in the embodiment of Figure 2 _» the row decoder 240 includes a respective row decoder for each memory bank and the column decoder 245 includes & respective column decoder for each memory hank. The bit lines BL and /BL are coupled to a respective sense amplifier (SAMP), Read data .from foe bit line BL or /BL is amplified by the sense amplifier SAMP, and transferred to read/write amplifiers 255 over complementar local data lines (LIOT/B), transfer gate (TO), and complementary main data lines (MIOT/B). Conversely, write data outputted from the read/write amplifiers 255 is transferred to the sense amplifier SAMP over the complementary main data lines MIO G B. the transfer gate TG, and the complementary local data lines LIOT/B. and written in the memory cell MC coupled to the bit line BL or /BL,

[M2 j The semiconductor device 200 may employ a plurality of external terminals that include command and address and chip select (CA/CS) terminals coupled to a command and address bus to receive commands and addresses, and a CS signal, clock terminals to receive clocks CK t an CK c, and data clocks WQ J and WCK c, and to provide access data clocks RDQSj and RDQS _„ c, data terminals DQ and DM, and power supply terminals io recei ve power supply poten tials VDD, YSS, VDDQ, and VSSQ,

|(JS3| The clock terminals are supplied with external clocks CK J and CK e that are provided to an input buffer 220. The external clocks may be complementary. The input buffer 220 generates an internal clock ICLK based on the CKj and CK_e clocks. The ICLK clock is provided to foe: command decoder 215 and to an interna! clock generator 222, The interna! clock generator 222 provides various internal clocks LCLK based on the ICXK clock. The LCLK clocks may he used. for timing operation of various internal circuits. Data clocks WCK, t and WCK c are also provided to the external clock terminals. The WCK! t and WCK e clocks are provided to a data clock circuit 275, which generates internal data clocks based on the WCK t a d WCK c docks. The Internal data clocks are provided to the inp /o put circuit 260 to time operation of circuits included in the inpufo iput circuit 260. for example, to data receivers to time the receipt of write data.

[854} The CA/CS terminals may be supplied with memory addresses. The memory addresses supplied to the CA/CS terminals are transferred, via a command/address Input circuit 205, to an address decoder 212. The address decoder 212 receives the address and supplies a decoded row address XA D to the row decoder 240 and supplies a decoded column address YADD to the column decoder 245. The CA/CS terminals may he supplied with commands. Examples, of commands include timing command for controlling the timing of various operations, access commands for accessing the memory, such as read commands for performing read operations an write commands for performing write operations, mode register write and read commands for performing mode register write and read operations, as well as other commands and operations.

[#55} The commands may be provide as Internal command signals to a command decoder 215 via the command-address input circuit 205. The command decoder 215 includes circuits to decode the internal command signals to generate various internal signals and commands for performing operations. For example, the command decoder 21 ma provide a row command signal ACT to select a word line and a column command signal R/W to select a bi line.

[056] The command decoder 15 may access mode registers 230 that is programmed with information for setting various modes and features of operation for the semiconductor device 200. For example, the mode registers 230 may be programmed with information: related to data access latency, such ax read latency or write latency. As another example, the mode registers 225 may he programmed with information related to data burst length. The data burst length defines a number of data bits provided from or to each of the data terminals DQ per access operation (e.g., read or write operation). As another example, the mode registers 230 may he programmed with information for modes related to monitoring internal data clocks that are generated by the data clock circuit 275 based on the WCK t and WCK c clocks, as well as information for modes related to changing a timing of the interna! data clocks, such as the duty cycle of Che interna! data clocks. The interna! data clocks may be monitored, for example, for duty cycle distort ion caused by circuits of Che data clock circuit 275. n the timing of the data clocks may be adjusted to compensate for duty cycle error, for example, caused by the circuits of the data clock circuits 275.

1057} The information in the mode registers 230 may he programmed by providing the semiconductor device 200 a mode register write command* which causes the semiconductor device 200 to perform a mode register write operation. The command decoder 215 accesses the mode registers 230, and based da the programme information along with the internal command signals provides the internal signals to control the circuits of the semicon uctor device 200 accordingly. Information programmed in the mode registers 230 may he externally provided by the semiconductor device 200 using a mode register read command, which causes the semiconductor device 200 to access the mode registers 230 and provide the programmed information,

[658} When a read comman is received, and a row address an a column address are timely supplied with the read command, read data is read from memory cells in the memory array 250 corresponding to the row address and column address. The read comman is received by the command decoder 215, which provides interna! commands so that read data from the memory array 250 is provided to the read/write amplifiers 255 The read data is output to outside from the data terminals DQ via the mput/outpai circuit 260 The RDQSj: and RDQS e clocks are provided externally from clock terminals for timing provision of the read data by die input/output circuit 260. The external terminals DQ include Severn! separate terminals, each providing a hit of data synchronized with a clock edge of the RDQS t and RDQS c docks. The number of external terminals DQ corresponds a data width, that is, a number of bits of data concurrently provided with a clock edge of the RDQS and RDQS e clocks , in some embodiment of the disclosure, the data width of the semiconductor device 200 is 8 bits in other embodiments of the disclosure, the data width of the semiconductor device 200 is 16 hits, with the 16 hits separated into a lower byte of data (including 8 bits) and a upper b te of data (including 8 bits). j ^§ 59) When the write command is received, and a row address and a colum address are timely supplied with the write command, write data supplied to the data terminals DQ is written to a memory cells in the memory array 250 corresponding to the row address and column address A data mask may be provided to the data terminals DM to mask portions of the data when written to memory. The write command is received by the command decoder 215. which provides internal commands so that the write data is receive by data receivers in the input/output circuit 260. WCK t and WCKjt clocks are also provided to the external clock terminals for timing the receipt of the write data by the data receivers of the input/output circuit 260. The write data is supplied via the input/output circuit 260 to the read/write amplifiers 255, and by the read/write amplifiers 255 to the memory array 250 to he written Into the memory cell MC. As previously described, the external terminals DQ include several separate terminals. With reference to a write operation, each external terminal DQ receives a bit of data, and the number of external terminals DQ corresponds to a data width of bits of data that are -concurrently received synchronize with: a clock edge of the WCK J and WCK e clocks. As previously described, some embodiments of the disclosure include a data width of 8 hits, a oilier embodiments of the disclosure, the data width is 1 6 bits, with the 16 bits separated into a lower byte of S bits of data and a upper byte of 8 bits of data.

| 0f The power suppl terminal are supplied with power supply potentials V DD and

VSS. The power supply potentials VD!> and VSS are supplie to an internal voltage generator circuit 270. The internal voltage generator circuit 270 generates various internal potentials VPP, VOD, VAR Y, VTARGET, VPBRI, and the lik based on the power supply potentials VDD and VSS supplied to the power supply terminals. The internal potential VPP is mainly used in the row decoder 240, fee internal potentials VOD and VARY are umty used in the sense amplifiers SAMP included in the memory array 250, VTARGET may be a target Voltage for the internal potential VAR Y, and the: internal potential VPBRI is used in many peripheral circuit blocks,

{ il The power supply terminals are also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are supplied to the snput/outpnt circuit 260. The power supply potentials VDDQ and VSSQ supplied to the power suppl terminals may he the same potentials: as the power supply potentials VDD and VSS supplied to the power supply terminals in an embodiment of the disclosure. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be ^· dif erent potentials from the power supply potentials VDD and VSS supplied to the power supply terminals in another embodiment of the disclosure. The power supply potentials VDDQ and VSSQ supplied to tire power supply terminals are used for the input/output circuit 260 so that power supply noise generated by the input/output circuit 260 does not propagate to the other circuit blocks.

|862} Figure 3 is a block diagram of a data clock path 300 according to an embodiment of the disclosure. The data clock path 300 may be included in a data clock circuit. In some embodiments of the disclosure, the data clock path 300 may be included in the data clock circuit 275 of Figure 2,

|163| The data clock path 300 includes an input clock buffer 310 that is provided external data clocks WCKJ and WCK c. As previously described, the WCK t and WCK _C docks may be complementary. The input clock buffer 310 buffers the WCK 1 and WCK c elocks aod provides complementary buffered clocks to a duty cycle adjuster (DC A) circuit 320. The DCA circuit adjusts a timing of the buffered WCK t and WCK _j r clocks to provide timing adjusted WCK t and WCK c clocks. The buffered WCK t and WCK c clocks are adjusted based on information programmed in a mode register 325. For example, the information programme in the mode register 323 may ^¬ be a . DCA code that corresponds to variou steps of a DCA adjuster range. The timing of the buffered WCK f and WCK c clocks are adjusted by programming the DCA code in the mode register 325 (e.g., programmed by a memory controller) corresponding to a desired: timing. The timing of the buffered WCK J and WCK ; clocks may foe changed by changing the DCA code programmed in the mode register 325. In embodiments of the disclosure, where the data clock path 300 is included in the data clock circuit of Figure 2, the mode register 325 may be included in the mode registers 230.

1664} The DC adjuster circuit provides the timing adjusted: WCK j and WCK e clocks are provided to a divider circuit 330. The divider circuit: 330 provide multiple internal data clock signals that have a clock frequency that is less than a clock frequency of the WCK t and WCK_c clocks. The multiple internal data clocks may have. a phase relationship relative to one another in some embodiments of the disclosure, the divider circuit 330 provides four internal data clocks have a phase relationship of 90 degrees relative to one another (0 degrees, 90 degrees, 180 degrees, 270 degrees), and have a clock frequency that is one-half of the frequency of the WCK t and WCK c clocks. However embodiments of the disclosure ate not intended: to be limited to this particular number of internal data clocks, phase relationship, and/or clock frequency. The multiple internal data clocks arc provided from the divider circuit 330 over a clock tree: and driver circuits 340 to circuitry that may he operated according to the internal data clocks For example, the internal data clocks are provided by the clock tree and driver circuits 340 to inpui/oiuput circuits: fe.g,, _: input/output circuits 260 of Figure 2) for timing the operation of data receivers to receive write data.

jfr&SJ The dock input buffer 310 and the cloc tree and drivers 340 may have inherent circuit characteristics that cause undesirable timing changes relative to the WCK t aiid WCK c clocks in providing the i n!e ai data clocks. The inherent circuit characteristics may deviate from ideal circuit characteristics due to variations in fabrication processes, as well as variations in operation due to changing temperature and vol tage. For example, the clock input buffer 310 and the clock tree and drivers 340 may cause duty cycle to change when providing the internal data clocks, resulting in the interna! data docks having dut cycles that arc distorted relative to the external WCK i and WCKm clocks. As a result, the timing of the resulting internal data clocks may cause undesirable performance of eircui that are operated according to the internal data clocks,

A duty cycle monitor (DCM) 350 monitors a timing of the internal data Clocks provided by the clock tree and driver circuits 340 For example, the DCM 350 may monitor a duty cycle of one or more of the interna! data clocks. The DCM 350 includes a DCM circuit 355 and a mode register 353. The DCM circuit 355 monitors one or more of the internal data clocks provide by the clock tree and drivers 340 an provides information indicative of timing of the internal data clocks. The information may include, for example, duty cycle {DC ) results from the monitoring by the DGM circuit 355. Where circuits of the data clock path cause undesirable timing changes in providing the internal data clocks, the DCM 350 may he used to determine the degree of undesirable change. The DC results may be provided to the mode register 353, where the DCM results may be accessed and provided externally, for example, in response to a mode register read command. The DC circuit 3.55 may include circuits for monitoring internal data clocks for upper and lower bytes where a data width includes /both upper and lower bytes of data. [967) The mode register 353 may also be programmed with information that controls operation of the DCM circuit 355. For example, the information may control when monitoring fey the DCM circuit 355 is started and when monitoring hy the DCM circuit 355 is stopped. As a farther example, the information may control the DCM circuit 355 to change (or“flip”) inputs when monitoring the mtema! data clocks to increase accuracy by monitoring the internal data clocks with a first input condition and then flipping to a second input condition to further monitor the internal data clocks. Accuracy may be increased because in some embodiments of the disclosure, the DCM circuit 355 may have hysteresis in testing the internal data clocks, and as a result , the DCM results may be less accurate if tested without flipping of foe inputs. The DCM circuit 355 may also have art inherent DCM offset due to process variations and mismatches in the circuits of the DCM circuit 355 that cause inaccurate measurement of the timing of the internal data clocks. The DCM offset may result in a range of indeterminate DCM results when monitoring the internal data clocks,

[968) Separate DCM results may be provided by the DCM circuit 355 for each input condition and provided to foe mode register 353. Moreover, wherein internal data clocks for np er and lower bytes of data are provided, separate DCM results may also be provided for each byte of data,

ft ⁾ 69| The information may be programme in foe mode register 353 as opcodes, with the opcodes corresponding to particular hits of the mode register 353. In Figure 3, foe information for controlling foe starting and stopping of the DCM circuit 355 and for controlling the flipping of the input condition for monitoring _: is shown as being programmed as two bits in opcodes OP(1:0] of the mode register 353, and the DCM results provided by the DCM circuit 355 are programmed as four bits in opcodes OFf 5:2]. However, the number of bits for the information and the opcodes programmed as previously described may be different for different embodiments of the disclosure, and consequently, the scope of the disclosure is not limited to the particular example shown in Figure 3,

1970) in some embodiments of the disclosure having a data width including lower and upper bytes of data, a separate clock path is provided for internal clock signals for each byte: of data. Each clock path includes circuits lor separately monitoring foe internal clock signals for each byte of data. For example, in some embodiments of the disclosure, the data path 300 is included for providing, adjusting a timing, and monitoring internal clods: signals for a first byte of data, and at least a portion of the data path 300 is duplicated for providing, adjusting a timing, and monitoring internal clock signals for a second byte of data.

[071 j A duty cycle monitor (DCMI feature according t an embodiment of the disclosure will be described with reference to Figures 4 and 5, Figure 4 i a diagram of a mode register related to a DCM feature according to an embodiment of the disclosure. Figure 5 is diagram of opcode definitions for a mode register related to a DCM feature according to an embodiment of the disclosure. The DCM feature described with reference to Figures 4 and 5 may he used with a DCM according to ail embodiment of the disclosure. For example, in some embodiments of the disclosure, the DCM feature may be used with the DCM 350 of Figure 3.

[072} The DCM feature allows die memory controller to monitor WCK, duty cycle distortion in an internal WCK clock tree. Both lower and upper bytes perfor the DCM function simultaneously when DCM is enabled. Two separate duty cycle results are provided for each byte; DCMI. O and DCMI.,1 for the lower byte and DCMUC) and DCMU1 for the upper byte.

[®73J Figure 4 is a diagram of a mode register Mils that may be used to program information, (e.g., by a memory controller) to control a DCM operation as well as for DCM results to be provided. The mode register MRx is shown as included 8 bits, which represent various opcodes of the mode register MRx. Opcode definitions show n m Figure 5 may be used: with the mode register MRx of Figure 4 In some embodiments of foe disclosure.

107 } DCM operation may he initiated by writing MRx OPjQ] ~ I . Setting MRx OPjOj 0 terminates DCM operation. Prior to In mating DCM operation, WCK clock to CK. clock synchronization should be performed. Continuous toggling WCK input is required while DCM operation is enabled until after DCM operation is halted by writing MRx OPpjj -- 0b.

ji75j DCM results may be inaccurate if DCM circuit hysteresis is present. To increase foe accuracy of this function, the DCM feature supports flipping the input by setting MRx OP[l ] to the opposite state and then repeating foe measurement. 1876) Mode regi star write operations MR WfDCM Flip] an MR.W [DCM Stop] may be osed by a memory controller to capture the DCM results. The DCM result is determined: by the state of DCM Flip bit (MR OPf 11). Bor example:

|877| DCM Flip ^» 0: DCMI..0 and DCMUO w P i be us d; and

1878} DC Flip - 1 : DCML 1 and DCMU i will be used.

f8?9| L duty cycle monitor (DCM) sequence according to an embodiment of the disclosure will be described with reference id Figures 6 and 7. Figure 6 is a flow diagram of DCM sequence 600 according to an embodiment of the disclosure. Figure 7 is a timing diagram for a DCM sequence according to an embodiment of the disclosure. The DCM sequence described with reference to Figures 6 and 7 may be used with a DCM according to an embodiment of the disclosure. For example, in some embodiments of the disclosure, the DCM. feature may e used with the DCM 350 of Figure 3.

1080} In some embodiments of the disclosure, prior to performing the DC sequence of Figure 6, DCM training is completed afte r CBT and WCK2CK levelin so that mode register write (M.RW) and mode register read (MRR) operations may he performed. Additionally, frequency set points are updated and the WCK. is active at a lull-rate before the DCM begins in such embodiments of the disclosure.

{881 } The DCM sequence of Figure 6 will be described with reference to the timing diagram of Figure 7, and with reference to the mode register M¾ of Figure 4.

{882} At step 610, a mode register write command (including commands MRW-J and MRW-2) is issued, for example, by a memory controller to a semiconductor device, to start DCM. The mode register write command is received at times TcO and Tel of Figure 7. At step 620. wait time tDCMM for the DCM to complete duty cycle measurement. At step 630 a mode register write command is issued to switch MRx OF[l j to flip the inputs of DCM. The mode register write command is recei ved at times TdO and Tdl of Figure 7. with tDC M between times Te l and Tdl .

{883} Transitioning the flip hit from a logic lo to a logic high will automatically: (3 } capture the current DCM results; (2) store the DCM results in MRx OP{2]/MRx OP{4J; and (3) reset and restart (he DCM. Transitioning the flip bit from a logic high to a logic low will automatically: ( ! ) capture the current DCM results; Store the DCM results in MRx OP[3]/MRx OP[S]; an (3) reset and restart tha DCM. 77

1084 ) At step 640, wait time iDCMM for the DCM to complete dirty cycle measurement with the Hipped inputs. At step 650 a mode register write command is issued to exit DCM, The mode register command is received at times TeO and Tel , with tDCMM between times Tell and Tel , Exiting DCM automatically captures am! stores the current DCM results in MRx OP 2]/MRx 0P[4] when MRx OR[ G| is a logic low, and automatically captures atid stores the current DCM results in MRx OP{3j/MRx OP[Sj when MRx OPjl ] is a logic high.

|U85j At step 660, MRx OP[5 2j is read out by issuing, an mode register mad command MRR after a minimum time from exiting DCM f e.g , at time TIB) using normal MRR timing to read the DCM results,

Ϊb86| The steps described with reference to Figures 6 and 7 may be combined in various manners, including adding steps and ignoring steps, wi thout departing from the scope of the disclosure.

jf>87| A duty cycle adjuster (DCA) feature according to an embodiment of the disclosure will be described with reference to Figures 8 and 9, Figure 8 is an example timing diagram of a DCA adjuster circuit for an. adjuster range according to an embodiment of the disclosure. Figure 9 is an example timing diagram of data clock signals that are adjusted using a DCA feature according to an embodiment of the disclosure. The DCA feature described with reference to Figures 8 and 9 may he used with a DCA circuit according to an embodiment of the disclosure. For example, in some embodiments of the disclosure.; the DCA feature may be used with DCA circuit 320 of Figure 3.

[688} The DCA feature is a mode-register-adjustabie WC DCA to allow a memory controller to adjust internal WCK clock tree duty cycle to compensate for systemic duty cycle error. The DCA feature adjusts the static internal WCK (e,g„ internal WCK 1 and WCK c) duty cycle _·; The Internal WCK may be included in the internal data signals provided by a clock path th at receives external WCK 1 and WCK e clocks. A separate DCA may be pro vided for each byte of data (e.g„ D AL for the Lower Byte adjustment and DC All for the Upper Byte adjustment).

f 689 j The WCK DCA may be located before the WCK divider or may equivalent place.

The WCK DCA may affect WCK duty cycle during memory operations. For example, the WCK duty cycle may be affected ibr some of all of the following operations in some embodiments of the disclosure: Read, Read32 Write, Write32, Masked Write, Mode Register Read, Read FIFO, Write FIR), Read DQ Calibration, and/or Duty Cycle Monitor. A memor controller can adjust the duty cycle of internal docks fey programming information in a mode register, for example, programming information as opcodes of a mode register. For example, in an embodiment of the disclosure including the data path 300 of Figure 3, the duty cycle may he adjusted b programming information as opcodes of the mode register (M R) 325, Assumi ng for an embodiment of the disclosure the MR 325 includes opcodes for eight bits, & controller may adjust the duty cycle through the opcode MR OP[3;fi] for DC L and MR OP[7 4] for DC AD settings. Desirable mode register seting for DC A may be determined by the controller in different ways,

[(>‘>01 Figure 8 illustrates an example adjustment of interna! WCK over a DCA range.

In the example of Figure 8, the DCA includes a range of adjustment of 4-7 to -7 steps. In this manner, the DCA may be set to one of fifteen different steps of a DCA range to a.d;s«st a duty cycle of internal W K The difference of actual value between step N and step NΉ (or N-i ) may vary because variation of duty cycle by changing DCA may not be linear. Adjusting the DCA by increasing (>·) steps increases high duty cycle of WCK, whereas adjusting the DCA by decreasing (-} steps decreases high duty cycle of WCK. Figure 9 illustrates the inerease of the high duty cycle of WCK; for DCA code increase and the decrease of the high dut cycle of WCK tor DCA code decrease.

[0911 Embodiments of the disclosure include changing the DCA code by multiple step sizes (e.g.. more than One step size) and/or identifying a DGM offset in terms of a range of DCA codes to identify a DCA code setting for a DCA circuit. Example embodiments of the disclosure will be described in more detail below. Using multiple step sizes may facilitate efficient identification of a DCA code setting for a DCA circuit. The multiple st ep sizes may be used with a linear search for the range of DC A codes, it h a larger step size considered to be a fast speed and a smaller step size considered to be a: slow speed, identifying a DCM offset in terms of a range of DCA codes may improve accuracy in setting a DCA code for a DCA circuit. Intermediate DCA codes in the range of DCA codes for the DCM offset, for example, DCA codes midway (or close to midway } the range of DCA codes, may he used as an acceptable DCA code setting. for a DCA circuit. [092] Figures 10- 15 are diagrams of operations for setting a duly cycle adjuster (DCA) circuit according to some embodiments of the disclosure. The operation may be used bv a memory controller to set the DC A circuit to adjust timing of internal clock signals, for example, to adjust m internal clock tree duty cycle, to compensate for systemic duty cycle error ot a semiconductor device. The operations of Figures 10-15 may be used with any combination of embodiments of the disclosure previously described with reference to Figures 1 -9, Commands may be issued, for example, by a memory controller to a: semiconductor device, to perform the operations as described below for Figures 10- 15. Specific reference to the particular commands issued and to the issuance of the particular commands has been omitted in the description below in the interests of brevity. However, the issuance of the commands and when the commands are Issued to perform the operations are intended to be within the scope of the disclosure,

J¾>3} Figures 10- 15 each shows an operation that includes performing duty cycle monitor (DCM) sequences to determine duty cycle results (DCM results], and adjusting a DCA circuit based on the DCM results to reach an optimal setting for a DCA circuit. In some embodiments of the disclosure, the DCM sequences may include the DC sequence of Figure 6 A DCM sequence having a timing as shown in Figure 7 may be included in the DCM sequences in some embodiments of the disclosure. The DCA results determined by the operation of Figure i f) , may defined as shown in Figure 5 hi some embodiments of the disclosure. The DCM results may be provided in a mode register as shown in Figure 4 in some embodiments of the disclosu re.

[094] lit the example operations of Figure 10- 15, the DCA circuit that is adjusted based on the DCM results includes a range of adjustment of 47 to -7 steps, In this manner, the DCA circuit may be set to one of fifteen different steps to adjust a duty cycle of an internal data clock, for example, an internal WC1C (e.g,, including internal WCK t and/or WCK_ c). The example operations of Figures 10- 1 Swill also he described with reference to the DCA circuit 320 and the DCM 350 of the clock path 300 of Figure 3. Additionally, each DCM sequence may provide two DCM results. For example, one DCM result is provided for a first input condition .for the DCM (e.g., a first DC flip setting] and a second DCM result is provided for a second input conditio for the DCM (e.g„ a second DCM flip setting). The DCM results may be provide in a mode register i some embodiments of the disclosure. For example, each of the DCM results may be provided as a respective opcode of the mode register in embodiments of the disclosure where the DCM results are provided in the mode register as shown in Figure 4, the two opcodes determined daring a DCM sequence of the: example operation of Figure Hi may correspond n> opcodes OPf2] and 0P[3], with OP 2j roviding the DCM results for a first DCM flip setting ie.g , with no flip) and with QP[3 j prov iding the DCM results for a second DCM flip setting (e.g., with flip). In embodiments of the disclosure that include upper an lower bytes of data, additional DCM results may be provided from the DCM sequence for the other byte of data.

jh95| Figur JO is a d iagra of an operation for setting a DC A circuit accord fog to an embodiment of the disclosure. The DCA circuit of the example operation of Figure 10 is considered to not have any DCM offset. That is, the DCA eiieuit does not include a range of measurement error resulting from circuit variation and mismatch.

Prior to time TO, the DCA circuit is set to an adjustment of 0, for example, following an initialization of the DCA circuit. At time TO a first DCM sequence is started and at time T1 the first DCM sequence is stopped, for example by a memory controller issuing appropriate commands to a memory. During the first DCM sequence between times TO and T! , first DCM results are determined. As previously described, a DCM sequence of the example operation of Figure 10 provides two DCM results, each corresponding to a different condition tor the DCM, for example, with no DCM flip and with DCM flip. The two DCM results will be described as corresponding to opcodes QP[3:2) of a mode register. In the example operation of Figure 10, the DCM results from the first DCM sequence are OPj 3:2] 00. The 00 results indicate that the high duty cycle for both conditions is less than 50%. The first DCM results are evaluated by a memory controller, for example, and commands are issued so that opcodes for setting the DCA circuit are changed by the memory controller to cause an increase in the high duty cycle of internal clocks. A s shown in Figure 10, the DCA circuit is adj nstcd by a first step size, for example, 2 steps, following time T.I to increase the setting of the DCA circuit to +2 and increase the high duty cycle.

[897) Following the 2 step increase Mowing time Tl, a second DCM sequence is started at time Ϊ2 and stopped at time T3. During the secon DCM sequence between times T2 and T3, second DCM results are determined. The DCM results from the second DCM sequence are OP[3:2] 00. As previously described, the 00 results indicate that the high duly cycle for both conditions for the DCM is less than 50%. The second DCM results a¾e evaluated and opcodes for seting the DCA circuit are changed to cause an increase in the high duly cycle of internal clocks. As shown in Figure 10, the DC A circuit is adjusted by She first s-tep size of 2 slops following time T3 to increase the seting of the DCA circuit to 4 and increase the high duty cycle.

[898 j A third DCM sequence is performed between times T4 and TS, which results in third DCM results 0fOP[3:2] ~ 00, , indicating that the hi gh duty cyc le for both conditions for the DCM is less than 50%. Opcodes for setting the DCA circuit are again changed to cause an increase in the high duty cycle of internal clocks. As shown in Figure 10 _t die DCA circuit is adjusted by the first step size of 2 steps following time TS to increase the seting of the DCA c ircuit to 4-6 and further increase the high duty cycle,

[899] A fourth DCM sequence is performed between times T6 and T7 , which results in fourth DCM results of OP[3:2j 1 1. The 11 results indicate that the high duty cycle for both conditions for the DCM is greater than 50%. The charge in OP[3::2] ^« 08 at time TS to an OP|3:23 11 at time T7 indicates that the adjustment of the DCA circuit to a setting of 46 following time Ϊ5 caused the high duty cycle of the internal clocks to increase more than needed Consequently, the DCA should be adjusted to decrease the setting from *6 to reduce t e high duty cycle of the internal clocks. As shown in Figure 10, the DCA circuit is adjusted by a second step size that is less than the first step size for example, 1 step, following time T7 to reduce foe seting of the DCA circuit to +5 and decrease the high duty cycle,

j 8100 j The second step size may be used to adjust the setting of foe DCA circuit more finely than adjusting the setting by the first step size. The second step size may be used, for example, folio win a change in the DCM results from indicating that the high duty cycle is less than 50% to indicating that the high duty cycle is greater than 50%. The second step size may alternatively or additionally be used based On the history Of DCM results. For example, decreasing the settings for the DCA circuit following time T? by the first step, that is, 2 steps, would result in a DCA circuit seting of +4, which based on the DCM results from the DCM sequence between times T4 and TS, is known to be C)Pp; _r 2] ^:::: 00. The DCM results of OF[3;2] ^:::: 00 indicate that fo high duty cycle for both condition for the DCM is less than 50%, Thus, adjusting the setting for foe DCA circuit by the second step following time T7 results in a DCA circuit setting of +5 that has not yet been evaluated (as DCA circuit settings of i-4 and +6 already have).

$1013 Following the adjustment of the DCA circuit to a setting of ÷S ₅ a fifth DCM sequence may be performed between times T8 and T9, which results in fifth DCM results that are indeterminate, that is, of OR|3:2] 10 or OP[3:2] ~ 01. Indeterminate DCM results indicate that the DCM results for each of the two conditions tested during the DCM sequence _: are different, one DCM result indicating a high duty cycle of greater than 50% and the other DCM result indicating a high duty cycle of less than 50%. Based on the history of DCM results, further adjustments to the DCA circuit; settings from +5 would result in conditions that have already been evaluated as needing DCA circuit adjustment (e.g„ OP|3:2] ^» 00 for a +4 setting and OP(3:2j™ 11 for a +6 seting). Consequently, the current +5 DCA setting results in an acceptable (e g., a least unsatisfactory) setting for the DCA circuit.

! 01021 To some embodiments of the disclosure, the fifth DCM sequence is not perfor med.

The fifth DCM Sequence may be deemed, for example, by a memory controller, unnecessary based on a history of the DCM results. In particular, DCA circuit settings of -i-4 and ·ί·6 were unsatisfactory and resulted in adjustments of the DCA circuit settings. Thus, by deduction, a DCA salting of +5 results in a least unsatisfactory setting for the DCA, circuit.

$I03| Figure 11 is a diagram of an operation for setting a duty cycle adjuster (DCA) circuit accord ing to an embodiment of the disclosure. The DCA circuit of the example operation of Figure 1 1 is considered to not have any DCM offset. That is, the DCA circuit does not include a range of measuremen error resulting fro circuit variation and mismatch.

$1043 Prior to time TO, the DCA circuit is set to an adjustment of 0, for example, following an initialization of the DCA circuit. At time TO a first DCM sequence is started and at time Tl the first DCM sequence i stopped, tor example, by a memory controller issuing appropriate commands to a memory. During the first DCM sequence between times TO and Tl, first DCM results are determined. As previously described, a DCM sequence of the example operation of Figure 1 1 provides two DCM .results, each corresponding to a different condition for the DCM, .for example, with no DCM flip an with DCM flip. The two DCM results will be described as corresponding to opcodes OP[3 :2 j of a mode register. In the example operation of figure 1 1 , the DCM results from the first DCM sequence are OF[3;2] l i. The 11 results indicate in the example operation of Figure 11 that the high duty cycle for both conditions is greater than 50%. The first DCM results are evaluated by a memory controller, for example, and commands are issued so that opcodes for setting the DC A circuit are changed by the memory controller to cause a decrease in the high duly cycle of internal clocks. As shown in Figure 1 l , the DCA circuit is adjusted by a first step size, for example, 2 steps, following time T I to decrease the setting of the DCA circuit to -2 and decrease the high duty cycle. jMOSJ Following the 2 step decrease following time Tl , a second DCM sequence is started at time 12 and stopped at time T3. During the second DCM sequence between times T2 and T3, second DCM results are determined. The DCM results from the second DCM sequence are OF[3:2] -·-·-· 00. As previously described, the 00 results indicate that the high duty cycle for both conditions for foe DCM is less than 50%, The second DCM results are evaluated and opcodes for setting the DCA circuit are changed to cause art increase in the high duty cycle of internal clocks. As shown in Figure 1 1 , the DCA circuit is adjusted by a second step size that is less than the first step size, for example, 1 step, following time T3 to increase the seting of the DCA circuit from -2 to ~1 and increase the high duty cycle.

[8106] As previously described with reference to the example operation of Figure 10, the second step size may be used to adjust the setting of the DCA circuit more finely than adjusting the setting by the first step size. The second step size may he used, for example, following the change in the DCM results front Indicating that the high duty cycle is greater than 50% to indicating that the high duty cycle is less than 50%. The second step size may alternatively or additionally be used based on the hi story of DCM results. For example, increasing the settings for the DCA circuit following time T3 by the first step, that is, 2 steps, would result in a DCA circuit seting of 0, which based on the DCM results from the, DCM sequence between times TO and TL is known to be OP[3:2] ~ 1 L The DCM results of OP[3;2] - 11 indicate that the high duty cycle for both conditions for the DCM Is greater than 50%. Thus, adjusting he settings tor the DC A circuit by the second step following time 13 results in a DCA circuit setting of 4 that has not yet been evaluated (as DCA circuit settings of 0 and -2 already have). _\mm\ Following the adjustment of the DCA circuit to a setting of -1 , a third DCM sequence may be performed between times 14 and 15, which results in third DCM results that are indeterminate, that i&, of OP[3 ;2] ~ 10 or OF 3 : 2 j 01. As previously described, indeterminate DC results indicate that the DCM results for each of the two conditions tested during the DCM sequence are different one DCM resuit indicating a high duty cycle of greater than 50% and the other DCM result indicating a high duty cycle of less than 50%. Based on the history of DCM results, further adjustmen ts to the DCA Circuit settings from - 1 would result in conditions that have already been evaluated as needing DCA circuit adjustment (e.g , OP|3:2] ----- 1 1 tor a 0 setting and OPp;2j ------ 00 tor a -2 setring). Consequently, the current -1 DCA setting results in an acceptable setting for the DCA circuit.

[0108} In some embodiments of the disclosure, the third DCM sequence is not performed. The third DCM sequence may be deemed, for example, by a memory controller, unnecessary based on a history of the DCM results, in particular, DCA circuit settings of 0 and -2 were Unsatisfactory and resulted in adjustments of the DCA circuit settings. Thus, by deduction, a DCA setting of-1. results in a least unsatisfactory setting for tire DCA circuit.

[0109} Figure 12 is a diagram of an operation for setting a duty cycle adjuster (DCA) circuit; accord ing to an embodiment of the disclosure. The: DCA circuit of the example operation of Figure 12 is considered to have a DCM offset. That is, the DCA circuit includes a range of measurement error resulting from circuit variation and mismatch. In the example operation of Figure 12, the DCM o ffset is over a range of about 2-3 steps of DCA settings.

m Prior to time TO, the DCA circuit is set to an adjustment of 0, for example, following an initialization of the DCA circuit. At time Id a first DCM sequence is started and at time T l the first DCM sequence is stopped, for example, by a memory controller issuing appropriate commands to a memory. During the first DCM sequence between times TO and TL first DCM results are determined. The DCM results from the first DCM: sequence arc OPp:2j ~ 00, indicating that the high duty cycle for both conditions is less than 50%, The first DCM results are evaluated by a memory controller, fo example, and commands are issued so that opcodes for setting the DCA circuit are changed by the memory controller to cause an increase in the high duty cycle of internal clocks. As shown in Figure 12, the OCA circuit is adjusted by a first step size, for example, 2 steps, following time IT o increase the setting of the DCA circuit to 2 and increase the high duty cycle.

[till! Following the 2 step increase following time Ti , a second DCM sequence is started at time T2 and stopped at time T3. During the second DCM sequence between times T2 and T3, second DCM results are determined The DCM results from the second DCM sequence are GPf3:2] - 00 As previously described, the 00 results indicate that the high duty cycle for both conditions for the DCM is less than 50%. The second DCM results are evaluated and opcodes for setting the DCA circuit are changed to cause an increase in the h igh duty cycle of internal docks. As shown in Figure 12, the DCA circuit is adj usted by the first step s ize of 2 steps following time T3 to increase the setting of the DCA circuit to ^÷ 4 and increase the high duty cycle.

|M12j A third DCM sequence is performed between times T4 and T5, whicivresnlt in third DCM results that are indeterminate, that is, of QP[3:2] *= 10 or OP 3;2 | 01. As previously described, indeterminate DCM results indicate that the DCM -results for each of the two conditions tested during the DCM sequence are different, one DCM result indicating a high duty cycle of greater than 50% and the other DCM result indicating a hig duty cycle of i ess than 50%. Given that the DCM results are indeterminate, and an overshoot in the DCA settings has not resulted in a definite change from the previous DCM results OP[3:2 j ^:: 00 from the DCM sequence between times T2 and T3, the indeterminate DCM results from the DCM sequence between times T4 and T5 is considered to be a setting within a range Of error for the DCM, that is, within the DCM offset of the DCM.

[91131 Boundaries of the DCM offset range are determined by performing DCM sequences for different DCA circuit settings to identify the settings resulting in determinate DCM results that border DCA circuit setings that result in indeterminate DCM results. The boundaries of the DCM offset are represented by the maxi mum DCA circuit setting that results in DCM results that are indeterminate (e.g„ upper boundary ) ami the minimum DCA circuit setting that results in DCM results that are indeterminate (e, _: g , lowe boundary). The DCA code for the determinate DCM results that borders the upper boundary of the DCM offset is one step greater than the DC code for the indeterminate DCA results representing the upper boundary, and the DCA code for the determinate D CM results that borders the lower boundary of the DCM offset is one step less than the DCA code: for the indeterminate DCA results representing the lower boundary.

|M ] For example following She indeterminate DCM results following time T5 from the DCA circuit setting of - , the setting for the DCA circuit is adjusted by the first step size of 2 steps to continue increasing the DCA circuit setting. The resulting DCA circuit setting is +6. A fourth DCM sequence is performed between times T6 and 17, he resulting fourth DCM results are again indeterminate, which indicate that the DCA circuit setting of -HS is within the range of the DCM offset. The DCA circuit setting is further increased iol lowing time T7 to find a boundary of the DCM offset With the DCA circuit setting already at +6, and a maximum DCA circuit setting of f7, the DCA circuit setting is adjusted by 1 step to increase the DCA circuit setting to +7.

fMIS j A fifth DCM sequence is performed between times TS and T9, which results in fifth DCM results of OP[3 :2 11 , The fifth DCM results are determinate, and indicate that the high duty cycle for both conditions for the DCM is greater than 30%. With the DCA circuit settings of +7 resulting in determinate DCM results, and indicating that the high duty cycle is greater than 50% for both conditions, and further with the DCA circuit settings of 6 resulting in indeterminate DCM results, it can be concluded that the DCA circuit setting of +6 represents an upper boundary of the DCM offset. The lower boundary of the DCM offset remains to be determined.

ftIMJ To determine the lower boundary of the DCM offset, the DCA circuit setting is adjusted relative to the DCA setting of +4, which as previously described, resulted m indeterminate DCM results from the DCM sequence between times T4 to TS. With the DCA circuit setting of *4 resulting in indeterminate DCM results, and searching for a lower boundary of the DCM offset the DCA -circuit settings are adjusted to decrease a .high duty cycle. The DCA setings are adjusted by a second step size that is less than the first step size, for example, 1 step, to reduce the setting of the DCA circuit -from +4 to t-3.

19117 The second step size of 1 step may be used to adjust the DCA circuit settings because, for example, there is a change in direction of adjustment for foe DCA circuit setting relative to the direction of adjustment that resulted k the indeterminate _: DCM results. As previously described, the direction of adjustment that resulted in the indeterminate DCM results from the DCA circuit seting of ÷ was increasing the high duty cycle (i.e., an adjustment of a 2 step increase from a DCA circuit setting of to +4 follow ing time Ύ3). With now adjusting the DCA circuit settings to decrease the high duty cycle in order to find a lower boundary of the DCM offset, the direction of adjustment is changed to the minus direction. The second step size may alternatively or additionally he used based on the history of DCM results. For example, decreasing the settings for the DCA circuit following time T5 by the first step, that is, 2 steps, would result in DCA circuit setting of +2, which based on the DCM results from the DCM sequence between times T2 and T3, is known to be OP[3:2] 00; The DCM results of 0P[S;2j 00 indicate that the high duty cycle for both conditions for the DCM is less than 50% Thus, adjusting the settings for the DCA circuit by the second step following time T5 results in a DCA circuit setting of *3 that has not yet been evaluated (as DCA circuit settings of *2 already has). Consequently, the second step size is used to decrease the DCA circuit setting from 4 to ÷3

jffl 18] A sixth DCM sequence is performed between times Tl 0 and TΊ 1 following the adjustment of the DCA circuit setting to +3, which resu It in sixth DCM results ofOPj 3:2] ~ 00. The sixth DCM results are determinate, and indicate that the high duty cycle for both conditions for the DCM is less than 50%. With the DCA circuit settings of +3 resulting™ determinate DCM results, an indicating that foe high duty cycle is less ft an 50% for both conditions, and further with the DCA circuit settings of a-4 resulting in indeterminate DCM results, it can be concluded that foe DCA circuit setting of 4-4 represents a lower boundary of the DCM effect.

[0119] Thus, in the example operation of Figure 12, the boundaries for the DCM offset are determined to be the DCA circuit settings of +4 aad +6.

[8120] A DCA circuit setting that is within the boundaries of the DCM offset may result in an acceptable setting for foe DCA circuit. For example, _: an intermediate DC A circuit setting that is midway (or close to midway) between the b undaries of the DCM offset may result in a least unsatisfactory setting for the DCA circuit With reference to foe example operation of Figure 12, the DCA circuit setting of +5 is an intermediate DCA circuit seting that is idway between foe .DCM offset boundaries of ÷4 and +6 The DCA circuit setting of +5 may provide an acceptable setting for the DCA circuit. [8121] Figure 13 is a diagram of an operation for setting a duty cycle adjuster (DCA) circuit according to an embodiment of the disclosure. The DC A circuit of the example operation of Figure 13 is considered to have a DCM offset That is, the DCA circuit includes a range of measurement error resulting from circuit variation and mismatch. In the exampl e operation of Figure 1 . the DCM offset Is over a range of about 2-3 steps of DCA setings

{Q122| Prior to time TO, the DCA circuit is: set to an adjustment of 0, for example, following an initialization of the DCA circuit. At time TO a first DCM sequence is started and at time TΪ the first DCM sequence is stopped. During the first DCM sequence between times TO and T1 , first DCM results are determined. The DCM results from the first DCM sequence are indeterminate. Given that the DCM results are indeterminate, and there have not been any DCA circuit settings that have resulted in determinate DCM results, the DCA circuit setting that resulted in the indeterminate DCM results from the DCM sequence between times TO and Tt are considered within a range of error for the DCM, that is, within the DCM offset of foe DCM,

[8123] As previously described, boundaries of the DCM offset range are determined by performing DCM sequences for different DCA circuit settings to identify the settings resulting in determinate DCM results that borde DCA circuit settings that result in indeterminate DCM results. "Die boundaries of the DCM offset are represented by the maximum DCA circuit setting that results in DCM results foat are imfoteiminaie (e.g., upper boundary) and the minimum DCA circuit setting that results in DCM results that are indeterminate (e.g., lower boundary)

[0124] For example, followin the indeterminate DCM results following time T 1 from the DCA circuit setting of 0, the sating for the DCA circuit is adjusted by a first step sire of 2 steps. In the example operation of Figure i 3, ihe DCA eircmt setting is increased by the first step sire to %2, However, in other embodiments of the diseiosure, the DC A circuit setting may be decreased by the first ste size when an initial DCA circuit setting is within a DCM offset,

[1125] A second DC sequence is performed between times T2 and T3 for· the DCA circuit setting of +2 to determine second DCM results. The second DCM results are OP[3;2] =* 11, As previously described, the 1 1 DCM results indicate that foe high duty cycle for both conditions for the DCM is greater than 50%. The second DCM results are evaluated and opcodes for setting the DCA circuit are changed to cause a decrease the high duty cycle. As shown in Figure 13, the DCA circuit setting is adjusted by a second step ske that is less than the first step size, for example, 1 step, following time T3 to reduce the setting uf the DCA circuit from *2 to Ή and decrease the high duty cycle, |M26| The second step size of l step may be used to adjust the DCA circuit settings because, for example, there is a change in direction of adjustment for the DCA circuit setting relative to the previous direction of adjustment As previously described, the direction of adjustment that resulted in the DCM results OP[3:2j ~ 11 for the DCA circuit setting oi>2 was increasing the high duty cycle lie.., an adjustment of 2 step increase from a DCA circuit setting of 0 to *2 following time T1 ). With now adjusting the DCA circuit seti ngs to decrease the h igh duty cy cle, the direc tion of adjustment is changed to the minus direction. Consequently the secon -step ske is used to adjust t>CA circuit setting from +2 to +1. The second step size may alternatively or additionally be used based on the history of DCM results. For example, decreasing the settings for the DCA circuit following time Ϊ3 by the first step, that is, 2 steps, would result in a DCA circuit setting of ft, which based on the DCM results from the DCM sequence between times TO and T1 , is known to be indeterminate. Thus, adjusting the setings for the DCA circuit by the second step following time T3 results in a DCA circuit seting of 1 that has not yet been evaluated b a DCM Sequence (as DCA circuit settings of 0 already has). |M27j A third DCM sequence may be performed between times T4 and T5 for the DCA circuit setting of *1 , which res Its in third DCM results of OP :21 ~ 1 1. The third DCM results are determinate, and m ieate that the high duty cycle for both conditions for the DCM is -greater than 50%. With the DCA circuit settings of Ή resulting in determinate DCM results, and indicating that the high duty cycle is greater than 50% for both conditions, and further with the DCA eueat settings of 0 resulting in indeterminate DCM results, it can be concluded that the DC A circuit setting of 0 represents an upper boundary of the DCM offset. The lower boundary Of the DCM offset remains to be determined, |0l28j To determine foe lower boundary of the DCM offset, foe DCA circuit setting is adjusted relative to the DCA setting of 0, which as previously described, resulted in indeterminate DCM, results from he DCM sequence between times TO to Tl . With the DCA circuit setting of 0 resulting in indeterminate DCM results, and searching for a lower boundary of the DCM offset, the DCA circuit settings are adjusted to decrease high duty cycle. The DC A setings are adjusted by the first step size to reduce the setting of the DCA circuit from 0 to 2 The first step size of 2 steps may be used because there are no DCM results for decreasing adjustments: of the DCA circuit settings.

| 29j A fourth DCM sequence is performed between times T6 and T7 The resulting fourth DCM results are indeterminate, which indicate that the DCA circuit setting of is within the range of the DCM offset. The DCA circuit setting is decreased again following time T7 to find a lower boundary of the DCM offset. Following the indeterminate DCM results following time T7 from the DCA circuit setting of -2, the setting for the DCA circuit is adjusted by the first step size of 2 steps to continue decreasing the DCA circuit setting. The resulting DCA circuit setting is -4, A fifth DCM sequence is performed between times Ύ8 and T9. The resulting fifth DCM results are 0P[3:2j -·-· Oft, which indicate that the high duty cycle for both conditions for the DCM is les than 50%. 1 he fifth DCM results are evaluated and opcodes for the DCA circuit setting are changed io cause an increase in the high duty cycle. As shown in Figure 13, the DCA circuit is adjusted by the second step size of 1 step following time T9 to increase the setting of the DCA circuit fro -4 to -3 and increase the high dut cycle.

[9l30j The second step size may be used to adjust the DCA circuit setings to -3, for example, following the change in direction of adjustment for the DCA circuit setting relative to the direction of a justment that resulted in foe previous DCM results. As previously described, the direction of adjustment that resulted in the DCM results for foe DCA circuit seting of ~4 was decreasing the high duty cycle t t.e„ an adjustment of -2 rom a DCA circuit setting of -2 to -4 following time 17). With now adjusting the DC circuit settings to increase tile high duty cycle in order to find a lower boundary of the DCM offset, the direction of adjustment is changed to the plus direction, Cotwequently, the second step size is used to adjust foe DCA circuit seting from -4 to -3.

(9131 j The second step size may alternatively or additionally he used based on foe history of DCM results. For example, increasing foe settings for foe DCA circuit following time T9 by the first step, that is, 2 steps, would result in a DCA circuit setting of 4, which based on the DCM results from the DCM sequence between times T6 and 17, is known to he indeterminate The DCM results of OP[3:2j“ 00 indicate that the high: duty cycle for both conditions for the DCM is less than 50%. Thus, adjusting the settings for foe DCA circuit by foe second step following time T results in a DCA circuit seting of ~3 that has not yet been evaluated by a DCM sequence (as DCA circuit setings of -2 already has).

132] A sixth DCM sequence is performed between times T10 ami Tl 1 following She adjustment of She DCA circuit setting to - 3. whit.:!! result in sixth DCM results DCM results of OPj 3:21 ^::: 00. The sixth DCM results are determinate, and indicate that the high duty cycle for both conditions tor the DCM is less than 50%. With the DCA circuit settings of -3 resulting: in determinate DCM results, and indicating that the high duty cycle is les than 50% for both conditions, and further with the DCA circuit settings of 2 resulting in indeterminate DCM results from the DCM: sequence between times T6 an 17, it can be concluded that the DCA circuit setting of -2 represents a lower boundary of the DCM offset

{01331 This, in the example operation of Figure 13, the boundaries for (he DCM offset are determined to be the DCA circuit settings of 0 and -2,

{©134} As previously described with reference to Figure 12, a DCA circuit seting that is withi the boundaries of the DCM offset may result in an acceptable setting for the DCA circuit. An intermediate DCA circuit setting that is midway (or close to midway) between the boundaries o f the DCM offset may resul t in a least unsatisfactory setting for the DCA circuit. With reference to the example operation of Figure 13, the DCA circuit setting of ~1 is an intermediate DCA circuit setting that is midway between the DCM offset boundaries of 0 and -2. Th DCA circuit setting of -3 .may provide an acceptable setting for the DCA circuit.

[0135] In contrast to the example operations of Figures 10 and i I, the example operations of Figure 12 and 13 includ identifying DCA circuit settings representing boundaries of a DCM offset. For the example operations of Figures 10 and 11, it was assumed that there was no DCM offset, and as a result, identifying die boundaries of a DCM offset was unnecessary. Based on the boundary DCA circuit settings, an intermediate DCA circuit seting between the boundary DCA circuit setings is used to set the DCA circuit. The example operation of Figures 10-13 may be combined partially or wholly to provide alternative embodiments of the disclosure.

[0136] Figure 14 is a diagram of an operation for seting a duty cycle adjuster (DCA) circuit according to an embodiment of the disclosure. The DCA circuit of the example operation of Figure 14 is considered to have a DCM offset. That is, the DCA circuit / includes a range of measurement error resulting from circuit variation and mismatch, in the example operation of Figure 14, the DCM offset is over a range of about 6 steps of DCA settings.

[6137] Prior to time TO, the DCA circuit 1$ set to an adjustment of 0, for example, following an initialization of the DCA circuit. At time TO a first DCM sequence is started and at time XI the first DCM sequence is stopped. During the first DCM sequence between times TO and XL, first DCM resuits are determined. The DCM results from the first DCM sequence are OPi F2 j 00, indicating that the high duty cycle for both conditions is less than S©%. The first DCM results are evaluated and opcodes for setting the DCA circuit are changed to cause an increase in the high duty cycle of internal clocks. As shown in Figure 14, the DCA circuit is adjusted by a first step size, for example, 2 steps, following time XI to increase the setting of the DCA circuit to *2 and increase the high duty cycle.

j®l38{ Following the 2 step increase to a DCA circuit setting of +2 following time Tl, a second DCM sequence is started at time T2 and stopped at time T3. During the second DCM sequence between times T2 and T3, second DCM results are determined. The DCM results from the second DCM sequence are indeterminate. Given that the DCM results are indeterminate, and an overshoot: in the, DCA settings has not resulted in a definite change from the previous DCM results OF[3:2] ^:::: 00 from the DCM sequence between times TO and Ti , the indeterminate DCM results from the DCM sequence between times T2 and T3 is considered within a range of error for the DCM, that is, within the DCM offset of the DCM.

[0139] Following the indeterminate DCM results following rime T3 from the DCA circuit setting of 2 the setting for the DCA circuit is adjusted by the first step size of 2 stops t s continue increasing the DCA circuit setting. The resulting DCA circuit setting is , A third DCM sequence is performed between times T4 and T5. The resulting third DCM results are Indeterminate, which indicate that the DCA circuit setting of +4 is still within the range of the DCM offset The DCA circuit setting is increased again following time T5 by the first step size of 2 steps to continue increasing the DCA circuit seting. The resulting DCA circuit settin is +6. A fourth DCM sequence is performed between times Tb and T7. The resulting fourth DCM results are again indeterminate, which indicate that the DCA circuit setting of -H> is still within the range of the DCM offset. The DCA circuit setting is increased again following time T7 to find a boundary of the DOM offset. With the DCA circuit setting: already at Kyand a maximum DCA circuit setting of -t 7, foe DCA circuit setting is adjusted by 1 step to increase the DCA circuit setting to +7.

jtS4Q j A fifth DCM sequence is performed between times T8 and T9, which results in fifth DCM results of OPj 3:2]“ 1 1. The fifth DCM result are determinate, and indicate that the high ditty cycle for both conditions for the DCM is greater than 50%. With the DCA circuit settings of +7 resulting in determinate DCM results, and indicating that the high duty cycle is greater than 50% for both conditions, and further with foe DCA circuit settings, of +6 resulting in indeterminate DCM results, it can be concluded that the DCA circuit setting of H> represents an upper boundary of the DCM offset The lower boundary of the DCM offset remains to be determined.

[8!41 j To determine foe lower boundary of the DCM offset, the DCA circuit setting is adjusted relative to the: DCA setting of +2. which as previously described, resulted in indeterminate DCM results from the DCM sequence between times T2 to T3. With the DCA circuit setting of 2 resulting in indeterminate DCM results, and searching for a tower boundary of the DCM offset, foe DCA circuit settings are adjusted to decrease a high dut cycle. The DCA settings are adjusted by a second step size that is less than the first step size, for example, 1 step, to reduce the setting of the DCA circui from +2 to l .

{0142} The second step size of 1 step ma be used to adjust foe DCA circuit settings because, for example, there is a change to direction of adjustment for foe DCA circuit setting relative to foe direction of adjustment that resulted in the indeterminate DCM results. As previously described, the direction of adjustment that resulted in the indeterminate DCM results from the DCA cucuii setting of was increasing the high duty Cycl (i,e., an adjustment of a 2 step increase from a DCA circuit seting oft ⁾ to 2 following time TI). With now adjusting: foe DCA circuit settings to decrease the high dut cycle in order to find & lower boundary of foe DCM offset the direction of adjustment is changed to the minus direction. Consequently, the second step size is used to adjust foe DCA circuit setting from†2 to Ή .

jM43] Tire second step size of 1 step may aliemaii vely or additionally ire used based on the history· of DCM results. For example, decreasing foe settings for the DCA circuit following time T9 by the first step, that is, 2 steps, would result in a DCA circuit setting of 0, which based on the DCM «suits from the DCM sequence between times TO and XL is known to be OP| 3:2] ^« = 00, The DCM results of OP|3:2] ^» 00 indicate that the high duty cycle for both conditions for the DCM is less than 50%. Thus, adjusting the settings for the DCA circuit by the second step fol lowing tmie T9 results in a DCA circuit selling of i-l that has not yet been evaluated by a DCM sequence (as DCA circuit ttings of 0 already has).

10144] A sixth DCM sequence is performed between times II 0 and Tl I following the adjustment of the DCA circuit setting to H , which result in sixth DCM results that are indeterminate. With the DCA circuit settings of -H resulting m indeterminate DCM results, and further with the DCA circuit setings of 0 resulting in determinate DCM results of OP[3:2] 00, it can be concluded that foe DCA circuit setting oi> 1 represents a lower boundary of the DCM offset.

j 91451 Thus, in the example operation erf ^’ Figure 14, the boundaries for the DCM offset are determined' to be the DCA circuit settings of *! and

[8146] As previously described with reference to Figures 12 and 13, a DCA circuit seting that is within the boundaries of the DCM offset may result in an acceptable setting for the DCA circuit. For example, an intermediate DCA circuit setting that is midway (or close to midway) betwee the boundaries of the DCM offset may result In a least unsatisfactory setting for foe DCA circuit. With reference to the example operatic» of Figure 14, the DCM offset between +1 and *6 include an even number of DCA circuit settings, namely, 6 steps. As a result, no one DCA circuit setting is midway between the boundaries of the DCM offset However, both DCA circuit settings of 3 and *4 are intermediate DCA circuit settings that are dose to midway between the boundaries of* 1 and *6 of the DCM offset Thus, a DCA circuit setting of +3 or +4 ay provide an acceptable setting for foe DCA circuit.

18147] The choice between two intermediate DCA circuit settings in a DCM offset may ^¬ be based on, for example, a preference for a resulting internal clock signal to have a high duty cycle of greater than 50% or to have a high duty cycle of less than 50%. The choice between two intermediate DCA circuits settings in a DCM offset may be based on alternative and/or additional considerations without departing from the scope of the disclosure. In a specific example operation of Figure 14, the DCA circuit is set to +3. However, setting the DCA cireuit to a lower setting of two intermediate DCA circuit settings, or to the DCA circuit _: setting that is closer to a 0 setting is- not intended to limit the scope of the disclosure.

81481 Figure 15 is a diagram of an operation for setting a duty cycle a j ter (DCA) circuit according to an embodiment of the disclosure. The DCA circuit of the example operation of Figure 15 is considered to have a DCM offset That is, the DCA circuit includes a range of me&suremehi error resulting from circuit variation. and mismatch. In the example operation of Figure 15, the DCM offset is over a range of about 6 steps of DCA settings.

[01491 Prior to time Til the DCA circuit is set to an adjustutent of 0, for example, following an initialization of the DCA circuit. At time TO a first DCM sequence is started and at time Tt the first DCM sequence is stopped. During the first DCM, sequence between times TO and XL first DCM results are determined. The DCM results from the first DCM sequence are indeterminate. Given that the DCM results are indeterminate, and there have not been any IX L circuit settings that have resulted in determinate DCM results, the DCA circuit setting that resulte in the indeterminate DCM results from the DCM sequence between times TO and Tl are considered within a range of error for the DCM, that is, within the DCM offset of the DCM .

[0150] Following the indeterminate DCM result following time Tl from the DCA circuit setting of 0, the setting for the DCA circuit is adjusted by a first step size of 2 steps. In the example operation of Figure 15, the DCA circuit setting is increased by the first step size to +2, However, in other embodiments of the disclosure, the DCA circuit setting may be decreased by the first step size when an initial DCA circuit setting is -A Ulan a DCM offset.

[0I51| A second DCM sequence is performed between times 12 and 1 ^' 3 for the DCA circuit setting of +2 to determine second DCM results. The second DCM results are OP[3:2] - 1.1. As previously described, the 1 1 DCM results indicate that the high duty cycle for both condition for the DCM is greater than 50%. The second DCM results are evaluated and opcodes for setting the DCA circuit are changed to cause a decrease In the high duty cycle. As shown in Figure 15, the DCA circuit setting is adjusted by a second step size that is less than the first ste size, for example, 1 step, .following time 1 to reduce the setting of the DCA cireuit from s-2 to M, and decrease foe high duty cycle. [§152] The second step size of I step may be used to adjust the DCA circuit settings because, for example, there is a change in direction of adjustment for the DCA circuit setting relative to the previous direction of adjustment. As previously described, the direction of adjustment that resulted in the DCM results OP 3.2J 1 1 for the DCA circuit setting of s-2 was increasing the high duty cycle (i.e., an adjustment of a 2 step increase from a DCA circuit setting of 0 to†2 foliowing time XI). With now adjusting the DCA circuit settings to decrease the high duty cycle, the direction of adjustment is changed to the minus direction. Consequently. the second step size is used to adjust the DCA circuit setting from - to +L The second step size may alternatively or additionally he used base on the history of DCM results, For example, decreasing the settings for the DCA circuit following time 13 by the first step, that is, 2 steps would result in a DCA circuit setting of 0, which based on the DCM results from the DCM sequence between times TO and Ti , is known to be indeterminate. hus, adjusting the settings for the DCA circuit by the second step following time T3 results in a DCA circuit setting of+1 that has not yet been evaluated by a DCM sequence (as DCA circuit settings of 0 already has).

[§153] A third DC sequence may be performed between times T4 and T5 for the DCA circuit setting of Ή , which results in third DCM results that are indeterminate. With the DCA circuit settings of + 1 resulting in indeterminate DCM results, and further with the DCA, circuit settings of 2 resulting in determinate DCM results of OP[3:2) 11, it can he concluded that the DCA circuit setting of Ή. represents an upper boundary of the DCM offset The lower boundary of the DC : offset remains to be determined.

[§154] To determine the lower boundary of the DCM offset, the DCA circuit setting is adjusted relative to "the DCA seting of 0, winch as previously described, resulted in indeterminate DCM results >m the DCM sequence between times TO to TI . With the DCA circuit setting of 0 resulting in indeterminate DCM results, and searching for a lower boundary of the DCM offset, the DC A circuit settings are adjusted to decrease a high duty cycle _* The DCA setings are adj usted by the first step size to reduce the setting of the DCA circuit fro Q to -2. The first step size of 2 steps may be used because there are no DCM results for decreasing adjustments of the DCA circuit settings.

[§155] A fourth DCM sequence is performed between times T6 and 17. The resulting fouiih IX M results are indeterminate, which indicate that the DCA circuit setting of -2 is wrthrn the range of the DCM offset. The DCA circuit setting is decreased again following time T7 to find a lower boundary of die DOM offset Following die indeterminate DCM results following time T? from the DCA circuit setting of -2, the setting for the DCA circuit is adjusted by the first step size of 2 steps to continue decreasing the DCA circuit setting. The resulting DCA circuit setting is -4. A fifth DCM sequence is performed between times T8 and T9. The resulting fifth DCM results are also indeterminate, which indicates that the DCA circuit setting of -4 is still within the range of the DCM offset. Following the indeterminate DCM results following time T9 from the DCA circuit seting of -4, the seting for the DCA circuit is adjusted by the first step size of 2 steps to continue decreasing: the DCA circuit seting. The resulting DCA circuit setting is -6.

jl!56j A sixth DCM sequence is performed between times T 10 an T11 , The resulting fifth DCM results are 0:P[3:2] ······= 00, which indicate that the high duty cycle for both conditions for the DCM is less than 50% The sixth DCM results are evaluated and opcodes for the DCA circuit setting are changed to cause an increase in the high duty cycle. As shown in Figure 15, the DCA circuit is: adjusted by the second step size of 1 step following time 19 to increase the setting of the DCA circuit from -6 to -5 and increase the high duty cycle.

jitl57| The second step size may be used to adjust the DCA circuit settings to -5, for example, following the change i direction of adjustment for the DCA circuit seting relative to the direction of adjustment that resulted in the previous DCM results. As previously described, the direction of adjustment that resulted in the DCM results for the DCA circuit setting of -6 was decreasing the high duty cycle (le., an adjustment of a 2 step decrease from a DCA circuit setting of ~4 to -6 following tune T9). Willi now adjusting the DCA circuit setings to increase the high duty cycle in order to find a lower boundary of the DCM offset, the direction of adjustment is changed to the plus direction. Consequently, the second step size is use to adjust the DCA circuit setting from -6 to - S,

{0158} The second step size may alternatively or additionally be used based on the history of DCM results. For example, increasing the setings for the DCA circuit following time Tl I by the first step, that is, 2 steps, would result in a DCA circuit setting of , which based on the DCM results from the DCM sequence between times T8 and T9, is known to be indeterminate. The DCM results of 0P[3:2 j ^® 00 from the DCM sequence between times T IO and ^' P I indicate that the high duty cycle for both conditions for foe DCM is less than 50%, Thus, adjusting the settings for the OCA circuit by foe second step following time Til results in a DC A circuit setting of ~5 that has not yet been evaluated by a DCM sequence (as DCA circuit settings of -4 already has).

|915f[ A seventh DCM sequence is performed between times T12 and T 13 following foe adjustment of foe DCA circuit setting to -5, which result in sixth DCM results in DCM results of OF| 3:2] ^::: 00 The seventh DCM results are determinate, and indicate that the high duty cycle for both conditions for foe DCM is less than 50%. With the DCA circuit settings of -5 resulting in determinate DCM results, and indicating that foe high duty cycle is less than 59% for both conditions, and further with the DCA circuit settings of -4 resulting in indeterminate DCM results from the DCM sequence between times T8 and T9, it can be concluded that the DCA circuit setting of -4 represents a lower boundary of the DCM offset.

j®t«0| Thus, in the example operation of Figure 15, the boundaries for the DCM offset are determined to be the DCA circuit settings of -4 and 4-1 ,

[81611 As previously described with reference to Figures 12-14, a DCA circuit setting that is within foe boundaries of the DCM offset may result an acceptable setting for the DCA circuit An intermediate DCA circuit setting that is midway Cor close to midway) between foe boundaries of foe DCM offset may result in a least unsatisfactory setting for foe DCA circuit. With reference to the example operation of Figure I S the DCM offset between -4 and -Kl include an even number of DCA circuit sellings. namely , 6 steps. As a result* no one DC A circuit setting is midway between foe boundaries of the DCM offset. However, both DCA circuit settings of -2 and -1 ate intermediate DCA circuit settings that are close to midwa between the boundaries of -4 to 4-1 of the DCM offset. Thus a DCA circuit setting of -2 or - 1 ma provide an acceptab le setting for the DCA circuit

[91621 The choice between two intermediate DCA circuit settings in a DCM offset may be based on, for example, a preference for a resulting infernal clock signal to have a high duty cycle of greater than 50% or to have a high duty cycle of less than 50%. The choice between two intermediate DCA circuits settings in a DCM offset may be based on alternative and/or additional considerations without departing from the scope of the disclosure. In a specific example operation of Figure 15, the: DCA circuit is set to -1 . However, setting foe DCA circuit to a higher setting of two intermediate DCA circuit settings, or to the PC A circuit setting that is closer to a 0 setting is not intended to limit the scope of the disclosure.

|M63l In contrast to the example operations of Figures 12 and 13, the example operations of Figures 14 and 13 include identifying DCA circuit settings representing boundaries of a DCM offset thru includes an even number of DCA circuit sellings. With reference to Figures 12 and 13, it was assumed that the DCM offset included an odd number of DCA settings, and as a result, t em was one DCA circuit setting midway between the boundaries of the DCM offset. As a result of having an eve number of DCA circuit settings in the DCM offset no one DCA circuit setting is midway between the boundaries of the DCM offset, hut instead two DCA circuit settings ate intermediate DCA circuit settings that are close to midway between the boundaries of the DCM offset.

One of the two intermediate DCA circuit settings mav be selected to set the DCA circuit.

Various considerations may he made in selecting which of the two intermediate DCA circuit setting to set. The example operations of Figures 10-15 may be combined partially or wholly to provide alternative embodiments Of the disclosure.

[§164] The example operations of F igures 1045 describe embodiments of the disclosure that include changing the DCA co e by multiple step sixes (e.g , more than one step size) and/or identifying a DCM offset in terms of a range of DCA codes to identify a DCA code setting for a DCA circuit. Using: multiple step sixes (e.g., fast speed and slow speed) and/or identifying a range of DCA codes for DCM offset may be combined in various manners to provide alternative embodiments of the disclosure. Moreover, embodiments of disclosure described with reference to _: Figures 1 5 may be included in various combinations to provide alternative embodiments of the disclosure,

[§165] As previously described, the range of adjustment for the DCA of the operations of Figures 1045 is *7 to -7. However, m some erobodiments ofthe disclosure, the range of DCA adjustment may be greater than +7 to -7. An example of such an embodiment may include a range of DCA adjustment of Ή5 to - I S. in same embodiments of the disclosure, the range of DCA adjustment may be dess than 7 to -7. An example of such an embodiment may include a range of DCA adjustment of +4 to Thus, embodiments of the disclosure are not limited to _: the particular range of adjustment of 37 to -7 as specifically described for the operations of Figures 1045. [8166] As previously described, multiple step sizes may be used in changing from one DCA code to another. For example, the operations of Figures 10~ 1 were described as including _: first and second step sizes. However, _: in some embodiments of the disclosure _* a greater number of step sizes may be i ncluded. For example, some embodiments of the disclosure include three step sizes. Although not limited to such additional step sizes may facilitate identifying an acceptable DCA code where a range of adjustment « greater than +7 to -7 (e,g„ +15 to 45). Additionally, the size of the steps may be different than described with reference to the operations of Figures 10 5 (e.g., 2 steps and 1 step). For example, some embodi ents of the disclosure may include steps sizes of 4 steps arid 2 steps. Thus, embodiments of the disclosure are not limited to the particular number of step sizes and sizes of steps previously described for Figures 10-15.

fM&7 j From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating front the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appende claims.