Title:
ARCHITECTURE GENERATING DEVICE AND ARCHITECTURE GENERATING PROGRAM
Document Type and Number:
WIPO Patent Application WO/2017/046941
Kind Code:
A1
Abstract:
A specification editing unit (130) edits a hardware specification file (193) in order to replace a plurality of arrays which is used in a plurality of processes with a common array. If the edited hardware specification file does not satisfy a constraint, a specification transform unit (150) transforms the hardware specification file for parallel execution of the plurality of processes. An architecture generating unit (160) generates an architecture file (194) which represents the architecture of a system on chip (SoC) which comprises hardware which corresponds to the hardware specification file.
Inventors:
OKADA NAOYA (JP)
YAMAMOTO RYO (JP)
MURANO KOKI (JP)
OGAWA YOSHIHIRO (JP)
MINEGISHI NORIYUKI (JP)
YAMAMOTO RYO (JP)
MURANO KOKI (JP)
OGAWA YOSHIHIRO (JP)
MINEGISHI NORIYUKI (JP)
Application Number:
PCT/JP2015/076656
Publication Date:
March 23, 2017
Filing Date:
September 18, 2015
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
International Classes:
G06F17/50
Foreign References:
| JP2013254472A | 2013-12-19 | |||
| JP2013125419A | 2013-06-24 | |||
| JP2014106639A | 2014-06-09 |
Attorney, Agent or Firm:
MIZOI, Shoji et al. (JP)
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