Technical Field

The invention relates to ARINC-429 IP core design that enables the filtering process to be implemented in the FPGA, thereby reducing the workload on the processor.

State of the Art

ARINC (Aeronautical Radio, Incorporated) 429 is a data bus standard used in avionics systems and is used in almost all commercial aircraft. ARINC 429 is an aeronautical standard that defines both an architecture, an electrical interface and a protocol for carrying digital data. It is a specification defining a local area network for the transmission of digital data between avionics system elements. The electrical and data format characteristics are defined for a two-wire serial data bus with one transmitter and up to 20 receivers. The data bus can operate at a speed of 100 kbit/s.

In the prior art, multiple channel counts are supported up to 16 transmitter and 16 receiver channels, compliant with the ARINC-429 standard. The designed IP interface includes a 32-bit wide programmable depth FIFO (First In First Out) for transmit and receive operations. Further, a noise filtering mechanism is also designed at the receiver side. The IP design is in compliance with DO-254 DAL-A (DO-254 is a guideline developed by the Radio Technical Commission for Aeronautics (RTCA Inc.) to facilitate and systematize certification).

In another prior art, the IP core supports multiple label counts. The design provides transmitter and receiver blocks with FIFO. It has direct access to all registers. The design can operate at data rates up to 2.5 Mbit/s.

In another prior art, independent channel configuration is provided by a processor interface. There is a 63-word deep FIFO interface for each input ARINC 429 channel and a 31-word deep FIFO interface for each output channel. A FIFO is available for each channel to ensure efficient transfer between the processor and IP. Many tools such as Xilinx Vivado, Microsemi Libero, Altera Quartus are supported.

The filtering process of ARINC 429 messages used in the prior is performed by the processor and causes time loss in the software.

As a result of the search conducted on the subject, CN109445325A has been found. The application relates to a high-speed ARINC 429 data processing method based on FPGA (Field Programmable Gate Arrays). The document comprises a CPU (Central Process Unit), an FPGA unit and a transceiver driver unit, and describes a high-speed ARINC 429 data processing method based on the FPGA. The CPU channel controls the speed and transmission information. However, there is no description of the implementation of the filtering process in the FPGA.

Therefore, it has become necessary to make an improvement in the relevant technical field due to the drawbacks mentioned above and the inadequacy of the existing solutions.

Object of the Invention

The invention is inspired by the current situation and aims to solve the drawbacks mentioned above.

The main object of the invention is to reduce the workload on the processor by implementing the filtering process in FPGA in ARINC-429.

Another object of the invention is to implement an HDL IP design that is compatible with the ARINC-429 standard, that supports multiple transmitter and receiver channels and has a processor interface.

In order to achieve the objects mentioned above, the invention is an ARINC-429 IP core that enables the filtering process to be implemented in FPGA and reduces the workload on processor, comprising:

• internal memory that stores the channel number, data transmission rate, the number of times the data will be sent, and the time offset information needed during periodic data transmission,

• FIFO, which allows the received ARINC 429 data to be written together with the "timetag" information and which is the data for which memory address where to be written is decided according to the "filter option" value,

• receiver that operates in accordance with the ARINC-429 specification, where the number of channels can be set by the user and the Rx blocks enable operation in accordance with the ARINC-429 specification,

• transmitter that operates in accordance with the ARINC-429 specification, where the number of channels can be set by the user and the Tx blocks enable operation in accordance with the ARINC-429 specification,

• control unit that allows writing operations to be made in the registers of the IP core, activate the channels, initiate rx-tx test and memory test, and check the IP status by reading the register addresses, Custom Programmable Integrated Data Bus Slave, which has 32-bit read and write channels and provides communication with the control unit, and

• Custom Programmable Integrated Data Bus Master, which has 32-bit read and write channels and provides communication with external memory.

The structural and characteristic features and all advantages of the invention will be more clearly understood by means of the figures given below and the detailed description written by making references to these figures, and therefore, evaluation should be made by considering these figures and detailed description.

Figures to Help Understand the Invention

Figure 1 is a representative view of the ARINC-429 IP core architecture of the invention.

Figure 2 is a representative view of the filter table used in the invention.

Description of Part References

1. Custom Programmable Integrated Data Bus Slave

2. Custom Programmable Integrated Data Bus Master 2x

3. Internal Memory

4. FIFO’s (first in, first out)

5. Receiver

6. Transmitter

7. External Memory

8. Control Unit

Detailed Description of the Invention

In this detailed description, the preferred embodiments of the ARINC-429 IP core design of the invention are described only for a better understanding of the subject matter.

The IP design, which is compatible with the ARINC-429 standard and has a processor interface that supports multiple transmitter and receiver channels, is implemented using the hardware description language VHDL (Very high speed integrated circuit Hardware Description Language). The developed IP allows for independent channel configuration and meets the requirements of the basic ARINC-429 standard, as well as extra features such as filtering, status management or error handling. By performing the filtering of ARINC-429 data in the FPGA, it is aimed to reduce the workload on the control unit (8). The subject of the ARINC-429 IP core design is briefly related to the IP features and how the filtering process is done in the FPGA. The ARINC-429 IP core architecture comprises Custom Programmable Integrated Data Bus Slave (1), Custom Programmable Integrated Data Bus Master (2), internal memory (3), FIFO (4), receiver (5) and transmitter (6) design blocks as shown in Figure 1. The receiver (5) and transmitter blocks are the blocks that operate with the receiver (5) and transmitter (6) channels in accordance with the ARINC-429 specification. There is a slave block that provides communication with the control unit (8) and a master block that provides communication with the external memory (7). The number of receiver (5) and transmitter (6) channels can be set by the user. IP supports up to 16 transmit (6) channels and up to 32 receive (5) channels. At the same time, the general parameters of receiver length and transmitter length are defined according to the number of channels used. These parameters can be adjusted by the user according to the number of bits that will be used in the design according to the number of channels. Thus, the ram/memory allocated for each channel can be used efficiently.

In the IP design, two storage areas are available for ARINC-429 data transmission. These are the individual and the snapshot buffers. These buffers are available for each channel and have a depth of 1024 "words". The addressing for the individual buffer is determined by the write pointer and read pointer updated by the CPU. During data transmission, the ARINC-429 IP core sends the data at the individual buffer address specified by the read pointer, while the received data is written to the memory address specified by the write pointer. The snapshot buffer address information consists of 3 different fields. These are 2-bit SDI (Source Destination Identifier), 8-bit Label and 2-bit type data. The received ARINC-429 data is written to the relevant part of the snapshot buffer according to this addressing mechanism. Periodic data transmission is provided depending on the data rate, channel number, time offset value and the number of times the data is to be transmitted, which are stored in the internal memory (3). On the IP core receiver (5) side, there are two storage areas as on the transmitter (6) side. The information about which storage area the received ARINC-429 data will be written to is provided by the filtering mechanism. The storage area is selected according to the data in the filter table. This table is kept in external memory (7) and the addressing information to access this data is designed as shown in Figure 2. Bits 31-22 of the address comprises the base address information; the other bit values change according to the number of transceiver channels as shown in figure 2. The "filter table base address" is defined by the ARINC-429 IP. In the filtering process, the addressing mechanism is established using the label, SDI (source destination identifier) and ssm (sign status matrix) bit fields of the received ARINC-429 data. Label comprises the first 8 bits of the ARINC-429 data. SDI field comprises bits 9 and 10 and essm field comprises bits 31 , 30, 29. According to this address information, it is decided which memory area to write the filter table value that is read from external memory according to the Isb (least significant bit) 2 bit. If it is "00", the received 429 data is first written to the snapshot buffer and then to the individual buffer. If it is "10", it is written to the individual buffer in SRAM. When it is "01", it is written to the snapshot buffer in SRAM; when it is "11", the received data is not written anywhere.

As described above, after deciding which memory area to write to, the memory address where the data will be written is determined as follows: the first 10 bits of the address comprises the label and SDI bit fields of the received data. The 10-12 bit field is essm. In the design, for the other bits of the 20-bit long address bus, an internal look-up table (lut) is defined according to the general parameters of receiver length (rx_bit_length) and transmit length (tx_bit_length). According to the addressing determined in this way, ARINC-429 data, "timetag_1", "timetag_2" and channel number information are written to the relevant memory address.

In the architecture proposed in the ARINC-429 IP core design, the filter table values are stored in external memory (7). To read the filter value, the filter table address is defined by ip. After deciding the storage area according to the read "filter_option" value, the buffer address where the data will be written is also determined by ip as described above. Thus, the filtering mechanism is implemented in the FPGA, reducing the workload on the control unit (8).