Title:
ARITHMETIC PROCESSING APPARATUS, IMAGE PROCESSING APPARATUS, AND IMAGE CAPTURE APPARATUS
Document Type and Number:
WIPO Patent Application WO/2018/029782
Kind Code:
A1
Abstract:
An arithmetic processing apparatus has a pipeline structure in which combinations of a combination circuit and a flipflop circuit group composed of a plurality of flipflop circuits corresponding to the respective bits of output data of the combination circuit are connected in a plurality of stages. The arithmetic processing apparatus is provided with a mask processing unit for controlling the masking of operation clock signals to be supplied to the respective flipflop circuits. The mask processing unit controls the masking of the operation clock signals to be supplied to the respective flipflop circuits on the basis of bits to be used for arithmetic processing in input data inputted to the combination circuits.
Inventors:
YANADA TAKASHI (JP)
UENO AKIRA (JP)
UENO AKIRA (JP)
Application Number:
PCT/JP2016/073431
Publication Date:
February 15, 2018
Filing Date:
August 09, 2016
Export Citation:
Assignee:
OLYMPUS CORP (JP)
International Classes:
H03K19/00
Domestic Patent References:
| WO2013042264A1 | 2013-03-28 |
Foreign References:
| JP2009187075A | 2009-08-20 | |||
| JP2013125436A | 2013-06-24 | |||
| JPH1127109A | 1999-01-29 |
Attorney, Agent or Firm:
TANAI Sumio et al. (JP)
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