TECHNICAL FIELD

Embodiments of the invention are in the field of integrated circuit fabrication and, in particular, array interconnects for resistive random access memory (RRAM) devices and their methods of fabrication.

BACKGROUND

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of

semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. It has become increasingly significant to rely heavily on innovative fabrication techniques to meet the exceedingly tight tolerance requirements imposed by scaling.

Non-volatile embedded memory with RRAM devices, e.g., on-chip embedded memory with non-volatility, can enable energy and computational efficiency. However, in addition to the technical challenges of creating an appropriate material stack for fabrication of RRAM devices that exhibit high performance (e.g., endurance, high retention and operability at low voltages and currents etc.), methods to connect a large array of memory cells in the least complicated manner presents formidable roadblocks to scaling of RRAM technology today. Specifically, as the size of the RRAM devices are scaled adding multiple layers of interconnects to connect each cell necessitates tighter process control and innovative techniques, and potentially may involve increasing series resistance to the circuitry. To address the challenges of meeting low voltage requirements of embedded RRAM devices at scaled dimensions and intricate geometries there is greater emphasis on improving interconnect engineering. Process development of interconnect engineering is an integral part of the non-volatile memory roadmap. BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1A illustrates an angled cross-sectional view of an array interconnect formed in a trench above an array of RRAM cells, in accordance with an embodiment of the present invention.

Figure I B illustrates a cross-sectional view of the array interconnect structure of Figure 1 A, as taken through the A- A' axis. Figure 1C illustrates a cross-sectional view of the array interconnect structure of Figure 1 A, as taken through the B-B' axis.

Figure 2 A illustrates an angled cross-sectional view of an array interconnect formed in a trench, and a via formed above each RRAM cell in an RRAM array, in accordance with an embodiment of the present invention.

Figure 2B illustrates a cross-sectional view of the array interconnect structure of Figure 2A, as taken through the A-A' axis.

Figure 2C illustrates a cross-sectional view of the array interconnect structure of Figure 2A, as taken through the B-B' axis.

Figures 3 A-3J illustrate cross-sectional views representing various operations in a method of fabricating an RRAM device integrated on a conductive interconnect, in accordance with an embodiment of the present invention.

Figure 3 A illustrates a conductive interconnect surrounded by a first dielectric layer.

Figure 3B illustrates the structure of Figure 3 A following the formation of a material layer stack for an RRAM application on the conductive interconnect.

Figure 3C illustrates the structure of Figure 3 B following the formation of a resist pattern on a dielectric hardmask layer formed on the material layer stack.

Figure 3D illustrates the structure of Figure 3C following an etch process used to transfer the resist pattern into the dielectric hardmask layer.

Figure 3E illustrates the structure of Figure 3D following the removal of the resist pattern.

Figure 3F illustrates the structure of Figure 3E following an etch process used to transfer the pattern of the dielectric hardmask layer into the material layer stack to form an RRAM device.

Figure 3G illustrates the structure of Figure 3F following the formation of a dielectric spacer layer covering the sidewalls of the resistive RRAM device, an uppermost portion of the dielectric hardmask layer and the top of the first dielectric layer surrounding the conductive interconnect.

Figure 3H illustrates the structure of Figure 3G following an anisotropic plasma etch of the dielectric spacer layer to form a dielectric spacer.

Figure 31 illustrates the structure of Figure 3H following the formation of a second dielectric layer covering the resistive random access memory device, the dielectric hardmask layer, the dielectric spacer and the first dielectric layer surrounding the conductive interconnect.

Figure 3 J illustrates the structure of Figure 31 following planarization of the second dielectric layer, the dielectric spacer, and the top portion of the top electrode. Figure 3K illustrates an angled view of an array of RRAM cells of the type illustrated in Figure 31, in accordance with an embodiment of the present invention.

Figures 4A-4D illustrate various operations in a method of fabricating an array interconnect on an array of RRAM cells of the type described in association with Figure 1 A, in accordance with an embodiment of the present invention.

Figure 4A illustrates various cross-sectional views of the structure of Figure 3K following the formation of a third dielectric layer on an RRAM cell array and formation of a resist pattern to define a trench location.

Figure 4B illustrates various cross-sectional and plan views of the structure of Figure 4A following an etch process to form a trench exposing the uppermost portion of top electrodes of each RRAM cell in an array, followed by mask removal.

Figure 4C illustrates various cross-sectional views of the structure of Figure 4B following the formation of a diffusion barrier layer in the trench, on the uppermost portion of each RRAM cell and the formation of a conductive fill layer on the diffusion barrier layer in the trench.

Figure 4D illustrates various cross-sectional views of the structure of Figure 4C following planarization of the conductive fill layer, diffusion barrier layer and the third dielectric layer.

Figures 5A-5J illustrate cross-sectional views representing various operations in a method of fabricating a resistive random access memory device integrated on a conductive interconnect, which may be used to fabricate a memory device such as described in association with Figure 2A, in accordance with an embodiment of the present invention.

Figure 5 A illustrates a conductive interconnect formed in a first dielectric layer above a substrate.

Figure 5B illustrates the structure of Figure 5 A following formation of a second dielectric layer on an uppermost surface of the conductive interconnect and on an uppermost surface of the first dielectric layer.

Figure 5C illustrates the structure of Figure 5B following patterning of a photoresist layer to form a mask to define a via location.

Figure 5D illustrates the structure of Figure 5C following an etch process to create a via in the second dielectric layer.

Figure 5E illustrates the structure of Figure 5D following removal of the mask.

Figure 5F illustrates the structure of Figure 5E following formation of a bottom electrode metal layer in the via and on the conductive interconnect.

Figure 5G illustrates the structure of Figure 5F following formation of a highly stoichiometric metal oxide switching layer in the via and on the bottom electrode metal layer. Figure 5H illustrates the structure of Figure 5G following formation of a sub- stoichiometric metal oxide layer in the via and on the highly stoichiometric metal oxide switching layer.

Figure 51 illustrates the structure of Figure 5H following formation of a top electrode metal layer in the via and on the sub-stoichiometric metal oxide layer.

Figure 5 J illustrates the structure of Figure 51 following a planarization process to form a top electrode, a sub-stoichiometric metal oxide layer, a highly stoichiometric metal oxide switching layer, and a bottom electrode.

Figure 5K illustrates an angled view of an array of RRAM cells of the type illustrated in Figure 5J, in accordance with an embodiment of the present invention.

Figures 6A-6F illustrate cross-sectional views representing various operations in a method of fabricating an array interconnect on an array of RRAM cells of the type described in association with Figure 2 A, in accordance with an embodiment of the present invention.

Figure 6A illustrates various cross-sectional views of the structure of Figure 5K following formation of a dielectric hardrnask layer on the RRAM cell array, formation of a third dielectric layer on the etch stop layer and formation of a resist pattern to form a trench mask.

Figure 6B illustrates various cross-sectional views of the structure of Figure 6 A following an etch process used to form a trench in the third dielectric layer, exposing an uppermost portion of the etch stop layer, followed by a mask removal.

Figure 6C illustrates various cross-sectional views of the structure of Figure 6B following formation of a resist pattern to define a via location.

Figure 6D illustrates various cross-sectional and plan views of the structure of Figure 6C following an etch process used to form a via in the etch stop layer, exposing an uppermost portion of the RRAM ceil, followed by a mask removal.

Figure 6E illustrates various cross-sectional views of the structure of Figure 61) following the formation of a diffusion barrier layer in the trench, on the top electrode of each RRAM cell and the formation of a conductive fill layer on the diffusion barrier layer in the trench.

Figure 6F illustrates various cross-sectional views of the structure of Figure 6E following planarization of the conductive fill layer, diffusion barrier layer and the third dielectric layer.

Figure 7 illustrates cross sectional views of an array interconnect where a diffusion barrier layer has a thickness that is approximately equal to the thickness of a dielectric hardrnask layer, in accordance with an embodiment of the present invention.

Figure 8 illustrates cross sectional views of an array interconnect where an array of RRA : devices represented by the structure of Figure 3 J are connected by an array interconnect of the type represented in Figure 6F, in accordance with an embodiment of the present invention. Figure 9 illustrates an I-V plot, demonstrating concepts involved with filament formation and voltage cycling (reading and writing) in an RRAM device, in accordance with embodiments of the present invention.

Figure 10 illustrates a cross-sectional view of an RRAM element coupled to a drain side of a select transistor, in accordance with an embodiment of the present invention.

Figures 11 A-l IE illustrate schematic views of several options for positioning an RRAM element in an integrated circuit, in accordance with embodiments of the present invention.

Figure 12 illustrates a schematic of a memory bit cell which includes a metal-conductive oxi de-metal RRAM devi ce, in accordance with embodiments of the present invention.

Figure 13 illustrates a block diagram of an electronic system, in accordance with embodiments of the present i nvention.

Figure 14 illustrates a computing device in accordance with embodiments of the present invention.

Figure 5 illustrates an interposer in accordance with embodiments of the present invention.

DESCRIPTION OF THE EMBODIMENTS

Array interconnects for resistive random access memory (RRAM) devices and their methods of fabrication are described. In the following description, numerous specific details are set forth, such as novel structural schemes and detailed fabrication methods in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features, such as switching operations associated with embedded memory, are described in lesser detail in order to not unnecessarily obscure embodiments of the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

To provide context, integrating a memory array with low voltage logic circuitry, such as logic circuitry operational at a voltage less than or equal to 1 Volt, may be advantageous since it enables higher operation speeds compared to having physically separate logic and memory chips. Additionally, approaches to integrating an RRAM device onto a transistor to create an embedded memory array presents material challenges that have become far more formidable with scaling. As transistor operating voltages are scaled down in an effort to become energy efficient, RRAM memory devices that are connected in series with such transistors are also required to function at lower voltages and currents. Embedded memory arrays may be characterized by RRAM devices that are connected together by a series of interconnects. To provide device functionality in connection with RRAM devices at scaled dimensions, interconnects may require innovations in structure, materials and architecture that overcome limitations imposed by tight spaces, limited layer thicknesses and alignment tolerances but still exhibit low line resistance. In accordance with an embodiment of the present invention, novel array interconnect schemes presented below can reduce the number of lithography steps, relax lithography alignment and ease metal fill requirements through elimination of high-aspect ratio via formation and can be fabricated with potentially reduced process operations. Furthermore, specific embodiments of an array interconnect may include enhanced features such as an ability to contact specific portions of a plurality of RRAM devices at small dimensions, providing flexibility with respect to the choice of the RRAM architecture adopted.

In accordance with embodiments of the present invention, various examples of an array interconnect are described in association with Figures 1A-1C and Figures 2A-2C.

Figure 1 A illustrates an angled cross-sectional view of an array interconnect 101 formed in a trench 119 above an array of RRAM cells 130, in accordance with an embodiment of the present invention. Each RRAM cell 130 in the array includes an RRAM device 140 coupled to a single conductive interconnect 104. The conductive interconnect 104 is disposed in a first dielectric layer 102 above a substrate. The uppermost surface of the conductive interconnect 104 is coplanar with the uppermost surface of the first dielectric layer 102. An RRAM device 140 is formed on a conductive interconnect 104 and on the first dielectric layer 102. A dielectric spacer 1 14 surrounds an RRAM device 140. A second dielectric layer 116 is disposed adjacent to the dielectric spacer 1 14 and on the first dielectric layer 102, The dielectric spacer 114 extends from an uppermost surface of the first dielectric layer 102 to an uppermost surface of the second dielectric layer 1 16. An uppermost surface of the second dielectric lay er 1 16, the dielectric spacer 1 4 and the RRAM device 140 are coplanar or substantially coplanar. A third dielectric layer 1 18 is disposed on the RRAM device 140, the dielectric spacer 1 14 and on the second dielectric layer 116. An array interconnect 101 is disposed in a trench 119 formed in the third dielectric layer 118. The array interconnect 101 is coupled to a plurality of RRAM devices 140. The array interconnect 101 includes a diffusion barrier layer 120 disposed at a bottom of and along sidewalls of the trench 119. A conductive fill layer 122 is disposed on the diffusion barrier layer 120. A portion of the diffusion barrier layer 120 which is disposed in the bottom of the trench 119 is in contact with an uppermost surface of each of the plurality of RRAM devices 140, the dielectric spacer 14 surrounding each of the plurality of the RRAM devices 140 and the second dielectric layer 1 16. The uppermost surfaces of the conductive fill layer 122, the diffusion barrier layer 120 and the third dielectric layer 1 18 are coplanar or substantially coplanar.

The conductive interconnect 104 is disposed in a dielectric layer 102 disposed on a substrate 100. In an embodiment, the conductive interconnect 104 includes a barrier layer, such as but not limited to tantalum nitride, tantalum, ruthenium and cobalt, and a fill layer, such as copper, as is known in the art.

The RRAM device 140 includes a bottom electrode 106 disposed above the conductive interconnect 104. In an embodiment, a highly stoichiometric metal oxide switching layer 108 is disposed on the bottom electrode 106. A sub-stoichiometric metal oxide layer 1 10 is disposed on the highly stoichiometric metal oxide switching layer 108, A top electrode 112 is disposed on the sub-stoichiometric metal oxide layer 110.

In an embodiment, the bottom electrode 106 extends laterally onto a portion of the first dielectric layer 102, as is depicted in Figure 1A. In an embodiment, the bottom electrode 106 includes a layer such as but not limited to titanium nitride, tantalum, tantalum nitride, tungsten or ruthenium. In an embodiment, the bottom electrode 106 has a thickness approximately in the range of 40 to 100 nanometers (nm). In an embodiment, the composition and thickness of the bottom electrode 106 are tuned to meet specific device attributes such as series resistance, programming voltage and current. In an embodiment, a portion of the bottom electrode 106 at an interface between the bottom electrode 106 and the highly stoichiometric metal oxide switching layer 108 is oxidized. In one such embodiment, the bottom electrode 106 includes tungsten or ruthenium and the oxidized portion of the bottom electrode 106 remains conductive.

In an embodiment, the highly stoichiometric metal oxide switching layer 108 is composed of a metal (M), such as but not limited to, hafnium, tantalum or titanium. In the case of titanium or hafnium, or tantalum with an oxidation state +4, the highly stoichiometric metal oxide switching layer 108 has a chemical composition, MOx, where 0 is oxygen and X is or is substantially close to 2. In the case of tantalum with an oxidation state +5, the highly

stoichiometric metal oxide switching layer 108 has a chemical composition, M ₂ Ox, where O is oxygen and X is or is substantially close to 5. In an embodiment, the highly stoichiometric metal oxide switching layer 108 has a thickness approximately in the range of 1 -5 nm.

In an embodiment, the sub-stoichiometric metal oxide layer 110 acts as a source of oxygen vacancy or as a sink for O ^2" . In an embodiment, the sub-stoichiometric metal oxide layer 1 10 is less stoichiometric than the highly stoichiometric metal oxide switching layer 108. In an embodiment, the sub-stoichiometric metal oxide layer 1 10 is composed of a metal (M), such as but not limited to, hafnium, tantalum or titanium. In the case of titanium or hafnium, or tantalum with an oxidation state +4, the sub-stoichiometric metal oxide layer 110 has a chemical composition, Μ0 ₂ -γ, where O is oxygen and Y is approximately in the range of 0.01 to 0.05, In the case of tantalum with an oxidation state +5, the sub-stoichiometric metal oxide layer 110 has a chemical composition given by M ₂ 0 ₅ -Y, where O is oxygen and Y is approximately in the range of 0.01 to 0.05. In an embodiment, the sub-stoichiometric metal oxide layer 1 10 has a thickness approximately in the range of 3-20 ran.

In an embodiment, the metal (M) of the highly stoichiometric metal oxide switching layer 08 is the same as the metal (M) of the sub-stoichiometric metal oxide layer 110. In another embodiment, the metal (M) of the highly stoichiometric metal oxide switching layer 108 is different than the metal (M) of the sub-stoichiometric metal oxide layer 1 10. In an embodiment, the highly stoichiometric metal oxide switching layer 108 is more stoichiometric than the sub- stoichiometric metal oxide layer 110 by at least 0.1% in oxygen content. In one embodiment, the highly stoichiometric metal oxide switching layer 108 is more stoichiometric than the sub- stoichiometric metal oxide layer 110 by at least 0.2% in oxygen content. In an embodiment, the thickness of the sub-stoichiometric metal oxide layer 110 is at least twice the thickness of the highly stoichiometric metal oxide switching layer 108. In another embodiment, the thickness of the sub-stoichiometric metal oxide layer 110 is at least three times the thickness of the highly stoichiometric metal oxide switching layer 108.

In an embodiment, the top electrode 112 is composed of a layer such as, but not limited to, titanium nitride, tantalum nitride, tungsten and ruthenium. In an embodiment, the bottom electrode 106 and the top electrode 1 12 are composed of the same layer. In an embodiment, the top electrode has a thickness approximately in the range of 20 to 100 nm. In an embodiment, the composition and thickness of the top electrode 112 are tuned to meet specific device attributes such as series resistance, programming voltage and current.

The dielectric spacer 114 is disposed adjacent and on sidewails of the RRAM device 100 and on the first dielectric layer 102, The dielectric spacer 1 14 extends from the uppermost surface of the first dielectric layer 102 to an upper most surface of the top electrode 112 and may be any suitable dielectric layer such as but not limited to carbon doped silicon nitride or silicon nitride. In an embodiment, the dielectric layer of the dielectric spacer 114 is a non-oxygen- containing layer. In an embodiment, the dielectric spacer 1 14 has a thickness in the range of 10- 50nm.

The second dielectric layer 116 is disposed on the first dielectric layer 102 and laterally adjacent to the dielectric spacer 1 14. Suitable layers for the second dielectric layer 16 include but are not limited to silicon dioxide, carbon doped silicon oxide, silicon nitride, carbon doped silicon nitride. An uppermost surface of the second dielectric layer 1 16 is coplanar or substantially coplanar with an uppermost surface of the dielectric spacer 1 14 and the uppermost surface of the top electrode 12,

The third dielectric layer 118 is disposed on the second dielectric layer 1 16, the top electrode 1 12 and on the dielectric spacer 1 14. In an embodiment, suitable layers for the third dielectric layer 1 18 include layers such as but not limited to silicon dioxide, carbon doped silicon oxide, silicon nitride, carbon doped silicon nitride.

In an embodiment, the array interconnect 1 01 includes a diffusion barrier layer 120, such as but not limited to tantalum nitride, tantalum, ruthenium or cobalt. The array interconnect 101 also includes a conductive fill layer 122. In an embodiment the diffusion barrier layer 120 has a thickness approximately in the range of 2nm-15nm. The conductive fill layer 122 includes a material such as but not limited to tantalum, ruthenium or copper. In an embodiment, the conductive fill layer 122 is a copper layer having a thickness approximately in the range of 2-2.5 times the depth of the trench 1 19.

Figure IB illustrates a cross-sectional view of the array interconnect formed on the RRAM cell along the A-A' axis illustrated in Figure 1 A. In an embodiment, the bottom electrode 106 has a width, WBE, approximately equal to a width, Wei, of the conductive interconnect 104. In an embodiment, the array interconnect 101 has a width WAi that is less than the width of the top electrode 112, WTE. In an embodiment, the array interconnect 101 has a width WAi that is greater than the width of the top electrode 1 12, WTE.

Figure 1C illustrates a cross-sectional view of the array interconnect formed on a pair of RRAM cells along B-B' axis illustrated in Figure 1 A. In an embodiment, the uppermost portion of the top electrode 1 12 and the dielectric spacer 1 14 of a pair of RRAM devices 140, are coplanar with each other and with the second dielectric layer 1 16 adjacent to the dielectric spacer 1 14. The diffusion barrier layer 120 is formed over the coplanar surfaces of the top electrode 112 of the pair of RRAM devices 140, over the dielectric spacer 1 14 and over the second dielectric layer 1 16. The conductive fill layer 122 is formed over the diffusion barrier layer 120.

Figure 2 A illustrates a cross-sectional view of an array interconnect 201 formed in a trench 219 and in a via 221 disposed above each RRAM cell 230 in an RRAM array, in accordance with an embodiment of the present invention. Each RRAM cell 230 includes an RRAM device 240 disposed on a conductive interconnect 204 disposed in a first dielectric layer 202 disposed above a substrate 200. In an embodiment, RRAM device 240 includes a bottom electrode 206, a highly stoichiometric metal oxide switching layer 208, a sub-stoichiometric metal oxide layer 210 and a top electrode 212 disposed in an opening in a second dielectric layer 216. In an embodiment, the uppermost portion of the second dielectric layer 216, the bottom electrode 206, the highly stoichiometric metal oxide switching layer 208, the sub-stoichiometric metal oxide layer 210 and the top electrode 212 are coplanar or substantially coplanar with one another.

A dielectric hardmask layer 224 is disposed above a plurality of RRAM devices 240. A third dielectric layer 218 is disposed on the dielectric hardmask layer 224, A trench 219 is disposed in the third dielectric layer 218 directly above a plurality of RRAM devices 240. A plurality of vias 221 is disposed in the trench 219 over a plurality of top electrodes 212 directly beneath the trench 219. A diffusion barrier layer 220 is disposed on the sidewalls of the trench 219, in and along the sidewalls of the plurality of vias 221, on the plurality of top electrodes 212 exposed in the via 221, on the uppermost surface of the dielectric hardmask layer 224 exposed by the trench 219. A conductive fill layer 222 is disposed on the diffusion barrier layer 220 in the trench 219 and in the via 221. The uppermost surfaces of the conductive fill layer 222, the diffusion barrier layer 220 and the third dielectric layer 218 are coplanar or substantially coplanar. In an embodiment, the diffusion barrier layer 220 is disposed completely in the plurality of vias 221.

In an embodiment, the portion of the bottom electrode 206 that is in contact with the uppermost surface of the conductive interconnect 204 has a thickness that is greater than a thickness of portions of the bottom electrode 206 disposed along the sidewalls of the second dielectric layer 216.

In an embodiment, the dielectric hardmask layer 224 includes a material such as but not limited to silicon nitride, carbon doped silicon nitride or any other oxygen-free layer. In an embodiment the dielectric hardmask layer 224 has a thickness approximately in the range of 5nm-50nm. In different embodiments, the dielectric hardmask layer 224 functions as an etch stop, as an insulating layer and as a mask or as combinations thereof, as is discussed below.

In an embodiment, exemplary layer compositions of the conductive fill layer 222, the diffusion barrier layer 220, top electrode 212, the sub-stoichiometric metal oxide layer 210, the highly stoichiometric metal oxide switching layer 208, second dielectric layer 216 and the third dielectric layer 218 may be as described above for conductive fill layer 122, the diffusion barrier layer 120, top electrode 1 12, the sub-stoichiometric metal oxide layer 110, the highly stoichiometric metal oxide switching layer 108, second dielectric layer 1 16 and the third dielectric layer 118, respectively.

Figure 2B illustrates a cross-sectional view of the array interconnect formed on an

RRAM cell along the A-A' axis illustrated in Figure 2A. In an embodiment, the trench 219 has sloped sidewalls with an angle approximately in the range of 45-60 degrees with respect to a vertical axis of the opening. The base of the trench 219 may have a width, WBT, that is equal to or greater than the width, Wy, of the via 221. In an embodiment the via 221 has width, y, that is less than the width, WTE, of the top electrode 212. In one such embodiment, the diffusion barrier layer 220 is limited to spatial contact with a portion of the upper surface of top electrode 212. In an embodiment when the dielectric hardmask layer 224 has a thickness approximately in the range of 5nm-7nm, a similarly sized diffusion barrier layer 220 completely fills the via 221 defined in the dielectric hardmask layer 224. In one such embodiment, the conductive fill layer 222 is above the upper most surfaces of the dielectric hardmask layer 224,

Figure 2C illustrates a cross-sectional view of the array interconnect formed on a pair of RRAM cells along the B-B' axis illustrated in Figure 2A. In an embodiment, each of a pair of RRAM devices 240 has a top electrode 212 that is coplanar with one another and with the second dielectric layer 216 adjacent to the pair of RRAM devices 240. The diffusion barrier layer 220 is formed in a via 221, on the uppermost surface of the top electrode 2 2 and on the upper most surface of the dielectric hardmask layer 224. The conductive fill layer 222 is formed over the diffusion barrier layer 220.

Figures 3 A-3 J illustrate cross-sectional views representing various operations in a method of fabricating a resistive random access memory device integrated on a conductive interconnect, which may be used to fabricate a memon,' device such as described in association with Figure 1 A, in accordance with an embodiment of the present invention.

Figure 3 A illustrates a conductive interconnect 304 surrounded by a first dielectric layer 302 formed above a substrate 300. In an embodiment, one or more dielectric layers are used. Dielectric layer 302 may be formed using dielectric layers known for their applicability in integrated circuit structures, such as low-k dielectric layers. Examples of dielectric layers that may be used include, but are not limited to, silicon dioxide (Si0 ₂ ), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosiiicate glass (FSG), and organosiiicates such as silsesquioxane, siloxane, or organosiiicate glass. The dielectric layer 302 may include pores or air gaps to further reduce their dielectric constant. In an embodiment, the total thickness of dielectric layer 302 may be in the range of 2000A - 3000A. The conductive interconnect 304 may be fabricated using dual damascene processing or sub tractive etching. The dielectric layer 302 has an uppermost surface

substantially co-planar with an uppermost surface of the conductive interconnect 304.

Figure 3B illustrates a material layer stack 320 for a resistive random access memory application formed on the conductive interconnect. The material layer stack includes a bottom electrode metal layer 306, a highly stoichiometric metal oxide switching layer 308, a sub- stoichiometric metal oxide layer 310 and a top electrode metal layer 312 formed on the uppermost surface of the conductive interconnect 304 and the uppermost surface of the first dielectric layer 302,

In an embodiment, the bottom electrode metal layer 306 is a layer having a composition and a thickness such as described above in association with the bottom electrode 106. In an embodiment, the bottom electrode metal layer 306 is formed using a PVD or an ALD process process.

In an embodiment the bottom electrode metal layer 306 includes a layer deposited by a physical vapor deposition (PVD) process. In one embodiment, the bottom electrode metal layer 306 is deposited by PVD and is composed of a layer such as, but not limited to, TiN, Ta , W or Ru, In an embodiment, the bottom electrode metal layer 306 is deposited by PVD to a thickness approximately in the range of 30 nm to lOOnm. The process of depositing the bottom electrode metal layer 306 using PVD may include an in-situ sputter cleans to first remove any oxide residue from the uppermost surface of the conductive interconnect 304, For example, a gas containing Ar may be used to energetically bombard the surface of the bottom electrode metal layer 306 to remove any native oxide. In an embodiment, the bottom electrode metal layer 306 is formed by a PVD process and is subsequently polished to achieve a surface roughness of I nm or less. Reducing surface roughness using a polishing process may offer advantages during cycling of an RRAM device as it may serve to reduce abrupt filament nucleation and hence lessen variation in cycling voltage in a large device array.

In another embodiment, the bottom electrode metal layer 306 is deposited using an atomic layer deposition (ALD) process. The ALD process may offers advantages such as greater film thickness uniformity (~1 %) compared to a PVD process (~5%), but may have a slower deposition rate, e.g., a deposition rate of 0.5 nm - 2nm/min. In one embodiment, a planarization process is not needed subsequent to depositing using an ALD process. Reducing surface roughness using an ALD process may offer advantages during cycling of an RRAM device as it serves to reduce abrupt filament nucleation and hence lessen variation in cycling voltage in a large device array. In an embodiment, the bottom electrode metal layer 306 is deposited by ALD and is composed of a layer such as, but not limited to, Ti N, TaN, W and Ru.

Referring again to Figure 3B, the highly stoichiometric metal oxide switching layer 308 is formed on the bottom electrode metal layer 306. In an embodiment, the highly stoichiometric metal oxide switching layer 308 is a layer having a composition and a thickness such as described above in association with the highly stoichiometric metal oxide switching layer 108. In an embodiment, the highly stoichiometric metal oxide switching layer 308 is formed using an ALD process. The ALD process may be characterized by a slow and a highly controlled metal oxide deposition rate. The ALD process may also be highly uniform (e.g., approximately 0.1 nm level variation). In an embodiment, a pre-clean of the surface of the bottom electrode metal layer 306 is performed immediately prior to deposition of the highly stoichiometric metal oxide switching laver 308. In an embodiment, the bottom electrode metal laver 306 and the highly stoichiometric metal oxide switching layer 308 are deposited sequentially in a same chamber or in a same tool without breaking vacuum. In such a case, it may not be necessary to perform an in-situ pre-clean immediately prior to deposition of the highly stoichiometric metal oxide switching laver 308.

Referring again to Figure 3B, the sub -stoichiometric metal oxide layer 310 is formed on the highly stoichiometric metal oxide switching layer 308. In an embodiment, the sub- stoichiometric metal oxide layer 310 is a layer having a composition and a thickness such as described above in association with the sub-stoichiometric metal oxide layer 1 0. In an embodiment, the sub-stoichiometric metal oxide layer 310 is formed using a PVD process. The PVD process may offer an advantage of a controllable oxygen flow rate resulting in a sub- stoichiometric metal oxide layer 310 that is oxygen deficient. In an embodiment, the oxygen flow rate is varied during the deposition process leading, to an oxygen concentration gradient within the resulting sub-stoichiometric metal oxide layer 310. In one embodiment, the concentration gradient has a higher concentration of oxygen proximate to the highly

stoichiometric metal oxide switching layer 308 and a lower concentration of oxygen distal from the highly stoichiometric metal oxide switching layer 308. Such an arrangement may preferably provide greater oxygen vacancies in a location that aids with filament formation and dissolution. In another embodiment, there is no oxygen concentration gradient.

Referring again to Figure 3B, the top electrode metal layer 312 is formed on the sub- stoichiometric metal oxide layer 310. In an embodiment, the top electrode metal layer 312 is a layer having a composition and a thickness such as described above in association with the top electrode 1 12. In an embodiment, the top electrode metal layer 312 is formed using a PVD process. In an embodiment, the top electrode metal layer 312 and the sub-stoichiometric metal oxide layer 310 are deposited sequentially in a same chamber or in a same tool without breaking vacuum. By doing so, the sub-stoichiometric metal oxide may retain its oxygen vacancies. In an embodiment the top electrode metal layer 3 2 has a same composition as the bottom electrode metal layer 306.

Figure 3C illustrates a resist pattern 319 formed on a dielectric hardmask layer 314 formed on the material layer stack 320. In an embodiment, the dielectric hardmask layer 314 is devoid of oxygen. In one embodiment, the dielectric hardmask layer 314 is a layer such as, but not limited to, silicon nitride, silicon carbide or carbon-doped silicon nitride. In one

embodiment, the dielectric hardmask layer 314 has a thickness approximately in the range of 50- lOOnm. The thickness of the dielectric hardmask layer 314 may be determined by patterning fidelity and subsequent processing tolerances, as will be discussed further below.

In an embodiment, the resist pattern 319 has a shape that ultimately defines a shape of an RRAM device fabricated from the material layer stack 320. In one embodiment, the resist pattern 319 has rectangular shape or a circular shape. In one embodiment, the resist pattern 319 has a shortest width in the range of 20-100nm. Resist pattern 319 may include one or more layers such as an anti-reflective coating (ARC), gap-fill and planarizing layer in addition to or in place of a photoresist layer, in one embodiment, the resist pattern 319 is formed to a thickness sufficient to retain its profile during subsequent patterning of the dielectric hardmask layer 314 but not so thick as to prevent lithographic patterning into the smallest dimensions (e.g., critical dimensions) possible with photolithography processing.

Figure 3D illustrates the structure of Figure 3C following an etch process used to transfer the pattern of resist pattern 319 into the dielectric hardmask layer 314. In an embodiment, an anisotropic plasma etch process is used to pattern dielectric hardmask layer 314 with selectivity to the resist pattern 319. In an embodiment, a selectivity of greater than 3 to 1 between photoresist layer and dielectric hardmask layer 314 is achieved. It is to be appreciated that chemical etchants utilized in the plasma etch process may depend on the dielectric layer being etched, and may include one or more of CH _x F _y , 0 ₂ , Ar, N ₂ and CF ₄ . Sidewall angles of the patterned dielectric hardmask layer 314 may be tailored to vary from 85-90 degrees depending on the type of etch conditions employed.

Figure 3E illustrates the structure of Figure 3D following removal of the resist pattern 319 selectively to the dielectric hardmask layer 314. In an embodiment, the resist pattern 3 9 is removed using an ash process. The ash process may include use of a gas containing 0?., H2/N2, etc. It is to be appreciated that polymeric films, which may result from the interaction between a photoresist layer and etch byproducts during memory device etch, may adhere to the sidewall portions of an etched RRAM layer stack 320, If portions of such polymeric layers have metallic components, device performance may be significantly degraded. As such, in one embodiment, the resist pattern 319 is removed prior to etching the material layer stack 320.

Figure 3F illustrates the structure of Figure 3E following an etch process used to transfer the dielectric hardmask pattern into the material layer stack 320 to form a resistive random access memory device 340.

In an embodiment, different chemistri es are utilized as part of numerous etch operations to etch the material layer stack 320. In an embodiment, a reactive ion etch utilizing a chemistry including Ar, CF ₄ and CI 2 is utilized to pattern a TiN top electrode 312 and a TiN bottom electrode metal layer 306. in an embodiment, a hafnium oxide sub-stoichiometric layer and a hafnium oxide highly stoichiometric layer are etched using an etch chemistry including BCI3, CI2, and Ar. In another embodiment, a Ta ₂ 05 and Ta ₂ 0 ₅ - _x stack is patterned using an etch chemistry including a mixture of CHF _X , Ar, and Cl ₂ . In one embodiment, etching of the material layer stack 320 is performed during a single introduction into an etch tool to etch all layers of the material layer stack 320 in a single pass.

In an embodiment, as is also depicted in Figure 3F, the width of the bottom electrode 306 is larger than the width of the conductive interconnect 304. When the bottom electrode 306 is completely etched the underlying first dielectric layer 302 is exposed. Depending on the etch selectivity to the first dielectric layer 302, there may be a small but noticeable amount of recess 303 in the dielectric layer 302 (indicated by the dotted line in Figure 3F).

Figure 3G illustrates the structure of Figure 3F following the formation of a dielectric spacer layer 315 covering the sidewalls of the RRAM device 340, the top dielectric hardmask layer 314 and the top of the first dielectric layer 302 surrounding the conductive interconnect 304,

In an embodiment, deposition of the dielectric spacer layer 315 is performed immediately post RRAM device etch, prior to breaking vacuum in the same tool or chamber used for the etch process. Such a procedure, known in the art as in-situ deposition, may hermetically seal the device and potentially decrease oxidation of sensitive sub-stoichiometric metal oxide layers. In an embodiment, the dielectric spacer layer 315 is a layer such as, but not limited to, silicon nitride, silicon carbide, carbon-doped silicon nitride, or any suitable non-oxygen containing layer. In an embodiment, the dielectric spacer layer 315 has a thickness approximately in the range of 20-50nm. In another embodiment, the RRAM device and the dielectric hardmask layer 314 have angled sidewalls between 80-90 degrees, and the dielectric spacer layer 315 is deposited to a thickness greater than 50nm.

Figure 3H illustrates the structure of Figure 3G following an anisotropic plasma etch of the dielectric spacer layer 315 to form a dielectric spacer 316. In an embodiment, a silicon nitride dielectric spacer layer 315 is etched using reactive ion etching utilizing a chemistry including Ar, ()?., and a fluorocarbon such as but not limited to CHF ₃ , CH ₂ F ₂ , or C ₄ F ₈ .

Figure 31 illustrates the structure of Figure 3H following formation of a second dielectric layer 318 covering the RRAM device 340, the dielectric hardmask layer 314, the dielectric spacer 316 and the first dielectric layer 302 surrounding the conductive interconnect 304.

Suitable layers for the second dielectric layer 318 may be the same as those described in association with the first dielectric layer 302. In an embodiment, a total thickness of the second dielectric layer 318 is approximately 2 to 2.5 times the combined height of the RRAM device 340 and the dielectric hardmask layer 314,

Figure 3 J illustrates the structure of Figure 31 following planarization of the second dielectric layer 318, the dielectric spacer 316, the dielectric hardmask layer 314, and an upper portion of the top electrode 312. In an embodiment, a chemical mechanical polishing (CMP) process is used for the pianarizing. To avoid localized dishing between RRAM devices the CMP process may include multiple processes. In one embodiment a first processing operation includes use of a first slurry to planarize the second dielectric layer 318, the dielectric hardmask layer 314 and a portion of the dielectric spacer 316. A second, different slurry is used to polish a portion of the top electrode 312, The resulting structure may include uppermost portions of the second dielectric layer 318, the dielectric spacer 316 and the top electrode 312 that are co-planar with one another.

Figure 3 illustrates an angled view of an array of RRAM cells of the type illustrated in Figure 3 J, in accordance with an embodiment of the present invention. In an embodiment, each RRAM device 340 has a circular shape from a plan view perspective, as is shown. In other embodiments, the shape of each RRAM device 340 from the plan view perspective is a shape such as, but not limited to, a square, a rectangle, or an oval.

Figures 4A-4D illustrate a variety of cross-sectional views representing various operations in a method of fabricating an array interconnect 101 on an array of RRAM cells 130 of the type described in association with Figure 1 A, in accordance with an embodiment of the present invention.

Figure 4 A illustrates various cross-sectional views of the structure of Figure 3K following the formation of a third dielectric layer 420 on an RRAM cell array and on the second dielectric layer 318 followed by formation of a resist pattern 426 to define a trench location. Cross-sections along two orthogonal directions defined by the A- A' axis and the B-B' axis are also depicted in Figure 4A. As illustrated in Figure 4A (Α-Α'), the location of the trench mask is shown relative to an RRAM device 340, while Figure 4A (Β-Β') depicts a pair of RRAM devices 340 that will ultimately be connected by an array interconnect. In an embodiment, the thickness of the third dielectric layer 420 can range from 100-200nm. In an embodiment after completion of a subsequent planarization process the third dielectric layer 420 has a height approximately in the range of 80-150nm. Typical materials for the third dielectric layer 420 may be as described above for the third dielectric layer 118 in association with Figure 1 A.

Figure 4B illustrates various cross-sectional and plan views of the structure of Figure 4A following an etch process to form a trench 421 followed by resist 426 removal. Trench 421 exposes an uppermost portion of the top electrode 312 and the dielectric spacer 316 of each of the plurality of RRAM cells in a given array as is depicted in the angled cross-sectional view of Figure 413. In an embodiment, the number of RRAM cells along the trench opening is approximately in the range from 10 ² - 10 ³ . The trench 421 has a width, WTB, at the bottom as is il lustrated in Figure 4B (Α-Α'). WTB may be larger, smaller or equal to the width of the top electrode 312, WTE. Depending on the width of the trench, a portion of the dielectric spacer 316 is partially covered by the second dielectric layer 318 or is fully exposed. In an embodiment, the etch process creates a recessed portion 311 of the dielectric spacer 316 and the second dielectric layer 3 8 as is illustrated by dashed lines in Figure 4B (Β-Β'). In an embodiment, recess 3 1 does not expose sidewali portions of the sub-stoichiometric metal oxide layer 310. In an embodiment, a reactive-ion etch utilizing a chemistry including Ar, 0 ₂ , and a fluorocarbon such as but not limited to CHF ₃ , CH ₂ F ₂ , or C ₄ F ₈ does not recess the top electrode by more than approximately 2nm.

Figure 4C illustrates the structure of Figure 4B following the formation of a diffusion barrier layer 422 in the trench 421, on the uppermost portion of each REAM device 340 and the formation of a conductive fill layer 424 on the diffusion barrier layer 422 in the trench 421 .

The diffusion barrier layer 422 is formed on the sloped sidewalls of the trench 421 , on the uppermost surface of the top electrode 312, on the uppermost surface of the dielectric spacer 316, on the second dielectric layer 318 and on the uppermost surface of the third dielectric layer 420 as depicted in Figure 4C (Α-Α') and Figure 4C (Β-Β'). In an embodiment, the diffusion barrier layer 422 includes a material such as but not limited to tantalum nitride, tantalum, ruthenium or cobalt. In an embodiment, the diffusion barrier layer 422 is deposited in a PVD tool and has a thickness in the range of 5-15nm. In an embodiment, a combination of non- conformal deposition technique and reflow of the diffusion barrier layer 422 after a high temperature anneal leads to the diffusion barrier layer 422 having a thicker amount on the base compared to on the sloped sidewalls of the trench 421. In an embodiment, the ratio of diffusion barrier layer thickness between the sidewali portion and the base portion of the trench 421 is approximately in the range of 2-3.

In an embodiment, the conductive fill layer 424 includes a material such as but not limited to tantalum, ruthenium or copper. In an embodiment, the conductive fill layer 424 is copper and is filled using an electroplating process. In one such embodiment, the copper layer has a thickness approximately in the range of 2-2.5 times the depth of the trench 421.

Figure 4D illustrates the structure of Figure 4C following planarization of the conductive fill layer 424, diffusion barrier layer 422 and the third dielectric layer 420 to form an array interconnect 427 including a planarized conductive fill layer 425 and a planarized diffusion barrier layer 423. In an embodiment, a chemical mechanical polishing (CMP) process is used for the planarizing. To avoid localized dishing between RRAM devices the CMP process may include multiple processes. The resulting structure may include uppermost portions of the diffusion barrier layer 423, the conductive fill layer 425 and the third dielectric layer 420, that are co-planar or substantially co-planar with one another. The height of the array interconnect 427 can be tuned by the polish process to meet specific line resistance values. In an embodiment the array interconnect has a height approximately in the range of 80-150nm. In an embodiment, the resistivity of a single array interconnect 427 is approximately in the range of 60-300 ohms - a value far below a low resistance level for an RRAM device 340, which is approximately in the range of 1000 ohms - 4000 ohms.

Referring again to Figure 4D, the cross sectional views illustrate an array interconnect formed in a trench utilizing a single lithography process to expose the uppermost portions of each RRAM device 340. In one such embodiment, the uppennost portion of each RRAM device 340 is the top electrode 312. In other embodiments, the uppermost portions of the RRAM device 340 include other conductive components that need to be isolated while the top electrode 312 is solely contacted by the diffusion barrier layer 423, Methods to fabricate such conductive interconnects for more complicated RRAM geometries are described below.

Figures 5A-5J illustrate cross-sectional views representing various operations in a method of fabricating a resistive random access memory device integrated on a conductive interconnect, which may be used to fabricate a memory device such as described in association with Figure 2 A, in accordance with an embodiment of the present invention.

Figure 5 A illustrates a conductive interconnect 504 formed in a first dielectric layer 502 above a substrate 500. Conductive interconnect 504 may be fabricated in a manner similar to the conductive interconnect 204 described in association with Figure 3 A.

Figure 5B illustrates the structure of Figure 5 A following formation of a second dielectric layer 514 on an uppermost surface of the conductive interconnect 504 and on an uppermost surface of the first dielectric layer 502. The second dielectric layer 514 may be composed of materials such as but not limited to silicon oxide, silicon nitride, carbon doped silicon nitride and silicon carbide. In an embodiment, a silicon dioxide based second dielectric layer 514 is implemented in conjunction with a tungsten bottom electrode. In an embodiment, the second dielectric layer 514 has a thickness ranging from 70nm- 150nm. The thickness of the second dielectric layer 514 may be selected based on the shape and size of the RRAM device 340 to be fabricated. The thickness may be selected to account for an amount to be sacrificed during a CMP operation used at the end of an RRAM device 340 fabrication process.

Figure 5C illustrates the structure of Figure 5B following patterning of a photoresist layer to form a mask 516 to define a via location. In an embodiment, the via location is selected to ultimately expose at least a portion of the conductive interconnect 504.

Figure 5D illustrates the structure of Figure 5C following an etch process to create a via 517 in the second dielectric layer 514. In an embodiment, the width of the top of the via 517 is wider than the bottom of the via 517. In one such embodiment the via 517 has sloped sidewalls, In an embodiment, the sloped sidewalls have an angle between 5-60 degrees with respect to a vertical axis of the via 517. In an embodiment, the width of the bottom of the via 517 is approximately the same size as the width of the conductive interconnect 504. In one

embodiment, a central vertical axis of the via 517 is centered with a center of the conductive interconnect 504. In another embodiment, the central vertical axis of the via 517 is off-set with the center of the conductive interconnect 504,

Figure 5E illustrates the structure of Figure 5D following removal of the mask 5 6. In an embodiment, the mask 516 is removed using a resist strip and cleans process. In one

embodiment, the conductive interconnect 504 is exposed to a plasma during the mask 5 6 removal. In one such embodiment, the conductive interconnect 504 is subjected to a sputter clean treatment prior to deposition of a next RRAM material layer stack.

Figure 5F illustrates the structure of Figure 5E following formation of a bottom electrode metal layer 506 in the via 517 and on the conductive interconnect 504. In an embodiment, the bottom electrode metal layer 506 is formed at the bottom of the via 517 on the conductive interconnect 504, along the sidewalls of the via 517, and on the uppermost surface of the second dielectric layer 514. Exemplary layer compositions and deposition techniques for forming the bottom electrode metal layer 506 may be as described above for the bottom electrode metal layer 306. In an embodiment, an interface 519 (depicted by a dashed line in Figure 5F), is formed when the second dielectric layer 514 is a silicon oxide. In an embodiment, a combination of the metal from the bottom electrode metal layer and oxygen from the dielectric constitutes a portion of the interface. It is to be appreciated such interface may not be present between the upper most portion of the conductive interconnect 504 and the flat portion of the bottom electrode 506 disposed inside the via 517.

Figure 5G illustrates the structure of Figure 5 F following formation of a highly stoichiometric metal oxide switching layer 508 in the via 517 and on the bottom electrode metal layer 506, In an embodiment, the highly stoichiometric metal oxide switching layer 508 is formed at the bottom of the via 517 on the bottom electrode metal layer 506, along the sidewalls of the via 517, and above the upperm ost surface of the second dielectric layer 514. Exemplary layer compositions and deposition techniques for forming the highly stoichiometric metal oxide switching layer 508 may be as described above for the highly stoichiometric metal oxide switching layer 308.

Figure 5H illustrates the structure of Figure 5G following formation of a sub- stoichiometric metal oxide layer 510 in the via 517 and on the highly stoichiometric metal oxide switching layer 508. In an embodiment, the sub-stoichiometric metal oxide layer 510 is formed at the bottom of the via 517 on the highly stoichiometric metal oxide switching layer 508, along the sidewalls of the via 517, and above the uppermost surface of the second dielectric layer 514. Exemplar}' layer compositions and deposition techniques for forming the sub-stoichiometric metal oxide layer 510 may be as described above for the sub-stoichiometric metal oxide layer 310,

Figure 51 illustrates the structure of Figure 5H following formation of a top electrode 512 in the via 517 and on the sub-stoichiometric metal oxide layer 510. In an embodiment, the top electrode 512 completely fills the via 517 and extends over the uppermost surface of the second dielectric layer 514. Exemplary layer compositions and deposition techniques for forming the top electrode 512 may be as described above for the top electrode 3 2.

Figure 5 J illustrates the structure of Figure 51 following a planaiization process to form an RRAM device 540. RRAM device 540 includes a top electrode 512, a sub-stoichiometric metal oxide layer 510, a highly stoichiometric metal oxide switching layer 508, and a bottom electrode 506. In an embodiment, the planarization process is a CMP process. In one such embodiment, the CMP process provides the top electrode 512, the sub-stoichiometric metal oxide layer 510, the highly stoichiometric metal oxide switching layer 508, and the bottom electrode 506 with uppermost surfaces coplanar or substantially coplanar with the uppermost surface of the second dielectric layer 514.

Figure 5 illustrates an angled view of an array of RRAM cells of the type illustrated in Figure 5 J, in accordance with an embodiment of the present invention. In an embodiment, each RRAM device 540 has a circular shape from a plan view perspective, as is shown. In other embodiments, the shape of each RRAM device 540 from the plan view perspective is a shape such as, but not limited to, a square, a rectangle, or an oval.

Figures 6A-6F illustrate various cross-sectional views representing various operations in a method of fabricating an array interconnect on an array of RRAM cells 240 of the ty pe described in association with Figure 2A, in accordance with an embodiment of the present invention.

Figure 6 A illustrates various cross-sectional views of the structure of Figure 5K following formation of a dielectric hardmask layer 616 on an RRAM cell 240 array, formation of a third dielectric layer 618 on the dielectric hardmask layer 616 and formation of a pattern on resist 617 to form a trench mask.

The dielectric hardmask layer 616 includes a material such as but not limited to silicon nitride, carbon doped silicon nitride or any other oxygen-free layer. In an embodiment the dielectric hardmask layer 616 has a thickness approximately in the range of 5nm-50nm and formed using a chemical vapor deposition (CVD) or a plasma enhanced chemical vapor deposition (PECVD) process. In an embodiment, the dielectric hardmask layer 616 functions as an etch stop, as an insulating layer and as a mask. In an embodiment, a dielectric hardmask layer 616 thickness of 5nm provides adequate electrical isolation for device operation in the range of 1-2V.

The third dielectric layer 618 includes a material such as but not limited to silicon dioxide, carbon doped silicon oxide or silicon carbide. In an embodiment, the third dielectric layer 618 has a thickness in the range of 70 nm - 200 nm. The thickness of the third dielectric layer 618 may be determined by a variety of factors such as but not limited to the size and shape of the array interconnect, spacing between two adjacent array interconnects and an amount that will be consumed by a planarization process. In an embodiment, the final thickness of the third dielectric layer can be tuned by the planarization process.

The width of the trench mask, WTM, may be less than, equal to or greater than the width of the uppermost portion, WRR, of RRAM device 540. The width may be determined by specific line resistance requirements for an array interconnect. In an embodiment, the line resistance is approximately in the range of 100-300 ohms.

Figure 6B illustrates various cross-sectional views of the structure of Figure 6A following an etch process used to form a trench 619 in the third dielectric layer 618, exposing an uppermost portion of the dielectric hardmask layer 616, followed by a mask removal.

Trench 619 exposes an uppermost portion of the dielectric hardmask layer 616 as depicted in the various cross-sectional illustrations. In an embodiment, a reactive-ion etch utilizing a chemistry including Ar, 0 ₂ , CO and a fluorocarbon such as but not limited to CF£F ₃ , CH2F2, or C ₄ F ₈ , is used to pattern the trench 619 in the third dielectric layer 618 selectively to the underlying dielectric hardmask layer 616. The material choices and thickness of the dielectric hardmask layer 616 may be governed by etch selectivity needed during trench 619 etch. In one such embodiment, a silicon nitride dielectric hardmask that has a thickness approximately in the range of 10-20nm provides a selectivity of greater than 10: 1 while etching a silicon oxide dielectric material, A few nanometers of the silicon nitride may be consumed providing protection to the underlying RRAM devices. In an embodiment, the dielectric hardmask layer 616 near the middle of the trench 619 is recessed as indicated by dashed line 623. Such a recess may be formed if the trench is wider than lOOnm. In an embodiment, not shown, micro trenching in the dielectric hardmask layer 616 can occur near the edges of the trench. In an embodiment, the resist 617 is removed using a resist strip and cleans process.

Figure 6C illustrates various cross-sectional views of the structure of Figure 6B following formation of a pattern in resist 625 to define a via 621.

Resist 625 is disposed in the trench 619 on the sloped sidewalls of the third dielectric layer 618 and uniformly over the uppermost surface of the dielectric hardmask layer 616 and patterned. Patterned resist 625 is also disposed over the uppermost surface of the third dielectric layer 618. Exemplar}' layer compositions and deposition techniques for forming the patterned resist 625 may be as described above for the resist 617. It is to be appreciated that accurate alignment of the center of the via 621 as illustrated in Figure 6C (Α-Α') and Figure 6C (Β-Β') to the center of the top electrode 512 may be needed to ensure proper device operation. In an embodiment, via 621 has a lateral dimension approximately in the range of lOnm - 20nm. In an embodiment, the patterned resist 625 has a circular shape from a plan view perspective. In other embodiments, the shape of each patterned resist 625 from a plan view perspective is a shape such as, but not limited to, a square, a rectangle, or an oval.

Figure 6D illustrates various cross-sectional and plan views of the structure of Figure 6C following an etch process used to transfer the via 621 into the dielectric hardmask layer 616, exposing an uppermost portion of the top electrode 512, followed by a mask removal operation. More specifically, in an embodiment, the via etch process exposes only a portion of the uppermost portion of the top electrode 512 as indicated in Figure 6D (Α-Α') and Figure 6D (B- B'). In one such embodiment, an annular portion of the top electrode 512 is covered by the dielectric hardmask layer 616 as illustrated in the plan view of Figure 6D. The annular portion extends radially from the edge of the via 621 to the dashed line 513. In an embodiment, a reactive-ion etch utilizing a chemistry including Ar, 0 ₂ , and a fluorocarbon such as but not limited to CHF3, CH ₂ F ₂ , or CF ₄ , is used to pattern the via 621 in the dielectric hardmask layer 616. In an embodiment, the via 621 has a sloped sidewalk In an embodiment, via 621 is formed by a wet chemical method. In one such embodiment, the profile of the via 621 is a rounded profile.

Figure 6E illustrates various cross-sectional views of the structure of Figure 6D following the formation of a diffusion barrier layer 620 in the trench 619, in the via 621 , on the top electrode 512 of each REAM device 540 and the formation of a conductive fill layer 622 on the diffusion barrier layer 622 in the trench 619.

In an embodiment, the diffusion barrier layer 620 is formed on the uppermost surface of the third dielectric layer 618 and on the sloped sidewalls of the trench 619. Furthermore, diffusion barrier layer 620 is also formed on the uppermost surface of the dielectric hardmask layer 616, on the sidewall of the via 621 and on the uppermost surface of the top electrode 512 as illustrated in Figure 6E (Β-Β'). In an embodiment, the diffusion barrier layer 620 includes a material such as but not limited to tantalum nitride, tantalum, ruthenium, or cobalt. In an embodiment, the diffusion barrier layer 620 is deposited in a PVD tool and has a thickness in the range of 5-15nm. In an embodiment, a non-conformal deposition technique leads to the diffusion barrier layer 620 having a greater material thickness on the base compared to on the sloped sidewalls of the trench 619. In an embodiment, the diffusion barrier layer 620 has a thickness on the base portion of the trench 619 that is approximately 2-3 times greater than the thickness of the diffusion barrier layer 620 on the sidewalls of the trench 619.

In an embodiment, the conductive fill layer 622 includes a material such as but not limited to tantalum, ruthenium or copper. In an embodiment, the conductive fill layer 622 is copper and is filled using an electroplating process. In one such embodiment the copper layer has a thickness approximately in the range of 2-2,5 times the depth of the trench 619.

Figure 6F illustrates various cross-sectional views of the structure of Figure 6E following pianarization of the conductive fill layer 622, diffusion barrier layer 620 and the third dielectric layer 618. In an embodiment, a chemical mechanical polishing (CMP) process is used for the planarizing. To avoid localized dishing between RAM devices the CMP process may include multiple processes. The resulting structure may include uppermost portions of the planarized diffusion barrier layer 624, the planarized conductive fill layer 626 and the planarized third dielectric layer 618, that are co-planar or substantially co-planar with one another. The height of the array interconnect 627 may be tuned by the polish process to meet specific line resistance values. In an embodiment the array interconnect has a height approximately in the range of 80- 150nm. In an embodiment, the resistivity of a single array interconnect 627 is approximately in the range of 60-300 ohms - a value far below a low resistance level for an RRAM device, which is approximately in the range of 1000 ohms - 4000 ohms.

Figure 7 illustrates cross-sectional views of an array interconnect 627 where the diffusion barrier layer 624 has a thickness that is approximately equal to the thickness of the dielectric hardmask layer 616. In one such embodiment the entire via 621 is filled with the diffusion barrier layer 624 and the conductive fill layer 626 occupies the volume defined by trench 619. In another embodiment, the diffusion barrier layer 624 has a material thickness greater than the material thickness of the dielectric hardmask layer 616 and occupies a portion of the trench 619 directly above the via 621 .

Figure 8 illustrates cross sectional views of an array interconnect 627, where an array of RRAM devices 340 represented by the structure of Figure 3 J is connected by an array interconnect 627 of the type represented in Figure 6F, in accordance with an embodiment of the present invention. In one such embodiment, the RRAM device 340 includes a material layer stack such as the material layer stack 320 described in connection with Figure 3B. In an embodiment, the array interconnect 627 illustrated in Figure 8 connects to REAM devices 340 where the uppermost surface includes only a top electrode 312, in contrast to the RRAM device 540 in Figure 6F, where the uppermost surfaces include the top electrode 512, the sub- stoichiometric metal oxide layer 510, the highly stoichiometric metal oxide switching layer 508 and the bottom electrode 506. In one such embodiment, the dielectric spacer 316 and the second dielectric layer 318 of RRAM device 340 are protected by the dielectric hardmask layer 616 during formation of the trench 619. In one such embodiment, thin layers (e.g., 10-20

nanometers) of high work function (e.g., above 5 eV, such as but not limited to platinum, palladium, iridium or tungsten) metals can be used as the material for top electrode 312 for RRAM device 340, in spite of the etch challenges in patterning such high work function metals. In the absence of such a dielectric hardmask layer 616, the dielectric spacer 3 16 and the second dielectric layer 3 18 may be eroded during formation of trench 619 as described in association with Figure 4B (Β-Β').

In an embodiment, after completion of an RRAM device fabrication process, RRAM devices 140 and 240 such as described in association with Figures 1A and 2A, are connected to form a two-terminal device as is described in greater detail below in association with Figure 12. In an embodiment, RRAM devices are subjected to a high temperature anneal process at the end of the fabrication process. In an embodiment, anneal temperatures reach approximately 400°C and last for a time period of approximately 60 minutes. In an embodiment, annealing is a thermal phenomenon that serves to drive the O ^2" from the fully stoichiometric metal oxide thus creating oxygen vacancies, V ₀ in the layer. The O ^2" from the fully stoichiometric metal oxide layer diffuses to the sul> stoichiometric layer above. The effect serves to increase the V ₀ density in a once highly stoichiometric metal oxide switching layer priming it for a conductive filament creation.

Figures 9 illustrates an I-V plot, demonstrating concepts involved with filament formation and voltage cycling (reading and writing) in an RRAM device 140, in accordance with embodiments of the present invention. The initial operation of an RRAM device begins by gradually applying a voltage that is increasing in magnitude (from point A to B), between the top electrode 1 12 and the bottom electrode 106. In an "intentional" one-time breakdown process, known as forming, oxygen vacancies are pumped in from a sub -stoichiometric metal oxide layer 110 leading to a formation of a conductive V ₀ filament in the sub stoichiometric metal oxide layer 1 10 and the highly stoichiometric metal oxide switching layer 108 (point B). With a conductive filament bridging the two electrodes (1 12 and 106), the RRAM device 140 is said to be almost immediately conductive and thus, in a low resistance state (point C). By sweeping the voltage between the top electrode 112 and bottom electrode 106 in a reversed direction (point C to D, through the 0V point E and then to F), causing a reversal of the electri c fi eld direction, the oxygen vacancies (technically positively charged ions) are now directed towards the sub- stoichiometric metal oxide layer 1 10 leading to a dissolution of a tip of the filament in the highly stoichiometric metal oxide switching layer 108, Filament dissolution takes place at some critical voltage (point F), termed Vaeset, an the device returns to a high resistance state (point G). It is to be appreciated that the high resistance level, of point G, is different and lower in magnitude compared to the resistance level of the device before the onset of the forming process. By once again "sweeping" the voltage in the opposite direction, traversing from point G to H and then to point I in the I-V plot, the momentarily dissolved filament begins to manifests again due to the action of vacancy migration. At some critical voltage, V _se t, the filament completely bridges the two electrodes (112 and 106) and the RRAM device 140 is once again said to be in a conductive mode or a low resistance state, point J. The cycling of the RRAM device 140 in this manner, where the resistance levels remain unchanged about the 0 voltage point, leads to the effect of non-volatile memory. In other words, even with the voltage turned off, the resistance level of the RRAM device is maintained, in an embodiment, when a device undergoes a read operation where a voltage VRead, less than the switching voltage (V _se t or VReset) is applied, the device exhibits a numerical resistance value approximately similar in value before the voltage is turned off. It is to be appreciated that the values V _se t and VReset, generally refer to a portion of a voltage that is applied to a transistor in series with the RRAM device 140. The RRAM device 140 coupled with a transistor in this manner is given the term embedded memory.

Figure 10 illustrates a RRAM device 1004, formed on a conductive interconnect 1002 disposed in a via and integrated with a logic transistor 1030 disposed above a substrate 1005. RRAM device 1004 includes a bottom electrode 1006, a fully stoichiometric metal oxide layer 1008, a sub-stoichiometric metal oxide layer 1010 and a top electrode 1012. In one such embodiment, the RRAM device 1004 is a device such as described in association with Figure 1 A. In one such embodiment, the RRAM device is disposed directly on a conductive interconnect coupled to a contact structure 1016 connected to the drain 1020 of the transistor. In other embodiments, the RRAM device 1004 is a device such as described in association with Figure IB or 1C.

In an embodiment, the underlying semiconductor substrate 1005 represents a general workpiece object used to manufacture integrated circuits. The semiconductor substrate often includes a wafer or other piece of silicon or another semiconductor layer. Suitable

semiconductor substrates include, but are not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other

semiconductor layers. The substrate may also include semiconductor layers, metals, dielectrics, dopants, and other layers commonly found in semiconductor substrates.

In an embodiment, transi stors associated with substrate 1005 are metal-oxide- semiconductor field-effect transistors (MOSFET or simply MOS transistors), fabricated on the substrate 1005, In various implementations of the invention, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.

In an embodiment, each MOS transistor 1030 of substrate 1005 includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (Si0 ₂ ) and/or a high-k dielectric layer. The high-k dielectric layer may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k layers that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k layer is used,

The gate electrode layer of each MOS transistorl030 of substrate 1005 is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a conductive fill layer.

For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.

In some implementations, the gate electrode may consist of a "ΙΓ-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the invention, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

In some implementations of the invention, a pair of sidewall spacers 1040 may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers 1040 may be formed from a layer such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers 1040 are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

As is well known in the art, source 1050 and drain 1020 regions are formed within the substrate 1005 adjacent to the gate stack of each MOS transistor 1030, The source and drain regions are generally formed using either an implantation/diffusion process or an

etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with layer that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor layers such as germanium or a group III-V layer or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may ^¬ be used to form the source and drain regions.

To provide further context, integrating memory directly onto a microprocessor chip would be advantageous since it enables higher operation speeds compared to having physically separate logic and memory chips. Unfortunately, traditional charge-based memory technologies such as DRAM and NAND Flash are now facing severe scalability issues related to increasingly precise charge placement and sensing requirements. As such, embedding charge-based memory directly onto a high performance logic chip is not very attractive for future technology nodes. However, a memory technology that does have the potential to scale to much smaller geometries compared to traditional charge-based memories is resistive random access memory (RRAM), since it relies on resistivity rather than charge as the information storage. However, in order to exploit the potential benefits of a high performance logic chip with embedded RRAM memory, an appropriate integrated logic plus RRAM structure and fabrication method is needed.

Embodiments of the present invention include such structures and fabrication processes.

Relating to one or more embodiments described herein, it is to be appreciated that traditional DRAM: memory is facing severe scaling issues and, so, other types of memory devices are being actively explored in the electronics industry. One future contender is RRAM devices. Embodiments described herein include a fabrication method for embedding RRAM bit ceil arrays into a logic process technology. Embodiments described may be advantageous for processing schemes involving the fabrication of logic processors with embedded memory arrays.

In an aspect, an RRAM element may be included in an integrated circuit in regions typically referred to as back end or back end of line (BEOL) layers of the integrated circuit. As examples, Figures 11 A-l IE illustrate schematic views of several options for positioning an RRAM element in an integrated circuit above a drain contact 1 110, in accordance with embodiments of the present invention.

Referring to all Figures 1 1 A-l IE, in each case, a memory region 1100 and a logic region

1102 of an integrated circuit are depicted schematically. Each memory region 1100 includes a select transistor 1104 and overlying alternating metal lines and vias. Each logic region includes a plurality of transistors 1 106 and overlying alternating metal lines and vias which can be used to connect the plurality of transistors 1106 into functional circuits, as is well known in the art.

Referring to Figure 1 1 A, an RRAM device 1 120 is disposed between a lower conductive via 1122 and an upper conductive line 1124. In one embodiment, the lower conductive via 1122 is in electrical contact with a bottom electrode of the RRAM device 1 120, and the upper conductive line 1124 is in electrical contact with an upper electrode of the R A : device 1 120, In a specific embodiment, the lower conductive via 1122 is in direct contact with a bottom electrode of the RRAM device 1120, and the upper conductive line 1124 is in direct contact with an upper electrode of the RRAM device 1120.

Referring to Figure I IB, an RRAM device 1130 is disposed between a lower conductive line 1132 and an upper conductive via 1134. In one embodiment, the lower conductive line 1132 is in electrical contact with a bottom electrode of the RRAM: device 1 130, and the upper conductive via 1134 is in electrical contact with an upper electrode of the RRAM device 1130. In a specific embodiment, the lower conductive line 1132 is in direct contact with a bottom electrode of the RRAM device 1 130, and the upper conductive via 1134 is in direct contact with an upper electrode of the RRAM device 1 130.

Referring to Figure 1 1 C, an RRAM device 1140 is disposed between a lower conductive line 1 142 and an upper conductive line 1144 without an intervening conductive via. In one embodiment, the lower conductive line 1 142 is in electrical contact with a bottom electrode of the REAM device 1140, and the upper conductive line 1144 is in electrical contact with an upper electrode of the RRAM device 140. In a specific embodiment, the lower conductive line 1 142 is in direct contact with a bottom electrode of the RRAM device 1 140, and the upper conductive line 1 144 is in direct contact with an upper electrode of the RRAM device 140.

Referring to Figure 1 ID, an RRAM device 1150 is disposed between a lower conductive via 1152 and an upper conductive via 1154 without an intervening conductive line. In one embodiment, the lower conductive via 1152 is in electrical contact with a bottom electrode of the RRAM device 1150, and the upper conductive via 1 154 is in electrical contact with an upper electrode of the RRAM device 1 150. In a specific embodiment, the lower conductive via 1 152 is in direct contact with a bottom electrode of the RRAM device 1150, and the upper conductive via 1154 is in direct contact with an upper electrode of the A : device 1 50.

Referring to Figure 1 IE, an RRAM device 1 160 is disposed between a lower conductive line 1 162 and an upper conductive via 1 164 in place of an intervening conductive line and conductive via pairing. In one embodiment, the lower conductive line 1 162 is in electrical contact with a bottom electrode of the RRAM device 1 160, and the upper conductive via 1 164 is in electrical contact with an upper electrode of the RRAM: device 1 160. In a specific

embodiment, the lower conductive line 1 162 is in direct contact with a bottom electrode of the RRAM device 1160, and the upper conductive via 1 164 is in direct contact with an upper electrode of the RRAM device 1160.

Figure 12 illustrates a schematic of a memory bit cell which includes a metal-conductive oxide-metal RRAM device 1210, in accordance with embodiments of the present invention.

Referring to Figure 12, the RRAM device 1210 may include a bottom electrode 1212 with a highly stoichiometric metal oxide switching layer 1213 adjacent the bottom electrode 1212. A sub-stoichiometric metal oxide layer 1214 is formed on the highly stoichiometric metal oxide switching layer 1213. A top electrode 1216 is adjacent the sub-stoichiometric metal oxide layer 1214. The top electrode 1216 may be electrically connected to a bit line 1232. The bottom electrode 1212 may be coupled with a transistor 1234. The transistor 1234 may be coupled with a wordline 1236 and a source line 1238 in a manner that will be understood to those skilled in the art. The RRAM device 1210 may further include additional read and write circuitry (not shown), a sense amplifier (not shown), a bit line reference (not shown), and the like, as will be

understood by those skilled in the art, for the operation of the RA : device 1210, It is to be appreciated that a plurality of the RRAM devices 1210 may be operably connected to one another to form a memory array, wherein the memory array can be incorporated into a non- volatile memory region of a substrate in common with a logic region. It is to be appreciated that the nomenclature top and bottom refer to relative positioning of the metal electrodes with respect to the metal oxide layers (stoichiometric and sub-stoichiometric). The transistor 1234 may be connected to top electrode 1216 although only connection to bottom electrode 1212 is shown.

Figure 13 illustrates a block diagram of an electronic system 1300, in accordance with an embodiment of the present invention. The electronic system 1300 can correspond to, for example, a portable system, a computer system, a process control system, or any other system that utilizes a processor and an associated memory. The electronic system 1300 may include a microprocessor 1302 (having a processor 1304 and control unit 1306), a memory device 1308, and an input/output device 1310 (it is to be appreciated that the electronic system 1300 may have a plurality of processors, control units, memory device units and/or input/output devices in various embodiments). In one embodiment, the electronic system 1300 has a set of instructions that define operations which are to be performed on data by the processor 1304, as well as, other transactions between the processor 1304, the memory device 1308, and the input/output device 1310. The control unit 1306 coordinates the operations of the processor 1304, the memory device 1308 and the input/output device 1310 by cycling through a set of operations that cause instructions to be retrieved from the memory device 1308 and executed. The memory device 1308 can include a memory element having a conductive oxide and electrode stack as described in the present description. In an embodiment, the memory device 1308 is embedded in the microprocessor 302, as depicted in Figure 13. In an embodiment, the processor 1304, or another component of electronic system 1300, includes an array of RRAM devices.

Figure 14 illustrates a computing device 1400 in accordance with one embodiment of the invention. The computing device 1400 houses a board 1402. The board 1402 may include a number of components, including but not limited to a processor 1404 and at least one

communication chip 1406. The processor 1404 is physically and electrically coupled to the board 1402, In some implementations the at least one communication chip 1406 is also physically and electrically coupled to the board 1402. In further implementations, the communication chi p 1406 is part of the processsor 1404.

Depending on its applications, computing device 1400 may include other components that may or may not be physically and electrically coupled to the board 1402. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an acceierometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). The communication chip 1406 enables wireless communications for the transfer of data to and from the computing device 1400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1406 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUP A+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 1400 may include a plurality of communication chips 1406. For instance, a first communication chip 1406 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1406 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 1404 of the computing device 1400 includes an integrated circuit die packaged within the processor 1404. In some implementations of embodiments of the invention, the integrated circuit die of the processor includes one or more arrays, such as RRAM memory arrays integrated into a logic processor, built in accordance with embodiments of the present invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 1406 also includes an integrated circuit die packaged within the communication chip 1406. In accordance with another implementation of an embodiment of the invention, the integrated circuit die of the communication chip 1406 includes RRAM memory arrays integrated into a logic processor, built in accordance with embodiments of the present invention.

In further implementations, another component housed within the computing device 1400 may contain a stand-alone integrated circuit memory die that includes one or more arrays, such as RRAM memory arrays integrated into a logic processor, built in accordance with

embodiments of the present invention.

In various implementations, the computing device 1400 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 1400 may be any other electronic device that processes data.

Accordingly, one or more embodiments of the present invention relate generally to the fabrication of embedded microelectronic memory. The microelectronic memory may be non- volatile, wherein the memory can retain stored information even when not powered. One or more embodiments of the present invention relate to the fabrication of RRAM memory arrays integrated into a logic processor. Such arrays may be used in an embedded non-volatile memory, either for its non-volatility, or as a replacement for embedded dynamic random access memory (eDRAM). For example, such an array may be used for 1T-1R memory or 2T-1R memory (R = resistor) at competitive cell sizes within a given technology node.

Figure 15 illustrates an interposer 1500 that includes one or more embodiments of the invention. The interposer 500 is an intervening substrate used to bridge a first substrate 1502 to a second substrate 1504. The first substrate 1502 may be, for instance, an integrated circuit die. The second substrate 1504 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 1500 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 1500 may couple an integrated circuit die to a ball grid array (BGA) 1506 that can subsequently be coupled to the second substrate 1504, In some embodiments, the first and second substrates 502/1 504 are attached to opposing sides of the interposer 1500. In other embodiments, the first and second substrates 1502/1504 are attached to the same side of the interposer 1500. And in further embodiments, three or more substrates are interconnected by way of the interposer 1500.

The interposer 1500 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic layer, or a polymer layer such as poiyimide. In further implementations, the interposer may be formed of alternate rigid or flexible layers that may include the same layers described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV layers.

The interposer may include metal interconnects 508 and vias 1 510, including but not limited to through-silicon vias (TSVs) 1512. The interposer 1500 may further include embedded devices 15 4, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio- frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1500. In accordance with

embodiments of the invention, apparatuses or processes disclosed herein may be used in the fabrication of interposer 1500.

Thus, embodiments of the present invention include approaches for an array interconnect for resistive random access memory (RRAM) devices and their methods of fabrication ,

In an embodiment, a resistive random access memory cell includes plurality of conductive interconnects disposed in a first dielectric layer above a substrate. A plurality of RRAM devices is disposed in a second dielectric layer and each of the RRAM devices are coupled to a corresponding one of the plurality of conductive interconnects. A dielectric spacer surrounds each of the plurality of RRAM devices and lies adjacent to the second dielectric layer. The di electric spacer extends from a bottom most surface of the second dielectri c layer to an uppermost surface of the second dielectric layer. An interconnect is disposed in a trench of a third dielectric layer and coupled to the plurality of RRAM devices. The interconnect includes a diffusion barrier lay er disposed at a bottom of and along sidewails of the trench and a conductive fill layer disposed on the diffusion barrier layer. Uppermost surfaces of the conductive fill layer, the diffusion barrier layer and the third dielectric layer are coplanar.

In one embodiment, the diffusion barrier layer is in contact with the uppermost surface of the second dielectri c l ayer, at least a porti on of the uppermost surface of each of the plurality of RRAM devices and a portion of the uppermost surface of the dielectric spacer layer.

In one embodiment, the diffusion barrier layer is in contact with the uppermost surface of the second dielectric layer, an uppermost surface of each of the plurality of RRAM devices and the uppermost surface of the dielectric spacer layer.

In one embodiment, the diffusion barrier layer of the conductive interconnect is disposed in the opening of the dielectric hardmask layer and completely fills the opening.

In one embodiment, the diffusion barrier laver of the conductive interconnect includes a material selected from the group consisting of titanium nitride, tantalum nitride, cobalt and ruthenium and the conductive fill layer is copper.

In one embodiment, the RRAM device includes a material stack with sidewails. The material stack further includes a bottom electrode metal layer disposed above the conductive interconnect, a highly stoichiometric metal oxide switching layer disposed on the bottom electrode metal layer, a sub-stoichiometric metal oxide layer disposed on the highly

stoichiometric metal oxide switching layer and a top electrode metal layer disposed on the sub- stoichiometric metal oxide layer.

In an embodiment, a resistive random access memory array interconnect includes a plurality of conductive interconnects disposed in a first dielectric layer above a substrate. A plurality of RRAM devices is disposed in a second dielectric layer and each of the RRAM devices is coupled to a corresponding one of the plurality of conductive interconnects, A dielectric hardmask layer is disposed on the plurality of RRAM devices and on the second dielectric layer. The dielectric hardmask has a plurality of openings that expose an uppermost portion of each of the plurality of RRAM devices. A third dielectric layer is disposed on the dielectric hardmask layer. A trench is disposed in the third dielectric layer and exposing the dielectric hardmask layer. An array interconnect disposed in a trench of the third dielectric layer and in the plurality of openings in the dielectric hardmask layer. The array interconnect includes a conductive fill layer disposed on a diffusion barrier layer.

In one embodiment, the diffusion barrier layer is in contact with an uppermost portion of a top electrode of each of the plurality of RRAM: devices.

In one embodiment, the diffusion barrier layer of the conductive interconnect includes a material selected from the group consisting of titanium nitride, tantalum nitride, cobalt and ruthenium.

In one embodiment, the the dielectric hardmask layer is a material selected from the group consisting of a silicon nitride, carbon doped silicon nitride and the third dielectric layer includes a material selected from a group consisting of silicon oxide, carbon doped oxide or silicon oxynitride.

In one embodiment, the RRAM includes a material stack wit sidewalls and includes a bottom electrode disposed above the conductive interconnect; a highly stoichiometric metal oxide switching layer disposed on the bottom electrode; a sub-stoichiometric metal oxide layer disposed on the highly stoichiometric metal oxide switching layer; a top electrode disposed on the sub-stoichiometric metal oxide layer.

In one embodiment, the sidewalls of the material stack are surrounded by a dielectric spacer layer, extending from a lowermost portion of the bottom electrode metal layer to an uppermost portion of the top electrode metal layer.

In one embodiment, the RRAM device is disposed in an opening with sidewalls in the second dielectric layer.

In one embodiment, the RRAM device includes a bottom electrode metal layer disposed on the bottom and along the si dewalls of the opening of the second di electric layer. A hi ghly stoichiometric metal oxide switching layer is disposed on the bottom electrode metal layer. A sub-stoichiometric metal oxide layer is disposed on the highly stoichiometric metal oxide switching layer and a top electrode metal layer is disposed on the sub-stoichiometric metal oxide layer. The upper most portion of the second dielectric layer, the bottom electrode metal layer, the highiy-stoichiometric metal oxide switching layer, the sub-stoichiometric metal oxide layer and top electrode metal layer are coplanar. In one embodiment, the third dielectric layer is disposed above the RRAM device has an opening that only partially exposes the top electrode metal layer.

In an embodiment, the method to form an array interconnect includes forming a plurality of conductive interconnects in a first dielectric layer above a substrate. The method further includes forming a plurality of RRAM devices in a second dielectric layer disposed above and coupled with each of the plurality of conductive interconnects. A trench is formed in a third dielectric layer formed above a plurality of RRAM devices and exposing at least a portion of each of the plurality of RRAM devices and the second dielectric layer. A diffusion barrier layer is formed in the trench and disposed on at least a portion of each of the plurality of RRAM devices and on the second dielectric layer. A conductive metal layer is formed on the diffusion barrier layer. The m ethod further includes planarizing to obtain coplanar surfaces of the conductive metal layer, the diffusion barrier layer and the third dielectric layer.

In one embodiment, patterning the trench exposes each of the plurality of RRAM devices,

In one embodiment, the conductive fill layer is formed via electroless plating.

In one embodiment, forming the RRAM device includes forming a material layer stack having sidewalls. The method further includes forming a bottom electrode metal layer on the conductive interconnect, forming a highly-stoichiometric metal oxide switching layer on the bottom electrode metal layer, forming a sub-stoichiometric metal oxide layer on the highly- stoichiometric metal oxide switching layer and forming a top electrode layer on the sub- stoichiometric metal oxide layer layer.

In one embodiment, the dielectric spacer is formed adjacent to the sidewalls of the material layer stack.

In an embodiment, the method of fabricating a resistive random access memory (RRAM) array interconnect includes forming a plurality of conductive interconnects in a first dielectric layer above a substrate. A plurality of RRAM devices is formed in a second dielectric layer disposed above and coupled with each of the plurality of conductive interconnects. The dielectric hardmask layer is formed on the plurality of RRAM devices and on the second dielectric layer, A trench is formed in a third dielectric layer and exposing the dielectric hardmask layer. The method further includes forming a plurality of openings in the dielectric hardm ask layer. The openings expose a portion of each of the plurality of RRAM devices. A diffusion barrier layer is formed in the opening, on a portion of each of the plurality of RRAM^ devices and along sidewalls of the dielectric hardmask layer and along the sidewall of the third dielectric layers. A conductive fill layer is formed on the diffusion barrier layer. The conductive fill layer, diffusion barrier layer and the third dielectric layer are planarized to form a conductive metal layer, diffusion barrier layer and a third dielectric layer having coplanar uppermost surfaces.

In one embodiment, plurality of openings is formed in the dielectric hardmask layer after formation of the trench in the third dielectric layer.

In one embodiment, the conductive fill layer is a copper layer formed by an electroless plating process.

In one embodiment, forming the RRAM device includes forming a material stack having sidewalls. The method further includes forming a bottom electrode metal layer on the conductive interconnect. A highly stoichiometric metal oxide switching layer is formed on the bottom electrode metal layer. A sub-stoichiometric metal oxide layer is formed on the highly stoichiometric metal oxide switching layer. A top electrode metal layer is formed on the sub- stoichiometric metal oxide layer.

In one embodiment forming the RRAM device further includes forming a plurality of conductive interconnects in the first dielectric layer above a substrate, A plurality of conductive interconnects is formed in a first dielectric layer above a substrate. A plurality of RRAM devices is formed in a second dielectric layer disposed above and coupled with each of the plurality of conductive interconnects. A bottom electrode metal layer is formed in the opening of the second dielectric layer, on the conductive interconnect, confomial with the bottom and the sidewalls of the opening. A highly stoichiometric metal oxide switching layer is formed in the opening, on the bottom electrode metal layer. A sub-stoichiometric metal oxide layer is formed in the opening, on the highly stoichiometric metal oxide. A top electrode metal layer is formed in the opening, on the highly stoichiometric metal oxide switching layer. The bottom electrode metal layer, the highly stoichiometric metal oxide switching layer, the sub-stoichiometric metal oxide layer, the top electrode layer and the second dielectric layer are pianarized to form a bottom electrode, a highly stoichiometric metal oxide switching layer, a sub-stoichiometric metal oxide layer, a top electrode and a second dielectric layer having coplanar uppermost surfaces.