ARRAY SUBSTRATE AND DISPLAY PANEL

WIPO Patent Application WO/2019/006817

A1

An array substrate (100) and a display panel. The array substrate (100) comprises: a substrate (110), a gate electrode (120), a gate insulating layer (130), a semiconductor layer (140), a source electrode (150), and a drain electrode (160). The gate electrode (120) is formed on the upper surface of the substrate (110); the gate insulating layer (130) is formed on the upper surfaces of the gate electrode (120) and the substrate (110) to cover the gate electrode (120); the semiconductor layer (140) is formed on the upper surface of the gate insulating layer (130) and is located above the gate electrode (120); the semiconductor layer (140) is formed of silicon germanium oxide; a channel portion (190) is formed on the semiconductor layer (140); the source electrode (150) is formed on the surfaces of the gate insulating layer (130) and the semiconductor layer (140) and is located at one side of the channel portion (190); the drain electrode (160) is formed on the surfaces of the gate insulating layer (130) and the semiconductor layer (140) and is located at the other side of the channel portion (190).

CHO EN-TSUNG (CN)
FAN KUN (CN)

PCT/CN2017/096714

January 10, 2019

August 10, 2017

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HKC CORP LTD (CN)
CHONGQING HKC OPTOELECTRONICS TECH CO LTD (CN)

H01L27/12; G02F1/1368

CN107359203A	2017-11-17
CN106483726A	2017-03-08
CN103824779A	2014-05-28
KR101325573B1	2013-11-05
CN106856169A	2017-06-16
CN101989015A	2011-03-23
US20030136991A1	2003-07-24
CN1462901A	2003-12-24
CN106910748A	2017-06-30

SHENZHEN BAIRUI PATENT & TRADEMARK OFFICE (CN)

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