Title:
ASSOCIATED MEMORY
Document Type and Number:
WIPO Patent Application WO/2007/119540
Kind Code:
A1
Abstract:
An associated memory is provided with features of suppression of power consumption and a device structure to be simplified with a small installing area while maintaining high speed retrieval. The associated memory is comprised of a simplified function operation unit made of an LUT coupled logic circuit of a simplified CAM function (g) in which an invalid output of the CAM function (f) is replaced by don't-care, an auxiliary memory in which a reverse function (f-1) of the CAM function (f) is stored, and a consistency judging means for judging whether an output of an LUT operating means is consistent with an output of the CAM function (f), wherein the LUT operating means outputs an operated value (tentative index value) of the simplified CAM function (g) for input data, the auxiliary memory outputs the reverse function (f-1) of the tentative index value when the tentative index value is input, and the judging means compares the input date with the reverse function (f-1) and outputs an output value of the LUT operating means when the input data and the output value are consistent with each other but, otherwise, outputs an invalid signal.
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Inventors:
SASAO TSUTOMU (JP)
Application Number:
PCT/JP2007/056498
Publication Date:
October 25, 2007
Filing Date:
March 27, 2007
Export Citation:
Assignee:
KYUSHU INST TECHNOLOGY (JP)
SASAO TSUTOMU (JP)
SASAO TSUTOMU (JP)
International Classes:
G06F7/00; G11C15/04
Foreign References:
| JP2004229163A | 2004-08-12 | |||
| JP2002334114A | 2002-11-22 | |||
| JP2000105770A | 2000-04-11 |
Other References:
SASAO T.: "Design Methods for Multiple-Valued Input Address Generators", 36TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL'06), May 2006 (2006-05-01), pages 1, XP010917777
Attorney, Agent or Firm:
ISHIDA, Kazuto (Kitakyushu Science and Research Park Collaboration Center 2-1, Hibikino, Wakamatsu-k, Kitakyushu-shi Fukuoka 35, JP)
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