LEE, Seong-Se (373-1, Guseong-dong Yuseong-gu, Daejeon-city 305-701, KR)
KIM, Jae-Kuk (373-1, Guseong-dong Yuseong-gu, Daejeon-city 305-701, KR)
MOON, Gun-Woo (1-105, Gyosu Apt. KAIST, 383-2,Doryong-dong, Yuseong-gu, Daejeon-city 305-340, KR)
CHO, Ja-Yong (504-302, Sindonga Pamillie Apt.Gwanpyeong-dong, Yuseong-gu, Daejeon-city 305-745, KR)
LEE, Seong-Se (373-1, Guseong-dong Yuseong-gu, Daejeon-city 305-701, KR)
KIM, Jae-Kuk (373-1, Guseong-dong Yuseong-gu, Daejeon-city 305-701, KR)
MOON, Gun-Woo (1-105, Gyosu Apt. KAIST, 383-2,Doryong-dong, Yuseong-gu, Daejeon-city 305-340, KR)
[CLAIMS]
[Claim 11
An asymmetric half bridge converter comprising: an input terminal A including a power unit Vs for supplying a rectified input voltage, a first switch and a second switch Q-i and Q 2 coupled in series to respective terminals of the power unit Vs and switched according to a predetermined duty, a first link capacitor and a second link capacitor C1 and C2 coupled in parallel between the first and second switches Q 1 and Q 2 and the power unit Vs and having a serial connection, and a primary coil Np of a transformer T; and an output terminal B including secondary coils Ns 1 and Ns 2 of the transformer
T, rectifying diodes D1 and D2, an inductor Lo, and a ripple removing capacitor Co, wherein a blocking capacitor CB is connected in series to the primary coil Np of the transformer T.
[Claim 2]
The asymmetric half bridge converter of claim 1 , wherein the voltage Vc 1 charged in the first link capacitor C1 is expressed in Equation 6, and the voltage V 02 charged in the second link capacitor C2 is expressed in Equation
7:
(Equation 6)
V S +C T V CB "° - S
(Equation 7)
^ = - 2 where Vs is a supply voltage, C τ = C B /Ciin k , and V C B is a voltage at the blocking capacitor.
[Claim 3l
The asymmetric half bridge converter of claim 1 , wherein when the first and second switches Qi and Q 2 perform an on/off switching operation according to the duty, the voltage at the blocking capacitor C B is expressed in Equation 8:
(Equation 8)
[Claim 41
The asymmetric half bridge converter of claim 1 , wherein an offset I L M of a limit current applied to the primary coil Np of the transformer T according to the connection of the blocking capacitor C B is expressed in Equation 9: (Equation 9)
^w=Ci -2∑>yr o where D is a duty supplied to a gate terminal of the second switch Q 2 .
[Claim 51
The asymmetric half bridge converter of claim 1 , wherein the voltage Vo output through a secondary coil Ns with respect to the voltage supplied to the primary coil Np of the transformer T is expressed in Equation 10: (Equation 10)
where Np is a winding number of the primary coil of the transformer, Ns is a winding number of the secondary coil of the transformer, Vs is an output voltage of the power unit, D is a duty of the second switch Q 2 , and 1-D is a duty of the first switch Q 1 . |
[DESCRIPTION]
[Invention Title!
ASYMMETRIC HALF BRIDGE CONVERTER
[Technical Field!
The present invention relates to an asymmetric half bridge converter, and in particular, it relates to an asymmetric half bridge converter having an in-rush current applied to a primary coil of a transformer in the initial drive eliminated.
[Background Art!
Various types of converters have been developed so as to acquire an output voltage required by a load from an input voltage, and recently, the switching mode power supply (SMPS) that is a switching mode converter has generally been used.
The SMPS receives a DC voltage as an input voltage and outputs at least one DC voltage that is equal to or greater than the supplied input voltage.
The SMPS is used for electronic devices having a load part that requires various voltages.
Recently, as CPUs, main boards, HDDs, and graphic cards used for PCs have been able to support high performance, power consumption has also been increased and the power supplies have come to support high power performance such as 350W, 400W, and 550W. Therefore, it is very important to develop PC power supplies with high power because of demands for upgrading desktop PCs to high specifications.
The efficiency of a power supply installed in the general PC is substantially 70%, which is very low, so a power supply with high efficiency is needed in consideration of energy usage in the high energy price age.
A PC power supply is a low-price product, and hence a circuit technique for acquiring high efficiency without any price increase is required.
A half bridge converter is generally used since it can have input voltages of 220V and 110V by using a voltage doubler. The half bridge converter has two switches, and the two switches flow a leakage current and a magnetizing inductance current of the transformer through an alternate switching operation to perform a zero voltage switching operation.
An asymmetric half bridge converter is applied in order to acquire further efficiency, and the same has great efficiency through the zero voltage switching by using a lesser number of switches, and hence it is desirable for a power supply of a PC having the characteristic of a low voltage and a great current.
Conventionally, the asymmetric half bridge converter includes an input terminal A and an output terminal B as shown in FIG. 4.
The input terminal A includes a power unit Vs for supplying a rectified input voltage, a first link capacitor and a second link capacitor C1 and C2 for functioning as a voltage doubler, a first switch and a second switch Q 1 and Q 2 that are switched according to a predetermined duty, and a primary coil Np of a transformer T.
The first and second switches Q 1 and Q 2 are connected in series to respective terminals of the power unit Vs, and the first and second link capacitors C1 and C2 coupled in series and applicable to the input voltages of 110V and 220V are connected in parallel between the power unit Vs and the first and second switches Q 1 and Q 2 .
The primary coil Np of the transformer T is connected in series to a node of the first link capacitor C1 and the second link capacitor C2 and a node of the first switch Q 1 and the second switch Q 2 . The output terminal B includes rectifying diodes D1 and D2 connected to output terminals of the secondary coils Ns 1 and Ns 2 of the transformer T, an inductor Lo
connected to anode terminals of the diodes D1 and D2, and a load Ro connected to an output terminal of the inductor Lo.
A ripple removing capacitor Co is coupled in parallel to the load Ro. Therefore, the rectified voltage output by the power unit Vs is charged into the first link capacitor C1 and the second link capacitor C2.
In this instance, when the first switch Qi and the second switch Q 2 generate an on/off switching operation according to a predetermined duty, the voltages charged in the first link capacitor C1 and the second link capacitor C2 are supplied to the primary coil Np of the transformer T. In this process, when the first switch Q 1 and the second switch Q 2 are turned off, the voltage supplied to the primary coil Np of the transformer T is applied to a first coil Nsi or a second coil N S2 of the secondary coil of the transformer T in the output terminal B, the voltage is controlled by a turn ratio of the primary coil Np and the secondary coils N S i and N S2 , the voltage is rectified by the diodes D1 and D2, and the voltage is then supplied to the load Ro through the inductor Lo.
The first switch Q 1 and the second switch Q 2 are alternately operated for the purpose of flowing the leakage current and the magnetizing inductance remaining in the primary coil Np of the transformer T and thereby performing zero voltage switching of the transformer T. Regarding the above-configured conventional asymmetric half bridge converter, when no voltage is supplied to the output terminal B connected to the load Ro, that is, when the first and second switches Q 1 and Q 2 are not switched, the voltages at the respective first and second link capacitors C1 and C2 coupled in parallel to the power unit Vs are half the input voltage, that is, Vs/2. However, a controller for controlling the switching operation by the first and second switches Q 1 and Q 2 so as to transmit the voltage to the load Ro by gradually
increasing the voltage from OV in the initial driving stage performs a soft start operation for increasing the switching duty from 0 to the maximum duty.
An undesired in-rush current is generated in the above-noted process.
For example, when the duty of the second switch Q 2 is increased from 0, the current of the primary coil Np is greatly increased so as to balance the voltages of the primary coil Np and the secondary coils N S1 and N 82 depending on the duty.
That is, during the process of reaching the normal state, the voltage of DVs that is determined by the duty of the second switch Q 2 and the voltage Vs of the power unit will flow to the first link capacitor C1 , and the voltage of (1-D)Vs that is determined by the duty 1-D of the first switch Q 1 and the voltage Vs of the power unit will flow to the second link capacitor C2.
Therefore, the first link capacitor C1 and the second link capacitor C2 are charged with the voltage of Vs/2 that is much different from the normal voltage in the earlier stage, and hence an in-rush current is generated to the primary coil Np of the transformer T in the initial driving.
For example, as shown in FIG. 5, when the current Ij n output from the power unit Vs and input to the first link capacitor C1 and the second link capacitor C2 is approximately 2OA, the in-rush current l pri supplied to the primary coil Np of the transformer T through the first and second link capacitors C1 and C2 is approximately 6OA which is three times the output current of the power unit.
To solve the problem of the in-rush current that is generated in the initial driving, a capacitor with less capacitance is applied to the link capacitor.
When the capacitance of the link capacitor is small even though the voltage difference is large, it is possible to reach the normal-state voltage with a lesser current. As an example for the above-noted case, the application of the first and
second link capacitors C1 and C2 to a 2.2μF Mylar capacitor generates an in-rush
current of 25A to the primary coil Np of the transformer T in the initial driving, as shown in FIG. 6.
Also, the current l in supplied by the power unit Vs generates EMI noise by the in-rush current. In the case of generating a DC voltage from a 60Hz AC line input through a rectifier, the DC voltage may be unstable when the link capacitor has less capacity, and as a result a heavy load may be provided to the DC/DC converter.
Hence, it is inappropriate to apply a link capacitor having less capacitance.
Another method is to reduce the voltage at the first link capacitor C1 to OV and then start a corresponding drive thereof.
To perform this, a dummy resistor R is connected in parallel to the first link capacitor C1.
The voltage at the first link capacitor C1 is reduced from Vs/2 to 0 according to the RC time constant, and the voltage at the second link capacitor C2 is increased from Vs/2 to Vs.
It may be advantageous to reduce the resistance of the dummy resistor R since it is advantageous to discharge the capacitor at the fastest speed. However, since the loss of V 2 C i/R is consecutively generated by the dummy resistor R, it is desirable to increase the resistance of the dummy resistor R in consideration of its efficiency.
According to a test result, when the link capacitors C1 and C2 are set to have
the capacitance of 470μF and the dummy resistor R is set to have the resistance of
47kω, the time in which the voltage at the first link capacitor C1 is reduced to OV takes
more than 20 seconds, which is undesirable. Therefore, the above-noted method is not desirable since the efficiency
reduction caused by the power consumption of the dummy resistor R and the initial driving thereof can be performed in advance to it.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
[Disclosure]
[Technical Problem I
The present invention has been made in an effort to provide a converter having advantages of eliminating an in-rush current applied to the primary coil of a transformer in the initial driving of an asymmetric half bridge converter to provide semiconductor device stability, and having a high-efficiency low voltage and great current characteristic through stable zero voltage switching.
[Technical Solution!
In one aspect of the present invention, a converter includes an input terminal A including a power unit Vs for supplying a rectified input voltage, a first switch and a second switch Q 1 and Q 2 coupled in series to both terminals of the power unit Vs and switched according to a predetermined duty, a first link capacitor and a second link capacitor C1 and C2 coupled in parallel between the first and second switches Q 1 and Q 2 and the power unit Vs and having a serial connection, and a primary coil Np of a transformer T; and an output terminal B including secondary coils Ns 1 and Ns 2 of the transformer T, rectifying diodes D1 and D2, an inductor Lo, and a ripple removing capacitor Co. A blocking capacitor CB is connected in series to the primary coil Np of the transformer T.
[Advantageous Effects)
As described above, the present invention controls such that no in-rush current that negatively influences the semiconductor switch in the asymmetric half bridge converter in the initial drive is generated, by connecting a blocking capacitor to the primary coil of the transformer, thereby allowing stability and reliability for power supply to the load.
[Description of Drawings]
FIG. 1 shows a circuit diagram for an asymmetric half bridge converter according to an exemplary embodiment of the present invention. FIG. 2 shows a waveform diagram of signals that are output by respective elements of an asymmetric half bridge converter according to an exemplary embodiment of the present invention.
FIG. 3 shows a waveform diagram of an input current and a current supplied to the primary coil of a transformer in an asymmetric half bridge converter according to an exemplary embodiment of the present invention.
FIG. 4 is a circuit diagram showing a conventional asymmetric half bridge converter.
FIG. 5 is a waveform diagram for an input current and a current supplied to the primary coil of a transformer in a conventional asymmetric half bridge converter. FIG. 6 is a waveform diagram for an input current and a current supplied to the primary coil of a transformer in another conventional asymmetric half bridge converter.
[Best Model
Hereinafter, referring to the drawings, an exemplary embodiment of the present invention will be described.
The present invention can be realized into many various formats and hence it is not restricted to the current exemplary embodiment described with reference to the present invention.
Also, parts that are not related to descriptions in the drawings are omitted for clarification of description, and parts that are the same or similar to those described in the prior art have the same reference numerals.
An asymmetric half bridge converter according to an exemplary embodiment of the present invention will now be described referring to FIG. 1.
As shown in FIG. 1, the asymmetric half bridge converter includes an input terminal A including a power unit Vs for supplying a rectified input voltage, a first link capacitor and a second link capacitor C1 and C2 functioning as a voltage doubter, a first switch and a second switch Q 1 and Q 2 that are switched according to a predetermined duty applied by a controller (not shown), and a primary coil Np of a transformer T; and an output terminal B including secondary coils N 51 and N S2 of the transformer T, rectifying diodes D1 and D2, an inductor Lo, and a ripple removing capacitor Co.
In the input terminal A, the first and second switches Q 1 and Q 2 are connected in series to the power unit Vs, and the first and second link capacitors C1 and C2 coupled in series are connected in parallel between the power unit Vs and the first and second switches Q 1 and Q 2 .
A blocking capacitor CB is connected between a node of the first link capacitor
C1 and second link capacitor C2 and a first terminal of the primary coil Np of the transformer T 1 and a second terminal of the primary coil Np of the transformer T is connected to a node provided between the first and second switches Q 1 and Q 2 coupled in series.
Therefore, the rectified voltage output by the power unit Vs is charged in the
first link capacitor C1 and the second link capacitor C2.
In this instance, the voltage Vci charged in the first link capacitor C1 is expressed in Equation 1.
(Equation 1)
Vc > 5
Also, the voltage Vc 2 charged in the second link capacitor C2 is expressed in Equation 2.
(Equation 2)
When the second switch Q 2 is turned on according to a predetermined duty, the voltage at the blocking capacitor C B coupled in series to the primary coil Np of the transformer T is expressed in Equation 3. (Equation 3)
where D-1 is a duty supplied to a gate terminal of the first switch Q 1 . An offset value of a limit current applied to the primary coil Np of the transformer T is expressed in Equation 4. (Equation 4)
where D is a duty supplied to a gate terminal of the second switch Q 2 . Therefore, when the first switch Q-i and the second switch Q 2 are switched according to a predetermined duty provided by the controller, the voltage supplied to
the primary coil Np of the transformer T is applied to the secondary coils Nsi and Ns 2 of the output terminal B to be thus applied as an operation power to the load Ro connected to the end terminal.
In this instance, the voltage Vo that is output through the secondary coils Ns 1 and Ns 2 with respect to the voltage supplied to the primary coil Np of the transformer T is expressed in Equation 5.
(Equation 5)
VV j >
where Np is a winding number of the primary coil of the transformer, Ns is a winding number of the secondary coil of the transformer, Vs is an output voltage of the power unit, D is a duty of the second switch Q 2 , and 1-D is a duty of the first switch Q 1 . In Equation 1 to Equation 5, it is given that C τ = C B /C| in κ and C-) = C 2 = Cπn k - The above-configured asymmetric half bridge is operated in a similar or like manner of the prior art. That is, as shown in (A) of FIG. 2, the first switch Q 1 performs an on/off switching operation according to the duty of 1-D, the second switch Q 2 performs an on/off switching operation according to the duty of D, the second switch Q 2 maintains the off state when the first switch Q 1 is turned on, and the first switch Q 1 maintains the off state when the second switch Q 2 is turned on. Therefore, when the on/off switching operation by the first switch Q 1 and the second switch Q 2 are generated, the charge and discharge operation by the first link capacitor C1 and the second link capacitor C2 is progressed as shown in (B), and the zero voltage switching is accordingly provided.
In this instance, the charge and discharge operation at the blocking capacitor C B coupled in series to the primary coil of the transformer T is performed as shown in
(C), the voltage V pri supplied to the primary coil Np of the transformer T is shown in (D), and the current l pr j has a waveform as shown in (E).
In the case of the general asymmetric half bridge, the voltage V C1 at the first link capacitor C1 is determined as DVs by the duty D of the second switch Q 2 and the power Vs, and the voltage V C2 at the second link capacitor C2 is determined as 1-DVs by the duty 1-D of the first switch Q 1 and the power Vs.
However, since the blocking capacitor C B is connected in series to the primary coil Np of the transformer T in the embodiment of the present invention, the offset value of the limit current of the transformer T is modified as expressed in Equation 4 according to the blocking capacitor C 5 .
Therefore, the voltages at the first link capacitor C1 and the second link capacitor C2 are changed by the blocking capacitor C B as expressed in Equation 2 and Equation 3.
Hence, when the first switch Qi is turned on according to the duty of 1-D in the initial drive, the voltage at the blocking capacitor C 6 is charged to Vs/2 from the first link capacitor C1 charged with Vs/2 by a very small current.
As a result, the voltage at the primary coil Np of the transformer T is OV.
In addition, when the second switch Q 2 is turned on according to the duty of D, the voltage of Vs/2 charged by the blocking capacitor CB and the voltage at the second link capacitor C2 are added to be supplied as the voltage of Vs at the primary coil Np of the transformer T.
Accordingly, the voltages at the primary coil Np and the secondary coil Ns of the transformer T are balanced by the voltage at the blocking capacitor C B in the initial drive to thus generate no in-rush current. For example, when the blocking capacitor C B coupled in series to the primary
coil Np of the transformer T is set to be 22OnF, the in-rush current is removed and the
current l in input from the power unit Vs is stable as shown in FIG. 3.
While this invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
[Industrial Applicability]
As described above, the present invention controls such that no in-rush current that negatively influences the semiconductor switch in the asymmetric half bridge converter in the initial drive is generated, by connecting a blocking capacitor to the primary coil of the transformer, thereby allowing stability and reliability for power supply to the load.