BACKGROUND

Device density in integrated circuits (ICs) has increased for decades in conformance with Moore’s law. However, as the lateral dimensions of a device structure shrink with each technology generation, it becomes increasingly difficult to further reduce structural dimensions.

Three-dimensional (3D) scaling is now of considerable interest as reductions in z- height (device thickness) offer another avenue of increasing overall device density and IC performance. 3D scaling may be in the form of chip stacking or packaged IC stacking, for example. Known 3D integration techniques are expensive and may offer only incremental improvements in z-height and device density. One challenge of 3D scaling is the electrical interconnect of stacked device layers or stratum. Dimensions of transistors may be only 20- 50nm, or less, for example. Interconnection of a terminal of one transistor with such dimensions to an underlying device layer, which may also include another transistor of similar dimensions, poses a significant manufacturing problem.

BRIEF DESCRIPTION OF THE DRAWINGS

The material described herein is illustrated by way of example, and not by way of limitation, in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements. In the figures:

FIG. 1 is a plan view of an integrated circuit (IC) wafer with expanded views of IC die on the wafer, and of transistors within the IC die fabricated with one or more asymmetrical terminal interconnects, in accordance with some embodiments;

FIG. 2 illustrates an expanded cross-sectional view of the transistors shown in FIG. 1 and further shows interlayer interconnection with asymmetrical terminal interconnects, in accordance with some exemplary embodiments;

FIG. 3 is a flow diagram illustrating methods for fabricating asymmetrical terminal interconnects suitable for interlayer interconnection of stacked devices, in accordance with some embodiments; FIG. 4, 5, 6, 7, 8, 9, 10, and 11 are cross-sectional views illustrating a portion of a device including stacked transistors evolving as selected operations in the methods illustrated in FIG. 3 are practiced, in accordance with some exemplary embodiments;

FIG. 12 illustrates a mobile computing platform and a data server machine including a processor with asymmetrical terminal interconnects, in accordance with some exemplary embodiments; and

FIG. 13 illustrates a functional block diagram of an electronic computing device, in accordance with some exemplary embodiments.

DETAILED DESCRIPTION

One or more embodiments are described with reference to the enclosed figures. While specific configurations and arrangements are depicted and discussed in detail, it should be understood that this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that techniques and/or arrangements described herein may be employed in a variety of other systems and applications other than what is described in detail herein.

Reference is made in the following detailed description to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. Further, it is to be understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of claimed subject matter. It should also be noted that directions and references, for example, up, down, top, bottom, and so on, may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of claimed subject matter is defined solely by the appended claims and their equivalents.

In the following description, numerous details are set forth. However, it will be apparent to one skilled in the art, that embodiments may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the embodiments. Reference throughout this specification to“an embodiment” or“one embodiment” or“some embodiments” means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase“in an embodiment” or“in one embodiment” or“some embodiments” in various places throughout this specification are not necessarily referring to the same embodiment.

Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

As used in the description and the appended claims, the singular forms“a”,“an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term“and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

The terms“coupled” and“connected,” along with their derivatives, may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments,“connected” may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other, without any intermediary materials or devices.“Coupled” may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship), through one or more passive or active intermediary materials or devices.

A“device” may generally refer to an apparatus according to the context of the usage of that term. For example, a device may refer to a stack of layers or structures, a single structure or layer, a connection of various structures having active and/or passive elements, etc. Generally a device is a three dimensional structure with a lateral x-y plane and a height along the z direction within an x-y-z Cartesian coordinate system. The plane of the device may also be the plane of an apparatus, which comprises the device.

The terms“over,”“under,”“front side,”“back side,”“top,”“bottom,”“over,” “under,” and“on” as used herein refer to a relative position of one component, structure, or material with respect to other referenced components, structures or materials within a device, where such physical relationships are noteworthy. These terms are employed herein for descriptive purposes only and predominantly within the context of a device z-axis and therefore may be relative to an orientation of a device. Hence, a first material“over” a second material in the context of a figure provided herein may also be“under” the second material if the device is oriented upside-down relative to the context of the figure provided. In the context of materials, one material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material“on” a second material is in direct contact with that second material. Similar distinctions are to be made in the context of component assemblies.

The term“adjacent” generally refers to a position of a thing being laterally (within an x-y plane) next to (e.g., immediately next to), or adjoining another thing (e.g., abutting it).

The term“between” may be employed in the context of the z-axis, x-axis or y-axis of a device. A material that is between two other materials may be in contact with one or both of those materials, or it may be separated from both of the other two materials by one or more intervening materials. A material“between” two other materials may therefore be in contact with either of the other two materials, or it may be coupled to the other two materials through an intervening material. A device that is between two other device may be directly connected to one or both of those devices, or it may be separated from both of the other two devices by one or more intervening devices.

Unless otherwise specified the use of the ordinal adjectives“first,”“second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

As used throughout this description, and in the claims, a list of items joined by the term“at least one of’ or“one or more of’ can mean any combination of the listed terms. For example, the phrase“at least one of A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B and C.

Unless otherwise specified in the explicit context of their use, the terms“substantially equal,”“about equal” and“approximately equal” mean that there is no more than incidental variation between two things so described. In the art, such variation is typically no more than +/-l0% of a predetermined target value.

As described further below, one or more terminal interconnects of a device are positioned asymmetrically relative to one or more underlying features of the device. The terminal interconnect may overlap the underlying feature, with a difference between a footprint of the terminal interconnect and the feature to one side of the semiconductor body (bodies). With a majority of the overlapping area of the terminal interconnect biased to one side of the feature, a majority the terminal interconnect overlap that is adjacent to a side of the feature can define a conductive via that may be interconnected with another underlying feature, such as another device layer or interconnect metallization layer of a stacked device, without exceeding the via exceeding a threshold aspect ratio. In some embodiments described further below, a terminal interconnect coupled to a gate, source, or drain terminal of a finFET in a vertically-stacked device is positioned asymmetrically to a semiconductor fin. A portion of the terminal interconnect adjacent to one side of the fin extends to a depth below a plane of the fin and intersects another interconnect, or another device terminal, that is in another plane of the stacked device.

FIG. 1 is a plan view of IC wafer 100 with an expanded view of an IC die 101, and of a further expanded view of a logic transistor structure 103 disposed within IC die 101, in accordance with some embodiments. In the example shown in FIG. 6, a plurality of transistor structures 103 are arrayed over an area of a device layer within IC die 103. Additional device cells 102 may be, for example, any of memory cells, power transistor structures, RF transistor structures, optical device cells, or the like. Exemplary transistor structures 103 include a multi-fin field effect transistor (FET) 107 and a single-fin FET 108. Each of FETs 107 and 108 include a gate terminal between source and drain terminals. In some embodiments, source and drain terminals include semiconductor having the same conductivity type (e.g., both n-type or both p-type). In other embodiments, the source and drain terminals include semiconductor having complementary conductivity type (i.e., a tunnel FET, or TFET). The FET may also include a heterojunction (i.e., HFET) and may also qualify as a high electron mobility transistor (HEMT) when the channel comprises a Group III-V or Group III-N material. In FIG. 6, solid lines within transistor structures 103 denote salient materials overlying other material or structural features denoted in dashed lines within one transistor structure stratum. Heavy dot-dashed line in FIG. 6 denote a plane A-A’ along which cross- sectional views are further provided in FIG. 2.

As further shown in FIG. 1, transistor structures 103 are over an underlying device stratum 105 with semiconductor bodies (e.g., fins) 110 embedded within a front-side, or top side, device stratum. Field isolation dielectric material 180 surrounds FETs 107 and 108.

Field isolation dielectric material 180 may have any composition of suitable dielectric strength for the purpose of electrically isolating adjacent devices, such as, but not limited to, silicon dioxide, silicon nitride, silicon oxynitride, and low-k materials (e.g., having a relative permittivity below 3.3). In FET 107, gate metal 173 is over a channel region of each of a first and a second semiconductor body 110A and 110B. Although two semiconductor bodies 110A and 110B are illustrated in FIG. 6, a non-planar FET may include one, or more than two such semiconductor bodies. For example, FET 108 includes one semiconductor body 110C. In some exemplary embodiments, semiconductor bodies 110, 110A and 110B include at least one semiconductor region, which may have any composition that is suitable for a field effect transistor. In some exemplary embodiments, semiconductor bodies 110A-C include one or more group IV (i.e., IUPAC group 14) semiconductor material layers (e.g., Si, Ge, SiGe), group III-V semiconductor material layers (e.g., GaAs, InGaAs, InAs, InP), or group III-N semiconductor material layers (e.g., GaN, AlGaN, InGaN). Semiconductor bodies 110A-C may also include one or more semiconductor transition metal dichalcogenide (TMD or TMDC) layers. In other embodiments, semiconductor bodies 110A-C include one or more graphene layer, or a grapheme material layer having semiconductor properties. In still other embodiments, semiconductor bodies 110A-C include one or more oxide semiconductor layers. Exemplary oxide semiconductors include oxides of a transition metal (e.g., IUPAC group 4-10) or post-transition metal (e.g., IUPAC groups 11-14). In

advantageous embodiments, the oxide semiconductor includes at least one of Cu, Zn, Sn, Ti, Ni, Ga, In, Sr, Cr, Co, V, or Mo. The metal oxides may be suboxides (A2O) monoxides (AO), binary oxides (AO2), ternary oxides (ABO3), and mixtures thereof. In other embodiments, semiconductor bodies 110A-C includes one or more magnetic, ferromagnetic, ferroelectric material layer. For example, semiconductor bodies 110A-C may include one or more layers of any material known to be suitable for an tunneling junction device, such as, but not limited to a magnetic tunneling junction (MTJ) device.

In some embodiments, semiconductor bodes 110A-C are substantially

monocrystalline. For monocry stalbne embodiments, a significant number of crystalline defects may nonetheless be present. In other embodiments, semiconductor bodies 110A-C are amorphous or poly crystalline (e.g., micro or nano crystalline). Semiconductor bodies 110A- may have any width (e.g., y-dimension in FIG. 1). In some exemplary embodiments, semiconductor bodies 110A-C have a width less than 20nm and advantageously less than lOnm and more advantageously between 4nm and 9nm. As further illustrated in FIG. 1, source and drain metallization 150 is disposed adjacent to gate metal 173 and also extends across semiconductor bodies 110A-C. Source and drain metallization 150 may include one or more metals (e.g., Ti, W, Pt, their alloys, nitrides, carbides, etc.) that form an ohmic or tunneling junction with doped source/drain semiconductor 640. In the illustrated

embodiment, source and drain metallization 150 is on regrown or raised source and drain semiconductor 140, which is further in contact with semiconductor bodies 110. Source and drain semiconductor 140 may include electrically active impurities imparting n-type or p-type conductivity. For some exemplary embodiments, both the source and drain semiconductor 140 is doped to the same conductivity type (e.g., n-type for NMOS and p-type for PMOS). In alternative embodiments (e.g., for a tunneling FET), source and drain semiconductor 140 is doped to have complementary conductivity (e.g., n-type source and p-type drain).

Source/drain semiconductor 140 may be any semiconductor material compatible with semiconductor bodies 110A-C, such as, but not limited to, group IV semiconductors (e.g., Si, Ge, SiGe), and/or group III-V semiconductors (e.g., InGaAs, InAs), and/or group III-N semiconductors (e.g., InGaN), and/or (metal) oxide semiconductors.

An electrically insulating spacer dielectric 171 laterally separates gate metal 173 from source and drain metallization 150 and/or source and drain semiconductor 140. Spacer dielectric 171 may be or any dielectric such as, but not limited to, silicon dioxide, silicon nitride, or silicon oxynitride, or any known low-k material having a relative permittivity below 4.0. Although only one gate metal 173 is illustrated in solid line as being part of a single logic transistor structure, an exemplary second gate metal 173 is drawn in dashed line as being associated with an adjacent transistor structure.

In some embodiments, one or more terminal interconnects are laterally offset to a first side of a device structure. For a given device structure having a centerline about which it is substantially symmetric, a device terminal interconnect extends laterally beyond a first side of the device structure by significantly more (e.g., by 30%, or more) than it does a second side of the device structure. For the example illustrated in FIG. 1, multi -finned FET 107 has a transistor centerline that extends between bodies 110A and 110B, in a direction parallel to their longitudinal lengths (e.g., x-dimension). Gate metal 173 is laterally offset from the transistor centerline (e.g., in a +y-direction). A first portion of gate metal 173 on a first side of the transistor centerline has a width Wl (between a sidewall edge of gate metal 173 and the transistor centerline). Width Wl is significantly larger than width W2 on a second side of the transistor centerline to a sidewall edge of gate metal 173. For multi-finned FET 107, only gate metal 173 is laterally offset from the transistor centerline with the other terminal interconnects (e.g., source and drain metallization 150) symmetrically positioned with respect to the transistor centerline to emphasize the lateral offset of gate metal 173. However, either (or both) source and drain metallization 150 may be laterally offset in substantially the same manner as illustrated for gate metal 173. For embodiments where multiple terminal interconnects are laterally offset for one device, the direction of offset may vary between terminal interconnects and/or the magnitude of the offset may also vary.

As shown for FET 108, the transistor centerline for single-fin device extends through a longitudinal axis of semiconductor body 110C. Gate metal 173 is again laterally offset from the transistor centerline (e.g., in a +y-direction). For FET 108, a first portion of gate metal 173 on a first side of the transistor centerline has a width W3 (between a sidewall edge of gate metal 173 and the transistor centerline), which is again significantly larger than width W4 on a second side of the transistor centerline. Although only gate metal 173 is laterally offset from the transistor centerline of FET 108, with the other terminal interconnects (e.g., source and drain metallization 150) being symmetrically positioned with respect to the transistor centerline, either (or both) source and drain metallization 150 may be laterally offset in substantially the same manner as illustrated for gate metal 173.

FIG. 2 illustrates an expanded cross-sectional view of the transistor structures 103 shown in FIG. 1. FIG. 2 further shows interlayer interconnection with asymmetrical device terminal interconnects in accordance with some exemplary embodiments. Transistor structures 103 are within a front-side (or top) device layer (or stratum) 105. Device layer 205, underlying device layer 105, further includes transistor structures 203 and interconnect metallization 204. Transistor structures 203 may have any of the structural features or attributes of transistor structures 103. For example, as shown in the sectional view illustrated FIG. 2, transistor structures 203 includes a gate metal 273 and a work function metal 273 over a channel portion of semiconductor bodies 210. Transistor structures 203 are surrounded by an isolation dielectric material 280, which may have any suitable composition, such as any of those described above for dielectric material 180. In some embodiments, transistor structures 203 are substantially identical to transistor structures 103. In other embodiments, transistor structures 203 are dimensionally and/or compositionally, and/or functionally different from transistor structures 103. Although transistor structures 203 are included in the illustrated embodiment, device layer 205 may alternatively include any other device known to be compatible with an IC (e.g., a volatile or non-volatile memory device, a MEMs, a photodiode, a photovoltaic, etc.)

As further shown in FIG. 2, gate metal 173 is one metal of a composite terminal interconnect structure that includes at least two metal regions. In the illustrated example, gate metal 173 is a fill metal that is over a layer of a work function metal 272. Work function metal 272 may have any composition suitable for controlling the channel conductivity of a semiconductor channel. Work function metal 272 may have any suitable work function and may be an elemental metal layer, a metal alloy layer, or even a doped semiconductor (e.g., polysilicon) layer. Work function metal 272 may include at least one P-type work function metal or N-type work function metal, depending on conductivity type of the transistor channel (e.g., NMOS transistors with N-type work function metal and PMOS transistors with P-type work function metal). For PMOS transistors, metals that may be used for work function metal 272 include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For NMOS transistors, metals that may be used for work function metal 272 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. Gate metal 173 may be a fill metal of any composition known to be compatible for a transistor gate electrode (e.g., having suitable electrical conductivity, adhesion, and fill properties, etc.). Transistor structures 203 may have a similar gate electrode, for example with gate metal 173 also being any suitable fill metal over any suitable work function metal 272.

Work function metal 272 is separated from semiconductor body 110 by a gate dielectric 211. Gate dielectric 211 may have any composition and any thickness known to be suitable for transistors having a channel of a given semiconductor composition and operable under given bias conditions. In some embodiments, gate dielectric 211 is a material having a conventional relative permittivity (e.g., k value below 9), such as, but not limited to silicon dioxide, silicon oxynitride, or silicon nitride. In some other embodiments, gate dielectric 211 is a material having a high relative permittivity (e.g., k value above 10). The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. The high-k material in some embodiments is a metal oxide (e.g., comprising one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate). The high-k material in some embodiments is a metal silicate (e.g., comprising one or more of above metals, oxygen and silicon). In still other embodiments, gate dielectric 211 includes two or more dielectric material layers, such as, but not limited to, a layer with a higher relative permittivity over a layer with a lower relative permittivity. The one or more layers may include silicon oxide, silicon dioxide (SiCh) and/or a high-k dielectric material.

As further shown in FIG. 2, asymmetrical device terminal interconnects in an overlying device layer that are laterally offset to one side of a semiconductor body may be advantageous for increasing the footprint of an electrically conductive via that extends from the overlapping portion of the device terminal interconnect and into an underlying material. For FET 108, gate metal 173 has a footprint associated with the sum of partial widths W3 and W ₄ . Gate metal 173 is laterally offset from the denoted centerline of semiconductor body 110, so partial width W3 is larger than partial width Wr to the extent that a portion of gate metal 173 extends beyond one side of semiconductor body 110C by an overlap width Wo, which may satisfy some predetermined threshold. Partial width Wr is sufficiently small that no portion of gate metal 173 extends beyond the opposite side of semiconductor body 110C with the only a width Ws of a work function metal sidewall spacer 272C overlapping beyond semiconductor body 110C. Likewise, for FET 107, gate metal 173 has a footprint associated with the sum of partial widths Wi and W2. Gate metal 173 is laterally offset from the denoted centerline of the pair of semiconductor bodies 110A and 110B, so partial width Wi is larger than partial width W2 to the extent that a portion of gate metal 173 extends beyond one side of semiconductor body 110A by the overlap width Wo, which may satisfy the predetermined threshold. Partial width W2 is sufficiently small that no portion of gate metal 173 extends beyond the opposite side of semiconductor body 110B with the only the width Ws of a work function metal sidewall spacer 272B overlapping beyond semiconductor body 110B.

In FIG. 2 it can be seen that if partial width W3 is reduced toward equality with partial width W ₄ , overlap width Wo will approach a minimum of approximately ½ the difference between the width of gate metal 173 (e.g., the sum of partial widths W3 and Wr) and the width of semiconductor body 110 summed with approximately twice the thickness of gate dielectric 211. Likewise, if partial width Wi is reduced toward equality with partial width W2, overlap width Wo will approach a minimum of approximately ½ the difference between the width of gate metal 173 (e.g., the sum of partial widths Wi and W2) and the widths of semiconductor bodies 110A and 110B summed with the space between semiconductor bodies 110A and 110A, a portion of which is occupied by gate dielectric 211 in this example. Hence, while conventional overlay rules would typically specify symmetrical device terminal interconnect overlap on both sides of semiconductor body 110, symmetrical overlap would result in minimum overlap width on each illustrated side of semiconductor body 110 that may be only slightly larger twice the work function metal sidewall spacer width Ws. However, with gate metal 173 instead laterally offset to one side of semiconductor body 110, there is a larger overlap width Wo that increases the footprint of an electrically conductive via 250C extending from the overlapping portion of the device terminal interconnect. A laterally offset device terminal interconnect of a given footprint can therefore facilitate electrical coupling of the device terminal interconnect to an underlying circuit node through a conductive via having less than some threshold aspect ratio, whereas a symmetrically positioned terminal interconnect of the same footprint would necessitate a via with a significantly higher aspect ratio (e.g., associated with a lateral via diameter of only ½ a threshold overlap width Wo). Higher via aspect ratios may be associated with a significantly lower via conductivity, which may be detrimental to the operation of a stacked device. Higher via aspect ratios may also result in an electrically open circuit if an aggressive aspect ratio cannot be properly filled with metallization.

From FIG. 2 it can be further seen that as partial width W3 approaches partial width W ₄ , overlap width Wo approaches a minimum of approximately ½ the difference between the width of gate metal 173 (e.g., the sum of partial widths W3 and W ₄ ) and the width of semiconductor body 110 summed with approximately twice the thickness of gate dielectric 211. Hence, while conventional overlay rules would typically specify symmetrical device terminal interconnect overlap on both sides of semiconductor body 110, symmetrical overlap would result in minimum overlap width on each illustrated side of semiconductor body 110 that may be only slightly larger than twice the work function metal sidewall spacer width Ws.

Overlap width Wo may satisfy any dimensional threshold (e.g., 4nm, 9nm, 12 nm, etc.) sufficient to ensure an acceptable aspect ratio for a conductive via that extends from the overlapping portion of a device terminal interconnect, and into and an underlying device layer. With work function metal spacer width W _s being smaller than Wo, the dimensional threshold is not met along the opposite side of semiconductor body 110A, and no comparable conductive via extends from this edge of the device terminal interconnect. For the example illustrated in FIG. 2, the aspect ratio of an inter-device layer via 250C may be limited to some ratio of via depth to lateral via diameter (e.g., 4: 1, 10: 1, etc.) that will ensure via 250C is adequately filled with metallization for sufficient via conductivity. Hence, the threshold for overlap width Wo in a given architecture may be a function of the thickness of dielectric material between strata of a stacked integrated circuit device. In the illustrated example, via 250C extends through dielectric materials 190 and 191. Dielectric materials 190 and 191 may each have any composition known to be suitable as an IC interlayer dielectric (ILD), such as, but not limited to, the exemplary materials provided above for dielectric material 180. The threshold lateral dimension of overlap width Wo may depend, at least in part, on the thickness of dielectric materials 190, 191 traversed by via 250C. Notably, although two dielectric materials 190 and 191 are illustrated in FIG. 2, one or more such dielectric materials may be present between device layers of a stack integrated circuit device and embodiments herein are not limited in this respect.

A laterally offset device terminal interconnect of a multi-finned device may include one or more conductive vias to an underlying device layer. A laterally offset device terminal interconnect of a multi-finned device may, for example, advantageously increase the number of vias that couple a device terminal to an underlying device layer. For FET 107 further shown in FIG. 2, semiconductor bodies 110A and 110B are separated by a space that is approximately equal to overlap width Wo. While spacing between semiconductor bodies 110A and 110B may be larger than overlap width Wo, a spacing width that is at least equal to the overlap width Wo facilitates a conductive via between semiconductor bodies 110A and 110B and this conductive via may be supplemented by a second conductive via facilitated by the lateral offset of the device terminal interconnect. Hence, the gate electrode of FET 107 has two overlapping portions, each with overlap width Wo. Two inter-device layer conductive vias 250A and 250B extend through dielectric materials 190 and 191. Vias 250A and 250B may have approximately equal top diameters, which may be a function of overlap width Wo, as further described below. As such, the lateral widths of conductive vias 250A and 250B may differ. For example, where gate electrode 173 is made even more asymmetric (e.g., Wi exceeding W2 by an even greater amount than illustrated), conductive via 250A will become wider than conductive via 250B. In some embodiments where the lateral widths (y- dimension) of fins 110A and 110B is defined by the width of a spacer formed about a sacrificial backbone according to an arbitrary pitch reduction technique, a pitch of the backbone may result in conductive via 250B have a different lateral width than conductive via 250A

As further illustrated in FIG. 2, work function metal spacer width Ws for the multi- finned device is again smaller than Wo, and with the dimensional threshold not met along an outside of semiconductor body 110B no comparable conductive via extends from this edge of the device terminal interconnect. However, in other embodiments there may be a narrow lateral width of gate metal 173, or even a void, between fin 110B and dielectric material 180 when overlap exceeds work function metal spacer width Ws. Depending on the lateral dimension, the overlap region on this side of fin 110B may not completely fill with a metal, and/or work function metal portion 272B may not merge with a remainder of work function metal 272. Such artifacts are not likely to be significant in the function of devices and are merely noted here in recognition of some of the possible variations from the illustrated embodiments.

Conductive vias 250A, 250B and 250C extend below semiconductor bodies 210 and each via intersects, or makes contact to, interconnect metallization features 277 that are embedded within a dielectric material 192. Dielectric material 192 may also have any composition known to be suitable as an IC ILD, such as, but not limited to, the exemplary materials provided above for dielectric material 190. In the illustrated example, conductive via 250A contacts a first of interconnect metallization features 277, conductive via 250B contacts a second of interconnect metallization features 277, and conductive via 250C contacts a third of interconnect metallization features 277. Conductive vias 250A and 250B may electrically couple one laterally offset device terminal to two different circuit nodes. Alternatively, multiple conductive vias in contact with a laterally offset device terminal may further contact a single underlying interconnect metallization feature. For example, both conductive vias 250A and 250B may couple a single laterally offset gate electrode to one other circuit node, in which case the two vias 250A and 250B may have higher conductivity than a single via). Conductive via 250C, along with vias 250A and/or 250B may also electrically couple two or more different laterally offset device terminals to a single interconnect feature associated with one IC node.

In still other embodiments, one or more conductive vias directly couple one or more laterally offset device terminal with one or more underlying device terminal. For example, in FIG. 2 where device layer 205 further includes transistor structures 203, conductive via 250A and/or conductive via 250B and/or conductive via 250C may be in direct contact with one or more underlying device terminal. Hence, an inter-device layer via may couple an overlying laterally offset device terminal directly to a gate metal 273 that is over a channel region of semiconductor bodies 210, 210A or 210B. An inter-device layer via may also couple an overlying laterally offset device terminal directly to a source or drain terminal interconnect that is over a source or drain region of semiconductor bodies 210, 210A or 210B. In still other embodiments, one or more conductive vias coupled to a laterally offset device terminal make direct contact with one or more underlying semiconductor bodies. For example, conductive via 250A and/or conductive via 250B, and/or conductive via 250C may directly couple gate metal 173 to one or more portions of semiconductor bodies 210A, 210B (e.g., a source region and/or a drain region).

Device terminal interconnects of adjacent devices may be laterally offset by substantially the same magnitude. For example, in FIG. 2, the gate electrodes of both FET 107 and FET 108 are laterally offset from semiconductor bodies 210, 210A and 210B by substantially the same amount such that the overlap width Wo is the same for both FETS 107 and 108. Although only two laterally offset device terminals are illustrated in FIG. 2, in some embodiments at least one device terminal of all devices within a given device layer are laterally offset by substantially the same amount. For example, gate electrodes for all transistors within device layer 105 may be offset by the same amount such that the overlap width Wo is the same for transistors. In other embodiments where a source and/or drain terminal interconnect is laterally offset, for example in a manner similar to that illustrated in FIG. 2 for a gate electrode, source and/or drain terminal interconnects for all transistors within device layer 105 may be likewise offset by the same magnitude. Alternatively, one or more device terminal interconnects of only a subset of devices within a given device layer may be lateral offset. For example, the two laterally offset device terminals illustrated in FIG. 2 may be in a subset of transistors in device layer 105 that have offset device terminal interconnects while other transistors within device layer 105 have symmetrical device terminal interconnects. The magnitude of lateral offset may be substantially equal across those transistors that have laterally offset device terminal interconnects.

As noted above, the threshold overlap width of a laterally offset device terminal interconnect is sufficient to ensure a conductive via of an acceptable aspect ratio couples the overlapping portion of the terminal interconnect to an underlying circuit node. In view of the nanometer dimensions of device structures, formation of the conductive via is

advantageously self-aligned to the laterally offset device terminal interconnect, for example as further described below. In the exemplary embodiments illustrated in FIG. 2, conductive via 250C has a top width WT that is substantially equal to the overlap width Wo minus twice the sidewall spacer width Ws of work function metal 272 that is adjacent to a sidewall of semiconductor body 210A and/or 210B. Conductive vias 250A and 250B also have a top width WT that is substantially equal to the overlap width Wo minus twice the sidewall work function metal spacer width Ws. This relationship between the conductive via diameter the overlap width Wo and the sidewall work function metal spacer width Ws is indicative of conductive vias 250A-250C having been self-aligned the laterally offset gate electrode. Specifically, the via top width WT is equal to the width of an opening 282 that extends through the work function metal 272 within the overlapping portions of the gate electrode. Gate metal 173 extends through opening 282 and into vias 250A-250C. Opening 282 is bounded by work function metal spacers 272A, and therefore the via top width WT is substantially equal to the overlap width Wo minus twice the sidewall work function metal spacer width Ws.

FIG. 3 is a flow diagram illustrating methods 301 for fabricating asymmetrical terminal interconnects suitable for interlayer interconnection of stacked devices, in accordance with some embodiments. Methods 301 may be employed, for example, to fabricate the transistor structures illustrated in FIG. l and FIG. 2, for example. Methods 301 further exemplify formation of a transistor structure stratum that may be no more than a few hundred nanometers in thickness. As described elsewhere herein, such a stratum is amenable to being vertically stacked into a 3D IC having potentially very high vertical cell density (e.g., high strata count/micrometer thickness).

Methods 301 begin at operation 310 where non-planar semiconductor bodies (e.g., fins) are formed on a substrate. Operation 310 may, for example, entail any processes known to be suitable for fabricating semiconductor fins, as embodiments herein are not limited in this respect. Methods 301 continue at operation 315, where isolation dielectric material is formed adjacent to sidewalls of the semiconductor bodies asymmetrically. The formation of asymmetric isolation material may include one or more processes that form isolation material to a larger lateral width on one side of a semiconductor body than on an opposite side of the semiconductor body. In some exemplary embodiments, as described further below, asymmetric isolation material is formed by first depositing a layer of substantially uniform thickness over a semiconductor body followed by anisotropically etching and/or sputtering that layer with any process that removes the layer on one side of the body at a higher rate than on an opposite side of the fin. Such anisotropic etching and/or sputtering may be with a highly directional process, for example that is angled or tilted in a manner that results in one side of the isolation material being shadowed by the non-planar semiconductor body. Such anisotropic etching and/or sputtering may also be facilitated by a pre-treatment of the layer with a highly directional process, for example that is angled in a manner that results in one side of the isolation material being shadowed by the non-planar semiconductor body.

With the asymmetric isolation material adjacent to the non-planar semiconductor bodies methods 301 continue at operation 320 where another isolation dielectric material is deposited over the semiconductor bodies (e.g., fins) and over the asymmetric isolation material. Operation 320 may entail any deposition process(es) known to be suitable for embedding the non-planar semiconductor bodies within a dielectric of any composition suitable for electrical isolation of IC devices. In some embodiments a flowable oxide is deposited at operation 320, for example with any chemical vapor deposition process or spin- on deposition process suitable for the selected material. The isolation dielectric is then planarized at operation 325 to expose some portion of the asymmetric isolation material. Any planarization process, such as a chemical mechanical planarization (CMP) process, having suitable uniformity may be employed at operation 325.

Methods 301 continue at operation 330 where the asymmetric isolation material is removed selectively to the semiconductor body and the additional isolation dielectric material. The asymmetric isolation material may be selectively removed, for example, with an isotropic or anisotropic etch process that removes the asymmetric isolation material at a significantly higher rate than the semiconductor body and remaining isolation dielectric. At least a portion of the isolation removal may be self-aligned to the asymmetric geometry of isolation material, resulting in the formation of asymmetrical openings that follow the profile of the asymmetrical isolation material between the semiconductor body and surrounding isolation dielectric material.

Methods continue at operation 335 where a via opening is etched into a substrate layer that is below the semiconductor body. At least a portion of the via opening etched at operation 335 is advantageously self-aligned to the opening formed during the etch of the asymmetric isolation at operation 330. The via etch at operation 335 may therefore be at least partially self-aligned to be adjacent to an edge of the semiconductor body, and may be further masked by the additional isolation dielectric that was deposited at operation 320. The via etch at operation 335 may also have top lateral dimension that is dependent on the lateral dimensions of the asymmetric isolation material.

Methods 301 continue at operation 340, where the via formed at operation 335 is at least partially filled with metallization to form a conductive via. The conductive via metallization may also couple (directly or capacitively) to a sidewall of the semiconductor body to further function as the device terminal interconnect metallization. The device terminal interconnect metallization formed may be made asymmetrical to the semiconductor body as a result of the isolation material asymmetry. Any processes known to be suitable for depositing metallization material layer(s) may be employed at operation 340. In some embodiments, for example as further described below, the via formation operation 335 and/or via filling operation 340 may be made dependent on the lateral dimensions of the opening formed during the asymmetric isolation etch at operation 330. For some such embodiments, one or more material layer formed prior to, or during via fill may further serve as a process- based technique for selectively forming conductive vias within regions of sufficiently large lateral dimension (e.g., satisfying some predetermined threshold). In some examples, one or more dielectric materials may be deposited in conjunction with formation of the device terminal interconnect metallization. Such dielectric materials may be deposited prior to forming the via at operation 335. For example, where the device terminal interconnect is a gate electrode, a gate dielectric may be deposited or otherwise formed following the spacer removal operation 330. In a similar vein, the operations of methods 301 need not rigidly follow the sequence exemplified by methods 301. For example, if the device terminal interconnect fabricated at operation 340 has more than one material layer, operation 335 may be performed after one or more layers of the device terminal interconnect is formed, but prior to forming another layer of the device terminal interconnect. The one or more layers of the device terminal interconnect initially formed may therefore also serve as a process-based technique for selectively forming a conductive via within a region having a sufficiently large lateral dimension. The one or more layers of the device terminal interconnect formed subsequently to via formation may therefore also serve to fill any via opening selectively formed.

Following formation of the device terminal interconnect(s) and conductive via(s), methods 301 end at operation 350 where fabrication of the stacked device is completed following any suitable technique(s) known in the art. Any stacked devices having any stacked device architecture that includes a laterally offset device terminal and a conductive via in accordance with embodiments herein may be so fabricated.

To further illustrate methods 301, FIG. 4, 5, 6, 7, 8, 9, 10, and 11 provide cross- sectional views of a portion of a device including stacked transistors evolving as selected operations in the method 301 are practiced, in accordance with some exemplary

embodiments. Referring first to FIG. 4, structure 401 is on a workpiece (e.g., a wafer) that may be received by any upstream fabrication process. The workpiece includes semiconductor bodies over a substrate layer. In the example show in FIG. 4, structure 401 includes a semiconductor fin 110C spaced apart from a pair of semiconductor fins 110A and 110B by a lateral distance Sl that is greater than a lateral spacing S2 between fin 110A and 110B. Fins 110A-C may have been fabricated upstream using any techniques known to be suitable for finFET fabrication. Fins 110A-C are over dielectric material 190. Fins 110A-C may, for example, have been fabricated from a semiconductor on insulator (SOI) substrate, with dielectric material 190 being the insulator layer. Alternatively, dielectric material 190 may have been deposited over a bottom or backside of fins 110A-C during some upstream processing. In other alternative embodiments fins 110A-C may be protrusions from a bulk semiconductor substrate layer, such as, but not limited to a bulk monocrystalline silicon wafer.

Structure 401 further includes a cap 411 over fins 110A-C, which may be any hardmask material (e.g., dielectric, intermetallic or metallic compound) suitable for achieving a desired fin height (e.g., z-dimension), etc. An isolation material 415 has been deposited over fins 110A-C and over cap 411. Isolation material 415 may be any material composition suitable for conformal deposition process, such as, but not limited to, silicon dioxide, silicon nitride, and silicon oxynitride. Isolation material 415 may have been deposited by chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), and atomic layer deposition (ALD), for example. As shown, isolation dielectric film 415 is deposited to a thickness sufficient to fill the space S2 between fins 110A and 110B, but insufficient to fill the larger space Sl between fin 110C and fin 110B. As further shown in FIG. 4, isolation dielectric material 415 is symmetric about, or centered over, the centerline between fins 110A and 110B with width Wl equal to width W2.

Structure 501 is then subjected to directional, or anisotropic, processing which will form an asymmetric isolation dielectric spacer. Such anisotropic processing may for example, entail a first (laterally symmetric) etchback of isolation material 415 to form a spacer that is substantially symmetric about the fin(s) centerline, followed by laterally asymmetric removal of a portion of the spacer. Alternatively, such processing may entail an asymmetric etchback of isolation material 415 to directly form an asymmetric isolation material. Following any such etchback process(es), a portion of an isolation material 515 on one side of the fin(s) has a sidewall thickness (Tl) that is much greater than sidewall thickness (T2) on the opposing side of the fin(s). In the illustrated embodiment, sidewall thickness (T2) is substantially nil after the anisotropic processing.

There are many options for asymmetrically forming isolation material 515. In the illustrative embodiments, a directional reactive ion etch and/or sputter and/or implant ion flux 510 is depicted, during which fins 110A-C at least partially shadow a portion of isolation material 415 that is laterally adjacent to the protected side of the fins. Ion flux 510 may sputter and/or chemical etch away unshadowed portions of isolation material 415. Such a directional etch process is commercially available from one or more suppliers of

semiconductor processing equipment, for example. Ion flux 510 may also, or in the alternative physically and/or chemically modify, unshadowed portions of isolation material 415 rendering that material more susceptible to a subsequent removal process. In still other embodiments, ion flux 510 may also render unshadowed material more resistant to a subsequent removal process, in which case the direction of ion flux 510 or the resulting isolation material asymmetry may be opposite from that shown in FIG. 5.

For the illustrated embodiments, ion flux 510 may include one or more ionic species, such as, but not limited to Argon (Ar), Xenon (Xe), or Krypton (Kr) ions. Doses and energies may vary among any suitable for the application. In some further examples, any of the exemplary ionic species may be provided at a dose of lel6/cm ² , or higher. Energies may vary, but need not be more than lKeV, for example. Shadowing that facilitates advantageous asymmetry may be sufficient at orientations as little as 10-30 degrees off-axis (off-normal to the x-y plane of the workpiece). With such processes, a portion of fins 110A-C is exposed while a remnant of the isolation dielectric layer remains as isolation dielectric spacer 515. As a result of such ion flux, ionic species (e.g., any of those listed above) may be embedded within at least the unshadowed portion of fins 110A-C. Such ionic species may have no detrimental impact to device operation. The presence of such ionic species within a portion of fins 110A-C, in conjunction with an asymmetric terminal interconnect may be indicative of the technique employed in the fabrication of the asymmetric terminal interconnect.

Following anisotropic processing, another layer of dielectric material may be deposited, for example to supplement the isolation dielectric spacer and/or to build up a minimum thickness of material on the side of the fin structures where the isolation material has been removed. Any deposition process may be employed, but in some advantageous embodiments, a conformal deposition process is performed to symmetrically increase the dielectric material thickness by a target amount on both sides of the fins. FIG. 6 further illustrates a structure 601 that includes structure 501 and further includes a dielectric material 615, which has been deposited over isolation dielectric spacer 515 and over fins 110, 110A, and 110B. As shown, dielectric material 615 has a thickness T3 over a sidewall of fins 110, 110A and 110B. Hence, since isolation dielectric spacer 515 was substantially removed in structure 501, the thickness of dielectric material on one side of fins 110, 110A and 110B is only thickness T3 (with T2 being nil, or nearly so) while the thickness of dielectric material on the opposite side of fins 110, 110A and 11B being equal to a sum of Tl and T3. The composition of dielectric material 615 may vary. In some exemplary embodiments, dielectric material 615 has substantially the same composition as isolation dielectric spacer 515.

FIG. 7 further illustrates a structure 701 that includes structure 601 and further includes isolation material 180, which has been deposited over dielectric material 615.

Isolation material 180, introduce above in the context of FIG. 1, advantageously has a different composition than dielectric material 615, and a different composition than isolation dielectric spacer 515. Isolation material 180, may be formed by any process known to be suitable for the chosen material, such as, but not limited to CVD, PECVD, flowable oxide deposition processes and/or spin-on processes. With spaces between fins substantially backfilled, isolation material 180 may be planarized, for example with a chemical mechanical polish process to expose a top surface of dielectric material 615 and asymmetric isolation material 515. With these top surfaces exposed, dielectric material 615 and asymmetric isolation material 515 may be etched selectively relative to isolation material 180. FIG. 8 illustrates a structure 801 that includes structure 701 following a selective etch of dielectric material 615 and asymmetric isolation material 515, in accordance with some exemplary embodiments. As shown, openings 805 expose a sidewall of fins 110A-C, and are adjacent to opposite sides of the fins. Lateral dimensions of openings 805 are dependent, at least in part, on the lateral dimensions of dielectric material 615 and asymmetric isolation material 515. In the illustrated embodiment, openings 805 on one side of fins 110A-C have a lateral dimension substantially equal to Tl summed with T3, while openings 805 on an opposite side of fins 110A-C have a lateral dimension substantially equal to only T3. Hence, the maskless processing performed upstream has enabled openings 805 to be formed in a self-aligned manner such that openings 805 on one side of fins 110A-C have a larger lateral dimension (e.g., exceeding some predetermined threshold) with openings 805 on another side of fins 110A-C have a smaller lateral dimension (e.g., below some predetermined threshold). Openings 805 may be etched to any depth. However, in the exemplary embodiment openings 805 are etched to a depth just sufficient to expose a predetermined sidewall height of fins 110A-C.

With the fin sidewalls exposed, any desired processing may be performed to prepare the exposed fin portion for subsequent formation of a terminal interconnect. For example, where the exposed fin portion is to be a drain or source of a transistor, the exposed portion of the fin(s) may be impurity doped, replaced with epitaxial material, or the like, according to any technique known to be suitable. In the example illustrated in FIG. 9 where the exposed portion of the fin is to be a transistor channel, gate dielectric 211 is deposited, or otherwise formed, according to any techniques known to be suitable for the gate dielectric composition. Once the fin sidewall has been prepared, terminal interconnect metallization may be deposited into the openings. In the example illustrated in FIG. 9, work function metal 272 is deposited over gate dielectric 211. As shown, work function metal 272 is deposited to a thickness such that work function metal portion 272C substantially fills the smaller (sub threshold) openings 805 on one side of fin 110. Within larger openings 805 on the opposite side of the fins, function metal 272 is deposited on sidewalls of fins 110A-C. As shown, a conformal deposition process (e.g., CVD, ALD, etc.) may be employed to deposit work function metal 272. The lateral dimension of larger openings 805 is sufficient for a nominal thickness of work function metal to be deposited at a bottom of the openings with work function metal portions 272A each having a sidewall thicknesses T4, the sum of which is smaller than the sum of Tl and T3. Terminal interconnect metallization then continues with formation of a conductive via to an underlying metallization layer and/or device. FIG. 10 illustrates a structure 1001 that includes structure 901 with the addition of via openings. In some embodiments, work function metal 272 is etched with a maskless (e.g.,“self-aligned”) anisotropic etch suitable for forming conductive spacers from work function metal portions 272A and 272B. Upon etching through the target thickness of work function metal, a portion of dielectric material 190 is exposed at a bottom of those openings 805 which had sufficient lateral width. Any suitable dielectric etch may then be performed, for example to etch via openings 1050A,

1050B and 1050C into dielectric material 190 to a sufficient depth to land on interconnect metallization 277 (and/or an underlying device terminal).

FIG. 11 illustrates structures 103 that include structure 1001 with the addition of conductive vias. A metal fill process is performed, which substantially backfills the via openings 1050A-C, electrically coupling the terminal with an underlying device. Structures 103 have substantially the same features introduced above (e.g., in the context of FIG. 1).

Any deposition process, plating process, etc. may be employed to forming interconnect fill metallization within openings 805. Structures 103 are then ready to continue through any desired downstream processing.

FIG. 12 illustrates a mobile computing platform and a data server machine employing a processor 1250 including stacked device circuitry with asymmetrical terminal

interconnects, for example as described elsewhere herein. The server machine 1206 may be any commercial server, for example including any number of high-performance computing platforms disposed within a rack and networked together for electronic data processing. The mobile computing platform 1205 may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, the mobile computing platform 1205 may be any of a tablet, a smart phone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), a chip-level or package-level integrated system 1210, and a battery 1215.

Disposed within the integrated system 1210, a substrate 1260 includes stacked processor circuitry 1240 (e.g., a microprocessor, a multi-core microprocessor, graphics processor, or the like). The stacked circuitry may include vertically stacked transistors with asymmetric terminal interconnects, for example as described elsewhere herein. For monolithic embodiments, substrate 1260 is a semiconductor chip. For other embodiments, substrate 1260 may be any package substrate, or an interposer. Processor circuitry 1240, or a separate RFIC chip may be further coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 1302.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.

FIG. 13 is a functional block diagram of an electronic computing device 1300, in accordance with some embodiments. Computing device 1300 may be found inside platform 1205 or server machine 1206, for example. Device 1300 further includes a motherboard 1302 hosting a number of components, such as, but not limited to, a processor 1304 (e.g., an applications processor), which may further incorporate asymmetric terminal interconnects, for example in accordance with embodiments described herein. Processor 1304 may be physically and/or electrically coupled to motherboard 1302. In some examples, processor 1304 includes an integrated circuit die packaged within the processor 1304. In general, the term“processor” or“microprocessor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be further stored in registers and/or memory.

In various examples, one or more communication chips 1306 may also be physically and/or electrically coupled to the motherboard 1302. In further implementations,

communication chips 1306 may be part of processor 1304. Depending on its applications, computing device 1300 may include other components that may or may not be physically and electrically coupled to motherboard 1302. These other components include, but are not limited to, volatile memory (e.g., MRAM 1330, DRAM 1332), non-volatile memory (e.g., ROM 1335), flash memory, a graphics processor 1322, a digital signal processor, a crypto processor, a chipset, an antenna 1325, touchscreen display 1315, touchscreen controller 1375, battery 1310, audio codec, video codec, power amplifier 1321, global positioning system (GPS) device 1340, compass 1345, accelerometer, gyroscope, audio speaker 1320, camera 1341, and mass storage device (such as hard disk drive, solid-state drive (SSD), compact disk (CD), digital versatile disk (DVD), and so forth), or the like.

Communication chips 1306 may enable wireless communications for the transfer of data to and from the computing device 1300. The term“wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communication chips 1306 may implement any of a number of wireless standards or protocols, including but not limited to those described elsewhere herein. As discussed, computing device 1300 may include a plurality of communication chips 1306. For example, a first communication chip may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer-range wireless

communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

While certain features set forth herein have been described with reference to various implementations, this description is not intended to be construed in a limiting sense. Hence, various modifications of the implementations described herein, as well as other

implementations, which are apparent to persons skilled in the art to which the present disclosure pertains are deemed to he within the spirit and scope of the present disclosure.

It will be recognized that principles of the disclosure are not limited to the embodiments so described, but can be practiced with modification and alteration without departing from the scope of the appended claims. For example the above embodiments may include specific combinations of features as further provided below.

However, the above embodiments are not limited in this regard and, in various implementations, the above embodiments may include the undertaking only a subset of such features, undertaking a different order of such features, undertaking a different combination of such features, and/or undertaking additional features than those features explicitly listed. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.