TECHNICAL FIELD

[0001] The present disclosure relates generally to communications, and more particularly to communication methods and related devices and nodes supporting wireless communications.

BACKGROUND

[0002] A cell-free network is a distributed network in which joint signal processing is used over many access points (APs) or base stations (BSs) to serve users. In Cell free networks, access points (APs) are distributed over a large area. Consequently, in such networks, when a transceiver (TR) pair aims at exchanging information in a bidirectional manner with high data- rates, the end-to-end channels between TRs turn out to be multi-tap. This is due to the fact that the signals received at TRs through different APs experience different propagation delays. Such networks, called asynchronous Cell free networks, should deal with an inter-symbol interference (ISI) problem.

[0003] Bidirectional communications, also known as Two-way relaying, has been studied widely in different research contexts. (See for example, [1] R. Rahimi and S. Shahbazpanahi, "Asynchronous Two-Way MIMO Relaying: A Multi-Relay Scenario," in IEEE Transactions on Wireless Communications, vol. 17, no. 7, pp. 4270-4287, July 2018, doi:

10.1109/TWC.2018.2822274 and [2] S. Kiani, S. ShahbazPanahi, M. Dong and G. Boudreau, "Power-Optimal Distributed Beamforming for Multi-Carrier Asynchronous Bidirectional Relay Networks," in IEEE Transactions on Signal and Information Processing over Networks, vol. 7, pp. 114-129, 2021, doi: 10.1109/TSIPN.2020.3044962. Commonly, bidirectional communications systems adopt multiple access and broadcast (MABC) protocol, a two-phase protocol, for information exchange between a TR pair. Based on MABC protocol, in the first phase of communications, i.e., the multiple access (MA) phase, the TRs at both ends of communications link simultaneously send their signals to APs, or relays. Then APs, transmit the processed version of their received signals towards the TRs in the second phase of communications, i.e., broadcast (BC) phase.

[0004] Conventionally, APs use decode-and-forward (DF) or amplify-and-forward (AF) strategies for interchanging information between TRs. Employing the DF method, the received signals at APs are first decoded for exploring the errors, and then encoded again to be broadcasted towards the TRs. In AF scheme, the received signals at APs are amplified and phase-shifted before broadcasted to TRs. Compared to the DF technique, the AF methods burden lower computational complexity on APs, and therefore, are more appealing in practical systems.

[0005] Employing multiple antennas at APs, AF strategy has been considered to mitigate the ISI (inter-symbol-interference) effect in asynchronous bidirectional networks [1]. The solution proposed in [1] considers block wise single-carrier communications, where a cyclic prefix (CP) is used to eliminate the ISI effect between successive information blocks. To remove the intra- block interference, the beamforming (BF) matrices at APs and the transmit powers of TRs are found through an optimization problem aiming at minimizing the total consumed power in the network under constraints on the data-rates of TRs. Using OFDM (orthogonal frequency division multiplexing) modulation at TRs, total power minimization problem subject to constraints on TRs’ data-rates has been considered in [2] for multi-carrier bidirectional communications; however, information exchange between TRs are performed vis single- antenna APs in [2].

[0006] There currently exist certain challenge(s). The existing schemes in the context of asynchronous bidirectional communications can be divided into single-carrier and multi-carrier systems. However, there is no method which is applicable to both the single-carrier and multicarrier modulation. The existing solutions for mitigating ISI either are only applicable to singlecarrier setups [1] or are just suitable for multi-carrier systems [2].

SUMMARY

[0007] Certain aspects of the disclosure and their embodiments may provide solutions to these or other challenges. In various embodiments of inventive concepts, a bidirectional communication method between at least two single-antenna TRs in an asynchronous cell-free network is provided, which is applicable to both the single-carrier and multi-carrier systems having APs that enables the information exchange between TRs employ multiple antennas. In order to restrain the ISI effect, a CP assisted block transmission is adopted. Employing the CP, it is still required to deal with the intra-block interference resulting from ISI. Therefore, the joint pre- and post-channel equalizers at both the TRs are considered to mitigate the impact of intra- block interference. Employing an AF technique at the APs and power control at TRs, the optimal structures of equalizers, the BF gains of APs, and the transmit powers of TRs are found through an optimization problem which aims at minimizing the total consumed power in the network while guaranteeing predefined data rates at TRs. The optimization problem is computationally prohibitive; therefore, to be able to find a cost efficient solution, it is assumed that the BF matrices at APs should be symmetric. Under this assumption, a semi closed-form solution for the optimization problem is achieved. Based on the resulting solution, for optimality, only a synchronous subset of the APs should participate in the communication process. Furthermore, to have the optimum performance the pre-equalizer matrices should be unitary and the postequalizer matrices should be invertible.

[0008] According to some embodiments of inventive concepts, a method to minimize a total transmit power in a bidirectional asynchronous cell free network where at least two transceivers, TRs, exchange their information using a number of amplify and forward, AF, based access points, APs, the total transmit power subject to quality of service, QoS constraints on data-rates of the TRs is provided. The method includes estimating channels between the at least two TRs and the AF-based APs. The method further includes calculating a total power consumption for each channel tap. The method further includes determining a single non-zero channel tap which results in a lowest total power consumption. The method further includes based on the single non-zero channel tap determined: calculating beamforming matrices for the APs; calculating a total power transmission of each transceiver of the at least two transceivers; calculating precoding matrices at each transceiver of the at least two transceivers; and calculating postchannel equalizers at the at least two transceivers.

[0009] Analogous transceiver devices , computer program, and computer program products are also provided.

[0010] Certain embodiments may provide one or more of the following technical advantage(s). By employing pre- and post-channel equalizers at both the TRs, various embodiments are applicable to both the multi-carrier and single-carrier systems. The embodiments described herein minimize the average total power consumed in the network subject to the quality of service (QoS) constraints on the TRs’ date rates. Considering symmetric BF matrices at APs, and devising a dimensionality reduction procedure, optimal BF matrices of APs and transmit powers of TRs are found by means of a simple and fast algorithm.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate certain non-limiting embodiments of inventive concepts. In the drawings: [0012] Figure 1 is a graph illustrating a comparison between the various embodiments of a current method according to some embodiments of inventive concepts and a prior method;

[0013] Figure 2 is a block diagram illustrating a asynchronous bidirectional Cell free network according to some embodiments of inventive concepts;

[0014] Figure 3 is a block diagram illustrating a structure of a transceiver according to some embodiments of inventive concepts;

[0015] Figure 4 is a block diagram illustrating a structure of a first transceiver according to some embodiments of inventive concepts;

[0016] Figure 5 is a block diagram illustrating a structure of a second transceiver according to some embodiments of inventive concepts;

[0017] Figure 6 is a graph illustrating an average total transmit power versus number of antennas per AP according to some embodiments of inventive concepts;

[0018] Figure 7 is a block diagram illustrating a structure of a first transceiver in a singlecarrier implementation according to some embodiments of inventive concepts;

[0019] Figure 8 is a block diagram illustrating a structure of a second transceiver in a singlecarrier implementation according to some embodiments of inventive concepts;

[0020] Figure 9 is a block diagram illustrating a structure of a first transceiver in a multicarrier implementation according to some embodiments of inventive concepts;

[0021] Figure 10 is a block diagram illustrating a structure of a second transceiver in a multi-carrier implementation according to some embodiments of inventive concepts;

[0022] Figure 11 is a flow chart illustrating operations of a transceiver according to some embodiments of inventive concepts.

DETAILED DESCRIPTION

[0023] Some of the embodiments contemplated herein will now be described more fully with reference to the accompanying drawings. Embodiments are provided by way of example to convey the scope of the subject matter to those skilled in the art, in which examples of embodiments of inventive concepts are shown. Inventive concepts may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of present inventive concepts to those skilled in the art. It should also be noted that these embodiments are not mutually exclusive. Components from one embodiment may be tacitly assumed to be present/used in another embodiment. [0024] As previously indicated, in various embodiments of inventive concepts, a bidirectional communication method between at least two single-antenna TRs in an asynchronous cell-free network is provided, which is applicable to both the single-carrier and multi-carrier systems having APs that enables the information exchange between TRs employ multiple antennas.

[0025] As illustrated in Figure 1, applying multi-antenna APs, the various embodiments of inventive concepts offers a cell free network with lower total power consumption compared to the existing networks. Consequently, the various embodiments described herein provide a step forward towards the feasibility of the green communications systems. In addition, the pre- and post-channel equalizers at the TRs brings about the applicability of the proposed method in both the single-carrier and multi-carrier networks. The various embodiments take into account different delays corresponding to distinct end-to-end available paths between the TRs, and enables asynchronous wireless communications in practical systems. Unknown parameters of the network are designed based on a semi-closed form solution which is computationally efficient and very fast. Furthermore, the various embodiments described herein are easily applicable to massive antenna systems.

[0026] Figure 2 illustrates an example of an asynchronous bidirectional Cell free network 20 in which various embodiments of the inventive concepts may be implemented. Figure 2 shows two transceivers 202 designated as TR1 and TR2. The transceivers may be single antenna transceivers or multiple antenna receivers. While two transceivers 202 are shown, in other embodiments, there are more than two transceivers 202. Figure 2 also has a number L of multi- antenna APs 204 where each AP 204 employs M antennas. There are no direct links between transceivers 202.

[0027] In the system of Figure 2, channels between TRs 202 and APs 204 are assumed to be frequency-flat. As both the uplink and the downlink transmissions take place at the same frequency, channel reciprocity can be utilized for estimating the channel state information (CSI) at APs 204 using the uplink training signals transmitted by the TRs 202. Estimated CSI at APs 204 then is fed back to the TRs 202. Thus, we assume that the perfect CSI is available at both the TRs 203 and the APs 204.

[0028] In Figure 2, τ _l1 represents the propagation delay between TRI and APl, while τ _l2 denotes the propagation delay between TR2 and AP/. Also, shown in Figure 2, g _l1 represents the channel gain vector between TRI and APl, while g _l2 denotes the channel gain vector between TR2 and APl. Both g _l1 and g _l2 are of size Mx1. [0029] Since APs are distributed over a relatively large area the channels between each TR and APs may have different propagation delays. For instance, in Figure 2, it is possible to have for TR2. According to the channel reciprocity, the end-to-end propagation delay between TRI and TR2 through AP/ is defined as . Since r ₍ may have different values for different APs, the end-to-end channels between TRI and TR2 can be modeled as a multi-tap channel. Without loss of generality, one can assume that the AP indices are sorted based on their corresponding end-to-end path delays in an ascending order. That is, τ ₁ ≤ ₂ ≤ ••• ≤ τ _L . Based on this assumption, the discrete-time end- to-end multi-tap channel length is defined as (1) and the AP indices can be partitioned into L _c different clusters as follows where T _s is the symbol period. In fact, C _n+1 , defined above, contains the indices of those APs which contribute to the n-th tap of the end-to-end channel impulse responses (CIRs) between TRI and TR2. Note that each AP contributes to only one channel tap, and if none of the APs ontribute to the n-th tap of the end-to-end CIRs then we have C _n+1 = ø .

[0030] Figure 3 is a block diagram illustrating elements of a transceiver device 202 (also referred to as a network node, etc.) configured to provide cellular communication according to embodiments of inventive concepts. As shown, the transceiver device 202 may include transceiver circuitry 301 (also referred to as a transceiver) including a transmitter and a receiver configured to provide uplink and downlink radio communications with mobile terminals. The RAN node may include network interface circuitry 307 (also referred to as a network interface) configured to provide communications with other nodes (e.g., with other transceivers and access points) of the cell free network 200. The transceiver device 202 may also include processing circuitry 303 (also referred to as a processor) coupled to the transceiver circuitry, and memory circuitry 305 (also referred to as memory) coupled to the processing circuitry. The memory circuitry 305 may include computer readable program code that when executed by the processing circuitry 303 causes the processing circuitry to perform operations according to embodiments disclosed herein. According to other embodiments, processing circuitry 303 may be defined to include memory so that a separate memory circuitry is not required. The transceiver device in other embodiments may be implemented in a virtual environment (e.g., a cloud network) where various modules distributed across the environment performs various operations of the transceiver device 202.

[0031] As discussed herein, operations of the transceiver device 202 may be performed by processing circuitry 303, network interface 307, and/or transceiver 301. For example, processing circuitry 303 may control transceiver 301 to transmit downlink communications through transceiver 301 over a radio interface to one or more access points and/or to receive uplink communications through transceiver 301 from one or more access points over a radio interface. Similarly, processing circuitry 303 may control network interface 307 to transmit communications through network interface 307 to one or more other access points and/or to receive communications through network interface from one or more other access points. Moreover, modules may be stored in memory 305, and these modules may provide instructions so that when instructions of a module are executed by processing circuitry 303, processing circuitry 303 performs respective operations (e.g., operations discussed below with respect to Example Embodiments relating to transceiver devices). According to some embodiments, transceiver device 202 and/or an element(s)/function(s) thereof may be embodied as a virtual node/nodes and/or a virtual machine/machines.

[0032] TR structures

[0033] Because the end-to-end channels between TRs are multi-path, inter-symbol- interference (ISI) may have to be dealt with. In order to restrain the ISI effect, the Cyclic Prefix (CP) assisted block transmission of the information symbols can be used. The CP’s length should be greater than or equal to L _c , defined above. Besides utilizing CP, pre- and post-channel equalizer blocks are also employed in various embodiments at both the TRs to mitigate the ISI effect. Structures of the pre- and post-channel equalizers have direct impacts on the achievable data rates of TRs. In addition to the pre- and post-channel equalizers, the achievable data rates of TRs are determined by the BF matrices of APs and the transmit powers of TRs.

[0034] The detailed structure of the TRs is some embodiments are illustrated in Figure 4 and Figure 5. Depicted in these figures, at each transmitter branch of the TRs, the input stream 400 is first passed through source coder 402 and channel coder 404 to be coded. In the next step, the output stream of channel coder 404 enters a serial-to-parallel conversion block 406 (denoted as "S/P") thereby constructing a vector of data symbols containing Ns symbols. Then, to perform the pre-equalization, input data blocks to TRI and TR2 are multiplied by Nsx Ns preequalization matrices 408 (e.g., El and E2, respectively). The output of the pre-equalizer blocks 408 then are passed through CP-insertion block (represented by T _cp ) 410. After CP insertion, the signal block goes through a parallel-to-serial conversion block 412 (denoted as "P/S") and is converted to a block of serial symbols. At the final step, before being transmitted by TRI and TR2, signals are multiplied by pl and p2, respectively

[0035] As illustrated in Figure 4 and Figure 5, at the receiver branch of each TR, the received signal samples are passed through a serial-to-parallel ("S/P") conversion block 414 to form a signal block of length Ns. Then, self-interference (SI) terms are subtracted from the received signals using the self-interference-cancellation (SIC) blocks 416. In the next step, the CPs of the received signals are removed by R _cp (cyclic prefix removal) blocks 418. After CP elimination, in order to estimate the received data, TRI and TR2, respectively, multiply their received signals by the post-channel equalizer matrices 420 (e.g., Fl and F2). At the final step, the output of post-channel equalizer 420 is passed through the post-channel equalizer 422 and post-source equalizer 424 to produce output signals 426.

[0036] Network planning recommendation

[0037] For a fix total number of antennas available in the network, i.e., M X L = cte, there is an optimal number of antennas per AP, resulting in the best performance in terms of the least power consumption in the network. This optimal number is the consequence of a tradeoff between the BF gain and the diversity gain. Choosing large values for M results in small numbers of APs, and consequently lowers the spatial diversity gain. Conversely, small values of M turn into high values of spatial diversity gain and low values for BF gain. For relatively long distances between TRs the effect of diversity gain becomes dominant. This is due to the fact that distribution of a relatively large number of APs in the coverage area can, on average, decrease the distance of TRs from the closest AP. When TRs are relatively located close to each other BF gain becomes more advantageous than spatial diversity gain. This tradeoff is illustrated in Figure 6.

[0038] In order to optimize figures of merit such as network throughput or consumed power of the network, the BF matrices, pre- and post-channel equalizers and TRs’ transmit powers should be taken into account. The optimal solution for the figures of merit is achieved when only a synchronous subset of APs is selected and the remainder of the APs do not take part in information exchange between TRs. In other words, at the optimum, only a subset of APs who contribute to the best tap of the end-to-end channel should be active. Thus, to have the best performance the end-to-end multi-tap channels between TRs should turn to a reciprocal single- tap channel. To find the best channel tap and the associated optimum TRs’ transmit power, the optimal structures of equalizers and BF matrices, one can consider the network consumed power minimization problem.

[0039] Power Minimization

[0040] In this problem, we aim at minimizing the total transmit power subject to the quality of service (QoS) constraints on TRs’ data-rates in a bidirectional asynchronous cell free network where two TRs exchange their information using a number of AF-based APs. The consumed power in the proposed network is the sum of the powers transmitted by the TRs and the transmitted powers of the APs, and its average is calculated as:

[0041] In the above equation, σ ² is the AP’s noise power, and A _l , a matrix of dimension M X M, represents the BF matrix of I — th AP. In such a network, the data-rates of TRs are directly influenced by the pre- and post-equalizers’ structures, BF matrices of APs, and TRs’ transmit powers. Thus, the optimal structures of equalizers, APs’ BF matrices, and the optimal values of TRs’ transmit powers are found through solving the following optimization problem: and R ₂ are, respectively, the achievable data-rates of TR1 and TR2. Also, in (4), r _t and r ₂ denote the predefined thresholds for data-rates of TRI and TR2, respectively. In (4), constraints on the ranks of the pre- and post-equalizer matrices are considered to guarantee their invertibility.

[0042] Note that the optimization problem of equation (4) is non-convex and nonlinear.

Therefore, solving (4) can be very challenging.

[0043] Embodiment 1

[0044] In a first embodiment of solving (4), the optimization problem can be solved for an optimal solution using brute force search which is computationally intractable. Also, tolerating lower precision, heuristic methods can be used to solve (4) for suboptimal solutions.

[0045] Embodiment 2

[0046] Solving (4) without any assumption on the structure of the APs’ BF matrices can be very challenging. Therefore, in this method embodiment, an optimal solution for (4) which is computationally efficient and very fast is desirable. Towards this goal, at the first step, it is assumed that the BF matrices at APs should be symmetric. Under this assumption, the end-to- end channels between TRs become reciprocal. This, in turn, results in that the optimization problem of (4) becomes independent of the channel equalizers, and to achieve optimal solution pre-channel equalizers should be unitary matrices and post-channel equalizers should be invertible matrices. Consequently, (4) turns into an optimization problem over APs’ BF matrices and TRs’ transmit powers.

[0047] Considering symmetric BF matrices, the number of BF weights which should be designed are . Hence, when either the number of antennas at APs, i.e., M, or the number of APs, i.e., L, are large, finding weights could be computationally prohibitive. Therefore, in the next step, towards obtaining the optimal BF matrices, a dimensionality reduction procedure that replaces weights is used which should be designed to be 3 X L. Using this dimensionality reduction procedure, design steps become independent of the number of antennas employed in the APs. Consequently, the proposed method is efficiently applicable to the case when APs have a massive number of antennas.

[0048] In the description that follows, the steps of the various methods of inventive concepts are summarized by a very-high level algorithm, a high level description algorithm, and a detailed descriptive algorithm.

[0049] Very-high level

[0050] In this embodiment, the total transmit power is minimized subject to the quality of service (QoS) constraints on TRs’ data-rates in a bidirectional asynchronous cell free network where two TRs exchange their information using a number of AF-based APs. The consumed power in the network is the sum of the powers transmitted by the TRs and the transmitted powers of the Aps. The overall operations the TRs perform or that are performed on behalf of the TRs are below.

[0051] Step 1. Estimate channels between the transceivers and the APs. This operation of this step may be performed in all the algorithms.

[0052] Step 2. Calculate the total power consumption for each channel tap. (See steps 1-10 of high level description for detailed description of this step.)

[0053] Step 3. Find the single non-zero tap which results in the lowest total power consumption (See step 11 of high level description for detailed description of this step).

[0054] Step 4. Calculate the beamforming matrices for the APs (See steps 12 and 13 of high level description for detailed description of this step). 0055] Step 5. Calculate the power transmission of each transceiver (See step 14 of high level description for detailed description of this step).

[0056] Step 6. Calculate the precoding (pre-equalizer) matrices at the at least two transceivers (See step 15 of high level description for detailed description of this step)

[0057] Step 7. Calculate the post-channel equalizers at the at least two transceivers (See step 16 of high level description for detailed description of this step)

[0058] High level description

Definitions for High level description algorithm and detailed descriptive algorithm:

N _s : number of symbols per transmitted block r ₁ minimum required data rate at transceiver 1 r ₂ : minimum required data rate at transceiver 2 : the end-to-end propagation delay between TRI and TR2 through AP _l with τ ₁ ≤ τ2 ≤ ^τ 3 ≤ ... ≤ ^τ l

L _c : the discrete-time end-to-end multi-tap channel length

C _n+1 : the set of those APs (relays) which contribute to the tap n of the end-to-end channel impulse response (OR).

N : set of those tap indices to which at least one AP (relay) contributes. l _n : number of the APs (relays) which contribute to tap n of the end-to-end channel impulse response (OR). i _n : number of the APs (relays) which contribute to taps 0 to n — 1 of the end-to-end channel impulse response (OR). i' _n - number of the APs (relays) which contribute to taps n+1 to L _c — 1 of the end-to- end channel impulse response (OR). g _{l, 1} : channel vector between transceiver 1 and the l-th AP (relay) g _{l, 2} : channel vector between transceiver 2 and the l-th AP (relay)

U _l : an M X 2 matrix with orthogonal columns which spans the subspace spanned by

A _l : beamforming matrix of the l-th AP (relay) p ₁ : transmit power of transceiver 1 p ₂ : transmit power of transceiver 2 E ₁ : precoder matrix of transceiver 1

E ₂ : precoder matrix of transceiver 2

F ₁ : post-equalizer matrix of transceiver 1

F ₂ : post-equalizer matrix of transceiver 2

[0059] Initialization:

[0060] Operations

0061] detailed descriptive algorithm

[0062] Initialization

Define set 0}, as the set of indices of those taps of the end- to-end OR to which at least one relay contributes.

Define C _n+1 , based on (2), and calculate

System Embodiment 1 - Single Carrier -implementation

[0064] A single-carrier implementation of the proposed network is considered as embodiment #1. To have the optimal performance the pre-channel equalizers should be unitary matrices and post-channel equalizers should be invertible matrices. Thus, for a single-carrier implementation of the proposed system, an Identity matrix is one simple choice for both the pre- and post-channel equalizers. The detailed structures of TRI and TR2 for single-carrier implementation are depicted in Figure 7 and Figure 8, respectively.

[0065] System Embodiment 2 - Multi-Carrier implementation

[0066] A multi-carrier implementation of the network is considered as embodiment #2, and its details are illustrated in Figure 9 and Figure 10. As mentioned, pre-channel equalizers should be unitary and post-channel equalizers should be invertible matrices. Thus, for a multi-carrier implementation of the proposed system, the pre-equalizers are set to be inverse discrete Fourier transform (IDFT) matrix 900, and the post-equalizers are set to be discrete Fourier transform (DFT) matrix 902. The detailed structures of TRI and TR2 for multi-carrier implementation are depicted in Figure 9 and Figure 10, respectively.

[0067] Operations of the transceiver device 202 (implemented using the structure of the block diagram of Figure 3) will now be discussed with reference to the flow chart of Figure 11 according to some embodiments of inventive concepts. For example, modules may be stored in memory 305 of Figure 3, and these modules may provide instructions so that when the instructions of a module are executed by respective communication device processing circuitry 303, processing circuitry 303 performs respective operations of the flow chart.

[0068] Figure 11 illustrates operations the transceiver device 202 performs to minimize a total transmit power in a bidirectional asynchronous cell free network where at least two transceivers, TRs, exchange their information using a number of amplify and forward, AF, based access points, APs, the total transmit power subject to quality of service, QoS constraints on data-rates of the TRs. Turning to Figure 11, in block 1101, the processing circuitry 303 estimates channels between the at least two TRs and the AF-based APs.

[0069] In block 1103, the processing circuitry 303 calculates a total power consumption for each channel tap. In some embodiments, the processing circuitry 303 calculates the total power consumption for each channel tap by calculating the total power consumption in the network for the channel tap based on only those APs which contribute to the n-th tap of an end-to-end channel impulse response, OR, are turned on while a remainder of the APs are turned off.

[0070] In various of these embodiments, the processing circuitry 303 calculates the total power consumption by initializing variables, defining variables, and performing various calculations. For example, the processing circuitry 303 initializes variables r , r', and /i in accordance minimum required data rate at a first of the at least two TRs, TRi, r ₂ is a minimum required data rate at a second of the at least two TRs, TR2, and N _s is a number of symbols per transmitted block.

[0071] In these embodiments, the processing circuitry 303 defines set TV" = , as the set of indices of those taps of the end-to-end OR to which at least one AP contributes, wherein C _n+1 is a set of those APs which contribute to the tap n of the end-to-end OR and L _c , is a discrete-time end-to-end multi-tap channel length, L _c , as L _c = 1 + wherein r ₍ is an end-to-end propagation delay between TRI and TR2 through AP/ with τ ₁ ≤ τ ₂ ≤ τ ₃ ≤ • •• ≤ τ _l , and Ts is a symbol period.

[0072] In these embodiments, the processing circuitry 303 calculates various parameters.

The processing circuitry 303 calculates {0, 1, ••• , L _c — 1}. The processing circuitry 303 calculates in accordance with

[0073] The processing circuitry 303 defines S„(A, z) and „(z) in accordance with [0074] The processing circuitry 303 sets z _l > 0 small enough such that h _n (z _l ) < 0, and solves to find A associated to z _l . using a bisection method, as the unique positive solution to z . The processing circuitry 303 sets z _u > 0 large enough such that h _n (z _; ) > 0, and solves to find associated to z _u . using the bisection method, as the unique positive solution to

[0075] The processing circuity 303 responsive to h _n (z) < ∈, sets z = and solves to find A associated to z, and sets z _n = z and sets , wherein e determines a precision of the bisection method.

[0076] The processing circuitry 303 calculating the total power consumption in the network for the channel tap in accordance with where K _n is the total power consumption for the channel tap _n .

[0077] h _n (z) may not be < ∈. The processing circuitry 303, responsive to h _n (z) < 0: sets z _l = z, solves to find A associated to z _u , and sets z , and solves 0 to find A associated to z. The processing circuitry 303, responsive to h _n (z) > 0: sets z _u = z, solves to find A associated to z _l , sets z = , and solves to find A associated to z. This process in some embodiments repeats these operations until (z) < ∈ before proceeding to calculate the total power consumption in the network for the channel tap in accordance with

[0078] Returning to Figure 11, in block 1103, the processing circuitry 303 determines a single non-zero channel tap which results in a lowest total power consumption. Based on this single non-zero channel tap, various matrices, transceiver power transmission setting, and postchannel equalizers can be determined. In some embodiments, the processing circuitry 303 determines the single non-zero channel tap which results in a lowest total power consumption by determining the single non-zero channel tap in accordance with wherein K _n is the total power consumption for channel tap _n .

[0079] Returning to Figure 11, in block 1107, the processing circuitry 303 calculates beamforming matrices for the APs. In various embodiments, the processing circuitry 303 calculates the beamforming matrices by calculating where and reshaping a° to obtain the optimal value of the BF matrices of A _t , A ₂ , ... , A _L from a° = [vec ^T (A ₁ ) vec ^T (A ₂ ) ••• vec ^T (A _L )] ^T wherein U _l is an M X 2 matrix with orthogonal columns which spans the subspace spanned by gl,1, gl,2 wherein the at least two TRs comprise two TRs, g _{l, 1} is a channel vector between TR1 and the Z-th AP, and g _{( 2} is ^a channel vector between TR2 and the l-th AP as described above.

[0080] In some of these embodiments, the processing circuitry 303 determines U _l in accordance with

[0081] Returning to Figure 11, in block 1109, the processing circuitry calculates a total power transmission of each transceiver of the at least two transceivers. In various embodiments, the processing circuitry 303 calculates the total power transmission of each transceiver by calculating the total power transmission in accordance with where s the total power transmission of TRI and pi is the total power transmission of TR2.

[0082] In block 1111, the processing circuitry 303 calculates precoding matrices at each transceiver of the at least two transceivers. In various embodiments, the processing circuitry 303 calculates the precoding matrices at each transceiver by selecting precoding matrices E _1; E ₂ to be any two unitary matrices, wherein E ₁ is a precoder matrix of a first transceiver, TR1, of the at least two transceivers TR1 and E ₂ is a precoder matrix of a second transceiver, TR2, of the at least two transceivers.

[0083] In block 1113, the processing circuitry 303 calculates post-channel equalizers at the at least two transceivers. In various embodiments, the processing circuitry 303 calculates postchannel equalizers at the at least two transceivers by selecting F ₁ = , F ₂ = , wherein F ₁ is a post-equalizer matrix of TRI and F ₂ is a post-equalizer matrix of TR2.

[0084] Various operations from the flow chart of Figure 11 may be optional with respect to some embodiments of transceiver devices and related methods. Regarding methods of example embodiment 1 (set forth below), for example, operations of block 1101 of Figure 11 may be optional.

[0085] Although the computing devices described herein (e.g., transceiver devices, access points, etc.) may include the illustrated combination of hardware components, other embodiments may comprise computing devices with different combinations of components. It is to be understood that these computing devices may comprise any suitable combination of hardware and/or software needed to perform the tasks, features, functions and methods disclosed herein. Determining, calculating, obtaining or similar operations described herein may be performed by processing circuitry, which may process information by, for example, converting the obtained information into other information, comparing the obtained information or converted information to information stored in the network node, and/or performing one or more operations based on the obtained information or converted information, and as a result of said processing making a determination. Moreover, while components are depicted as single boxes located within a larger box, or nested within multiple boxes, in practice, computing devices may comprise multiple different physical components that make up a single illustrated component, and functionality may be partitioned between separate components. For example, a communication interface may be configured to include any of the components described herein, and/or the functionality of the components may be partitioned between the processing circuitry and the communication interface. In another example, non-computationally intensive functions of any of such components may be implemented in software or firmware and computationally intensive functions may be implemented in hardware.

[0086] In certain embodiments, some or all of the functionality described herein may be provided by processing circuitry executing instructions stored on in memory, which in certain embodiments may be a computer program product in the form of a non-transitory computer- readable storage medium. In alternative embodiments, some or all of the functionality may be provided by the processing circuitry without executing instructions stored on a separate or discrete device-readable storage medium, such as in a hard-wired manner. In any of those particular embodiments, whether executing instructions stored on a non-transitory computer- readable storage medium or not, the processing circuitry can be configured to perform the described functionality. The benefits provided by such functionality are not limited to the processing circuitry alone or to other components of the computing device, but are enjoyed by the computing device as a whole, and/or by end users and a wireless network generally.

[0087] Further definitions and embodiments are discussed below.

[0088] In the above-description of various embodiments of present inventive concepts, it is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of present inventive concepts. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which present inventive concepts belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0089] When an element is referred to as being "connected", "coupled", "responsive", or variants thereof to another element, it can be directly connected, coupled, or responsive to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected", "directly coupled", "directly responsive", or variants thereof to another element, there are no intervening elements present. Like numbers refer to like elements throughout. Furthermore, "coupled", "connected", "responsive", or variants thereof as used herein may include wirelessly coupled, connected, or responsive. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Well-known functions or constructions may not be described in detail for brevity and/or clarity. The term "and/or" (abbreviated “/”) includes any and all combinations of one or more of the associated listed items.

[0090] It will be understood that although the terms first, second, third, etc. may be used herein to describe various elements/operations, these elements/operations should not be limited by these terms. These terms are only used to distinguish one element/operation from another element/operation. Thus, a first element/operation in some embodiments could be termed a second element/operation in other embodiments without departing from the teachings of present inventive concepts. The same reference numerals or the same reference designators denote the same or similar elements throughout the specification.

[0091] As used herein, the terms "comprise", "comprising", "comprises", "include", "including", "includes", "have", "has", "having", or variants thereof are open-ended, and include one or more stated features, integers, elements, steps, components or functions but does not preclude the presence or addition of one or more other features, integers, elements, steps, components, functions or groups thereof. Furthermore, as used herein, the common abbreviation "e.g.", which derives from the Latin phrase "exempli gratia," may be used to introduce or specify a general example or examples of a previously mentioned item, and is not intended to be limiting of such item. The common abbreviation "i.e.", which derives from the Latin phrase "id est," may be used to specify a particular item from a more general recitation.

[0092] Example embodiments are described herein with reference to block diagrams and/or flowchart illustrations of computer-implemented methods, apparatus (systems and/or devices) and/or computer program products. It is understood that a block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by computer program instructions that are performed by one or more computer circuits. These computer program instructions may be provided to a processor circuit of a general purpose computer circuit, special purpose computer circuit, and/or other programmable data processing circuit to produce a machine, such that the instructions, which execute via the processor of the computer and/or other programmable data processing apparatus, transform and control transistors, values stored in memory locations, and other hardware components within such circuitry to implement the functions/acts specified in the block diagrams and/or flowchart block or blocks, and thereby create means (functionality) and/or structure for implementing the functions/acts specified in the block diagrams and/or flowchart block(s).

[0093] These computer program instructions may also be stored in a tangible computer- readable medium that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable medium produce an article of manufacture including instructions which implement the functions/acts specified in the block diagrams and/or flowchart block or blocks. Accordingly, embodiments of present inventive concepts may be embodied in hardware and/or in software (including firmware, resident software, micro-code, etc.) that runs on a processor such as a digital signal processor, which may collectively be referred to as "circuitry," "a module" or variants thereof.

[0094] It should also be noted that in some alternate implementations, the functions/acts noted in the blocks may occur out of the order noted in the flowcharts. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved. Moreover, the functionality of a given block of the flowcharts and/or block diagrams may be separated into multiple blocks and/or the functionality of two or more blocks of the flowcharts and/or block diagrams may be at least partially integrated. Finally, other blocks may be added/inserted between the blocks that are illustrated, and/or blocks/operations may be omitted without departing from the scope of inventive concepts. Moreover, although some of the diagrams include arrows on communication paths to show a primary direction of communication, it is to be understood that communication may occur in the opposite direction to the depicted arrows.

[0095] Many variations and modifications can be made to the embodiments without substantially departing from the principles of the present inventive concepts. All such variations and modifications are intended to be included herein within the scope of present inventive concepts. Accordingly, the above disclosed subject matter is to be considered illustrative, and not restrictive, and the examples of embodiments are intended to cover all such modifications, enhancements, and other embodiments, which fall within the spirit and scope of present inventive concepts. Thus, to the maximum extent allowed by law, the scope of present inventive concepts are to be determined by the broadest permissible interpretation of the present disclosure including the examples of embodiments and their equivalents, and shall not be restricted or limited by the foregoing detailed description.