Field of the Invention

This invention relates to the field of optical devices and sub-systems. In particular embodiments of the invention, a device is suitable for use as a 3R optical regenerator that can operate asynchronously and in burst mode.

Background to the Invention

It is known that there are optoelectronic techniques available to perform the function of optical regeneration for 3R (Re-shaping, Re-amplifying and Re-timing) regeneration. For example, US patent 6,570,694 (Yegnanarayanan) discloses the use of multiple wavelength clock signals and US patent 5,831,752 (Cotter et al) discloses the use of marker pulses within a data stream to derive an optical clock. However, in both of these cases optical to electrical conversion is required to determine which of the sampled versions of the data is correctly synchronised to the local clock. Once this has been determined electronically, the correct version of the regenerated data is electronically switched. This presents a significant limitation to the operating speeds available for the regeneration which is limited by the speed of the electronics, and furthermore introduces a latency to the transmission of the optical packets.

An object of this invention, at least in its preferred embodiments, is to enable all-optical 3 R regeneration of data without the need to extract a clock signal out of the data and do

away with the electronic processing of the regenerated data to determine the correct synchronisation.

Summary of the Invention Viewed from a first aspect, this invention provides an optical device comprising: a common data input for receiving input data to the device; a first local clock input for receiving a first local clock signal; a first optical logic gate having a clock input and at least a first data input; and a second optical logic gate having a clock input and at least a first data input, wherein the data inputs of the first and second optical logic gates are each arranged to receive data from the common data input and the clock inputs of the first and second optical logic gates are each arranged to receive a clock signal from the first local clock input, whereby the output of each optical logic gate, in use, is the input signal retimed to the first local clock signal, and wherein the device further comprises a third optical logic gate arranged to receive the output of the first and second optical logic gates and to output 3R regenerated data corresponding to the input signal.

The data input(s) of the second optical logic gate may be connected to the common data input via a delay. Each of the first and second optical logic gates may have a first data input and a second data input. Each such data input may be arranged to receive data from the common data input. The second data input may be delayed relative to the first data input. In this way, the optical logic gate defines a switching window. The switching window may be substantially half the nominal bit period of the input data.

The clock input of the second optical logic gate may be connected to the first local clock input via a delay. The relative delays at the inputs of the first and second optical logic gates may be configured such that only one of the optical logic gates switches at any given time.

The bit period of the first local clock signal may be equal to the nominal bit period of the input data.

The third optical logic gate may have a clock input arranged to receive a clock signal from a second clock input at a different wavelength to the first local clock signal.

The third optical logic gate may be an exclusive OR gate. Alternatively, the third optical logic gate may be an AND gate. In this case, the output of the first optical logic gate may be delayed relative to the output of the second optical logic gate such that the resulting signals are substantially time coincident.

The first and second optical logic gates may be Mach Zehnder optical logic gates. The third optical logic gate may be a Mach Zehnder optical logic gate.

The optical logic gates may be formed using the hybrid integration of semiconductor optical amplifiers and passive planar waveguides.

Viewed from a broad aspect, the invention provides a device using multiple optical logic elements to perform the function of all-optical 3 R asynchronous burst mode regeneration. In this device, an optical XOR gate may be used to combine the output of two Mach- Zehnder optical logic gates.

The outputs of two Mach-Zehnder optical logic gates may be combined using appropriate delay lines to bring them into time coincidence.

The logic elements may be formed using the hybrid integration of semiconductor optical amplifiers and passive planar waveguides.

Brief Description of the Drawings

An embodiment of the invention will now be described by way of example only and with reference to the accompanying drawings, in which:

Figure 1 is a schematic representation of an asynchronous regenerator according to a first embodiment of the invention; and

Figure 2 is a schematic representation of an asynchronous regenerator according to a second embodiment of the invention.

Detailed Description of Particular Embodiments Figure 1 shows an optical regenerator according to an embodiment of the invention. The device is in two parts. The first part consists of two optical logic gates Gl, G2 in parallel which enable asynchronous retiming off a local clock 5. Only one of these parallel gates will operate depending on the relative position of the data pulse in the optical window defined by the passive waveguide delay circuit 9 at the input to the gates. The output from both of these gates is then passed through a second stage device which performs an optical XOR operation on the regenerated data. The complete device is capable of operating at speeds of 40Gbit/s or more.

The first stage of the burst mode regenerator comprises two logic gates Gl, G2 in parallel with different time delays 9 at the input to each gate. The gates consist of passive planar waveguide Mach Zehnder interferometers 3 with semiconductor optical amplifiers 1 in each arm. The time delays 9 are defined in the passive waveguide layer. The switching windows to the gates are defined by the time delays on the input to the gates and the relative position of the switching window for each gate is determined by the input delay.

In the first embodiment, the device consists of two optical logic gates Gl, G2 in parallel followed by an optical XOR gate. These logic gates consist of non-linear semiconductor optical amplifiers (SOAs) 1 hybridly integrated with passive planar silica waveguides structures 2. The input data 4 is split using the passive waveguide circuitry and an equal portion of the split data is fed into each Hybrid Mach Zehnder Interferometer (HMZI) logic gate 3 with an appropriate time delay introduced at the input to the HMZI 2.

A local laser source 5, known as a clock source, produces a train of pulses at the appropriate data rate. This local clock 5 is equally split and one portion delayed relative to the other and also relative to the data input 4 using the passive waveguide structures 2. Figure 1 shows the first stage of the regenerator with the local clock source 5 and the timing relationship of the clock to the two logic gates Gl, G2. These relative delays 9 are arranged such that there is only one copy of the clock pulse present in one of the logic

gates Gl, G2 at any one time, and therefore only one output from the logic gates 3 at any one time. This output is a regenerated version of the input data. The effect of jitter on the data is to move the relative position of the switching windows of the logic gates Gl ₅ G2. This has the effect of moving the switching window over the clock pulse which determines which gate Gl , G2 provides the regenerated output. In this way there is only one gate with a switched clock at any one time.

Since we do not know which gate Gl , G2 has switched at any particular time, we need to perform the logical XOR operation on the output from the two gates Gl, G2. The truth table for this operation is described in table 1.

A B A G

0 0 0

0 1 1

1 0 1

1 1 0

Table 1. XOR truth table

The optical XOR device is shown in Figure 1 and consists of a HMZI 3 with the appropriate planar silica waveguide circuitry at the input and another local optical source 6 which is at a different wavelength to the first local optical clock 5. This device is an optical XOR gate with a local clock at a different wavelength from the first stage clock denoted as λ ₂ . The output 10 of the XOR is the fully 3R regenerated data transposed on to the wavelength of the source 6. The first and second stages of the device are fully integrated in the regenerator as shown in Figure 1.

In this embodiment, there is the potential for both gates Gl, G2 to switch at the same time if the jitter on the data exceeds half the bit period B or if the relative position of the switching windows of the logic gates Gl, G2 is such that the extremes of the windows are coincident with the position of the clock pulse. Whilst these situations are unlikely, they

are possible. In such cases, the XOR gate may not be the appropriate second stage device in the regenerator and the second embodiment would be the preferred option.

Figure 2 shows a second embodiment of the invention with an alternative output arrangement instead of the output XOR gate. In the second embodiment, shown in Figure 2, the output XOR gate is replaced with a delay line 7 to bring the output pulses from the first stage into time coincidence or near time coincidence (Δt > pulse- width), a saturating SOA 1 to ensure equal optical amplitudes from the gates, and another logic gate G3 to perform the logical AND operation.

In summary, an optical device comprises a common data input 4 for receiving input data to the device and a local clock input 5 for receiving a local clock signal. The devices includes two optical logic gates Gl, G2 having respective clock inputs respective data inputs. The data inputs of the first and second optical logic gates Gl, G2 are each arranged to receive data from the common data input 4 and the clock inputs of the first and second optical logic gates Gl, G2 are each arranged to receive a clock signal from the local clock input 5. In this way, the output of each optical logic gate Gl, G2 is the input signal retimed to the local clock signal. The device further comprises a third optical logic gate XOR arranged to receive the output of the first and second optical logic gates and to output 3R regenerated data corresponding to the input signal.