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AUDIBLE NOISE REDUCTION FOR SINGLE CURRENT SHUNT PLATFORM

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit and priority of U.S. Provisional patent application Serial No. 60/895,801 filed March 20, 2007 entitled AUDIBLE NOISE REDUCTION FOR SINGLE CURRENT SHUNT PLATFORM, the entire disclosure of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] The invention relates to a method and apparatus that reduces the motor audible noise induced by using the single current shunt feedback topology of PWM inverter drives. This invention is an extension of U.S. Serial No. 11/552,758, filed October 25, 2006 (U.S. Patent Publication No. 2007/0090785 Al) entitled AUDIBLE NOISE REDUCTION FOR SINGLE CURRENT SHUNT PLATFORM, the contents of which are incorporated herein by reference.

[0003] Fig. Ia shows the Space Vector Plane of a 2-level inverter for a motor drive. The vectors correspond to the condition of the high side switches in the inverter of the motor drive, i.e., 100 means the high side switch for the U phase is on and the low side switches of the V and W phases are on. See Figs. 4 and 4A. In order to observe dc link current and allow reliable current sampling, minimum pulse constraint (Fig. Ib) has to be imposed whenever the voltage vector enters the shaded regions (Sector Crossings of Fig. Ia). This means that the minimum pulse spacing cannot be less than Tmin, otherwise the sampled currents from the DC link shunt sensor are not reliable.

[0004] In application Serial No. 11/552,758, a motor drive is described and shown and a method for audible noise reduction is disclosed. The motor drive is

also shown in Fig. 4 herein. This method of motor audible noise reduction involves the reduction of the total number of minimum pulse clampings adaptively inside the shaded regions of Fig. Ia. This is done by introducing a new scheduling for minimum pulse insertion. When the voltage vector enters the sector-crossing area (shaded area), the current feedback sampling rate and motor controller bandwidth are modified in accordance with the new scheduling. As soon as the voltage vector exits the shaded regions, nominal feedback sampling rate and motor controller bandwidth are resumed. In addition, the new scheduling for minimum pulse insertion is adaptive to motor speed. This is done to maximize the achievable controller bandwidth. In this adaptive feedback sampling regime, the PWM switching frequency is unaltered and hence the characteristic of PWM induced harmonics is preserved.

[0005] In Fig. 4, the DC link supplies power to the inverter 30. Current samples are taken via the single shunt element, typically a resistor R.

[0006] In a 2-level inverter system like that of Fig. 4, the instantaneous current waveform in the DC link is composed of current pulses. The current pulse width reduces as the modulation index (motor speed) decreases up to a point where minimum pulse constraint (hardware dependent, typically 0.5 to 2usec) has to be imposed in order to acquire reliable current feedback data via the DC link shunt element. As a consequence of this minimum pulse constraint, the current harmonic increases. The motor audible noise spectrum also increases and is spread out which leads to unacceptable noise performance in some applications.

SUMMARY OF THE INVENTION

[0007] An object of the invention is to solve the problem stated above . Specifically, the invention relates to a method and apparatus providing a further improvement to reduce audible noise generated by the single current shunt feedback technology described above.

[0008] The present invention reduces audible noise by removal of current samples within a PWM cycle when motor speed drops below a certain threshold (modulation index reduces below a certain threshold). Inverter induced audible noise is most prominent at low motor speeds (low modulation index).

[0009] Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The invention will now be described in greater detail in the following detailed description with reference to the drawings in which:

[0011] Fig. Ia shows a motor drive space vector plane for phases UVW of a motor showing a modulation vector and the shaded regions where minimum pulse constraint is required;

[0012] Fig. Ib shows the minimum pulse constraint of the prior art required for the samples S2 and S3 (active vector 110) in a single PWM cycle for the modulation vector of Fig. Ia;

[0013] Fig. Ic shows another example of the modulation vector inside the shaded region where the motor current cannot reliably be reconstructed from the DC bus current without requiring the minimum pulse constraint for both sets of samples;

[0014] Fig. Id shows the minimum pulse constraint required when the modulation vector is in the shaded region as in Fig. Ic for both active vectors (100) and (110) in a single PWM cycle;

[0015] Fig. Ie shows the current sampling and current average removal to reduce audible noise according to the invention when the modulation index is in the shaded area;

[0016] Fig. 2 shows a block diagram of a system implementing the reduced

current sampling modulation compensation and current average removal in a motor drive;

[0017] Figs. 3a, b and c show modulation command generation for three cases including no minimum pulse clamping restriction (Fig. 3a) and two cases requiring minimum pulse clamping restriction (Figs. 3b and 3c);

[0018] Fig. 4 shows a motor drive block diagram of the prior art;

[0019] Fig. 4A shows details of the inverter of Fig. 4; and

[0020] Fig. 4B shows how the phase currents are determined from the U,V,W phase voltages by appropriate timed sampling of the DC link shunt element.

DETAILED DESCRIPTION OF THE INVENTION

[0021] Figs. Ic and Id shows the condition of minimum pulse constraint being imposed for both active vectors (110 and 100).

[0022] In this description, the standard voltage vector convention is used. Accordingly, vector (110), for example, is the voltage vector obtained when the high side switches connected to the U and V phases are on and the high side switch connected to the W phase is off. See Fig. 4A. Thus, when the vector 110 is active, switches Ql, Q3 and Q6 are on and switches Q2, Q4 and Q5 are off. If the DC link current is sampled when the 110 vector is active, the sensed current corresponds to the phase current in the motor coil W, corresponding to -iw. Vector 001 would provide a sampled current corresponding to iw.

[0023] In normal operation, samples Sl and S4 measure current of the same motor phase (phase U) in the shunt R and samples S2 and S3 measure current of the same motor phase (phase W). See Fig. 4A. These current samples are averaged and reconstructed to generate motor phase currents (iu and iw).

[0024] As shown in Fig. Id, Sl and S2 thus sample motor current of different

phases. At high modulation index, Sl and S2 (or S3 and S4) move further away from each other (compare Figs. Ib and Id), so the phase error between samples Sl and S2 increases. Averaging the two pairs of samples within a PWM cycle eliminates this phase error. However, when motor speed decreases (lower modulation index), samples Sl and S2 approach each other (Fig. Id) and therefore this phase error is reduced significantly. The current sample averaging can be removed without introducing noticeable phase error. According to the invention, samples Sl and S2 are removed when motor speed falls below a certain threshold. The minimum pulse constraint for sampling Sl and S2 can thus also be removed as shown in Fig Ie. The minimum pulse constraint occurrence is reduced by half and therefore inverter induced audible noise is also reduced as a consequence.

[0025] Fig. 2 shows the block diagram of a system in a motor drive implementing current averaging removal and voltage (modulation index) error compensation to reduce audible noise. The block diagram can be implemented in various ways, for example in a digital signal processor (DSP) in firmware, in a computer program or as a hard wired electronic circuit or a combination of these. Note that, as shown in Fig. 4, the prior art system (excluding the inverter, is implemented in firmware).

[0026] Absolute motor speed is compared via comparator stage 5 to a configurable speed threshold (SpdThr) to form current average removal command (RmA vg(n)). The speed threshold is application dependent. Normally, in a PWM cycle, two averaged current values are generated from four samples Sl to S4. These current values are calculated by (Sl+S4)/2 and (S2+S3)/2. When RmAvg(n) = 1, i.e., the speed is less than the threshold, the two current values will be directly taken from samples S3 and S4 and samples Sl and S2 are eliminated, as is the current averaging. Thus, samples Sl and S2 of Fig. Id are removed and the minimum pulse constraint for sampling Sl and S2 is also removed as shown in Fig Ie. Samples S3

and S4 can be removed instead of samples Sl and S2. The removal of Sl and S2 is preferable to allow the latest current sample updates (S3 and S4) at the end of each PWM cycle to be used.

[0027] As a consequence of minimum pulse clamping for current sampling, the actual output voltage is altered to allow minimum pulse insertion. The voltage output generation block 15 of Fig. 2 performs this task.

[0028] There are 3 cases of voltage generating as shown in Figs. 3a, 3b and 3c. In case 1 (Fig. 3a), minimum pulse width constraint is not imposed, therefore no modulation compensation (Verr(n) = 0) is required. Both cases 2 (Fig. 3b) and 3 (Fig. 3c) require compensation (Verr(n) not equal zero) and output voltage (Voutput(n)) modification. When current average removal takes place (RmA vg(n) = 1), the amount of Volt-sec error generated by minimum pulse clamping is reduced by half in a PWM cycle. Therefore Verr(n-l) is scaled down (Fig. 2) when average removal command (RmAvg(n-l)) is set. See element 16, which is switched in when RmAvg(n-l) = 1. This is shown by switch S in the position shown in Fig. 2. The delay 17 (RmAvg(n-l) on average removal command (RmAvg(n)) is required to provide proper synchronization between actual minimum pulse removal and voltage error compensation due to the removal of this minimum pulse. The instantaneous (based on one pwm cycle) inverter output volt-sec error is also reduced by half when RmAvg(n) =l.

[0029] The following summarizes the three cases:

Case 1 : Fig.3a

Vref is outside unobservable regions (Fig. Ia)

Verr(n-l)=0

Vref(n) = Vcommand(n) + Verr(n-l)

Voutput(n) = Vref(n)

Case 2: Fig.3b

00912789.1

Vref is inside region of Fig. Ia

Vref(n) - Vcommand(n) + Verr(n-l)

Verr(n) = Vapply(n) - Vref(n)

Voutput(n) = Vapply(n)

Note: Vapply(n) is restricted by the minimum pulse width of 110 vector and 100 vector. Case 3: Fig.3c

Vref is outside star region of Fig. Ia and inside sector crossing.

Voutput(n) = Vapply(n)

Verr(n) = Vapply(n) - Vref(n)

Note: Vapply(n) is restricted by the minimum pulse width of 110 vector. Definitions

Vcommand - modulation command from motor controller.

Voutput - actual modulation output.

Verr- modulation error introduced by minimum pulse clamping.

Vref - compensated modulation command.

Speed - Motor Speed information

SpdThr- Speed Threshold for current average removal

RmA vg - Control bit for commanding current average removal. where n denotes the present PWM cycle n-1 denotes the previous PWM cycle

[0030] Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. Therefore the present invention

should be limited not by the specific disclosure herein, but only by the appended claims.