Description Titel: Automatic Gain Control for Delta-Sigma Modulator

Field of the invention

[0001] The present application relates to delta-sigma modulators. In particular, the present application relates to an analogue-to-digital band-pass delta-sigma modulator for use in telecommunications systems. The present application also relates to a method for delta-sigma modulation. The present application further relates to a computer-program product usable for the manufacture of the delta-sigma modulator and to a computer- program product enabling a processor to carry out the method for delta-sigma modulation.

Background of the invention

[0002] Radio communication technology and, in particular, mobile communications technology has been greatly advanced in recent years, as evident by the high performance digital mobile phones currently available.

[0003] Base transceiver stations (BTSs) are used in mobile communications technology to establish radio communication links between a mobile station, such as a mobile phone or the like, and a communications network in order to transfer communications data into telephony or other communications networks and vice versa.

[0004] A BTS usually comprises a digital radio server and a radio unit situated in a base station and antenna elements placed on a tower top equipment. A novel all digital antenna array system is described in the commonly assigned patent applications

PCT/EP2007/006335 and US 60/807,512, the teachings of which are incorporated herewith by reference. The PCT/EP2007/006335 describes a radio unit that can be integrated with the antenna elements in the tower top equipment. The patent application teaches a digital transceiver that is, in sending direction, coupled via a power digital-to-analog converter

(DAC) and an analogue filter element connected to an antenna dipole.

[0005] Delta-sigma modulators (DSM) and switching amplifiers are used, for example, within transmitters for RF and mobile communication.

[0006] Delta-sigma modulators have to cope with high dynamic-range signal of signal amplitudes. Large signal amplitudes at the input of a delta-sigma modulator might cause instability or clipping of the signal. Consequently, the signal amplitude within a delta- sigma modulator has to be controlled in order to ensure a stable operation and function.

[0007] Automatic gain controls (AGCs) have been employed to control the amplitude of delta-sigma modulators. For example, US 6,148,048 describes an AGC to control the input of an analogue-to-digital converter in the receive path of an intermediate frequency transceiver. The AGC is cascaded with an input amplifier for adjusting the signal before the adjusted signal is applied to a bandpass delta-sigma analogue-to-digital converter.

[0008] US 2006/0071835 describes a delta-sigma modulation circuit with a variable gain amplifier and a level variable feedback circuit. A digital signal processor is used to control the variable gain amplifier amplifying the input signal of a delta-sigma modulator and the level variable feedback circuit generating the feedback reference level of the delta-sigma modulator. The control signal controlling the variable gain amplifier and the control signal controlling the level variable feedback circuit are identical.

[0009] Japanese patent application JP 2007-324977 describes a delta-sigma modulation circuit that comprises a plurality of integrators connected in cascade in response to the order of the delta-sigma modulation; a quantizer for quantizing an output of a final stage integrator in the plurality of the integrators and outputting it as a 1 bit signal; an amplifier for amplifying a pulse height value output from the quantizer to a predetermined magnitude and feeding it back to the integrator; and gain control means for changing the gain of the amplifier 89 so as to increase the same when an output signal level of the final stage integrator exceeds a predetermined value. The disclosed delta-sigma modulator appears to be designed for base band signal processing and uses integrators as filter elements.

Summary of the invention

[0010] The teachings of the present application provide an analogue-to-digital delta- sigma modulator comprising a quantizer with a quantizer input and a quantizer output, a first resonator of one or more resonators, the first resonator providing a first resonator output signal as quantizer input signal to the quantizer input, at least one feedback loop feeding an output signal of the analogue-to-digital delta- sigma modulator to at least one scaling element, wherein an output of the at least one scaling element is connected to at least one of the one or more resonators. The analogue-to-digital delta-sigma modulator further comprise a gain control loop feeding the quantizer input signal to a signal processing element, wherein the signal processing element is connected to the at least one scaling element for providing a gain scaling factor to the at least one scaling element.

[0011] The quantizer input signal, i.e the quantizer input voltage or the amplitude of the quantizer input voltage is thus monitored and directly used for adjustment or scaling of the gain.

[0012] The proposed structure for automatic gain control of a delta-sigma modulator can be implemented in a simple and inexpensive manner. An analogue variable gain amplifier is not needed with a delta-sigma modulator according to the teachings of the present application. This prevents the generation of additional noise or distortion due to the analogue variable gain amplifier.

[0013] In yet a further aspect a computer program product is proposed that is embodied on a computer readable medium and comprises executable instructions for the manufacture of the above mentioned delta-sigma modulator.

[0014] The teachings disclosed herein equally provide a method for analogue-to-digital delta-sigma modulation, the method comprising filtering a first resonator input signal in a first resonator of one or more resonators to obtain a first resonator output signal, quantizing the first resonator output signal to obtain a quantized output signal, scaling the quantized output signal using a gain scaling factor to obtain at least one scaled feedback signal,

feeding the at least one scaled feedback signal back to at least one of the one or more resonators, and determining the gain scaling factor from the first resonator output signal.

[0015] The first resonator output signal or quantizer input signal, i.e. the voltage or amplitude of the first resonator output signal or quantizer input signal, are used for determining the gain scaling factor.

[0016] An input signal to the analogue-to-digital delta-sigma modulator may be a radio frequency (RF) signal such as a mobile telecommunications signal.

[0017] The delta-sigma modulator can be a continuous-time delta-sigma modulator. The delta-sigma modulator can be a bandpass delta-sigma modulator or a low pass delta-sigma modulator. The filtering can be adjusted by the one or more resonators.

[0018] The signal processing element comprises a level detector for detecting the amplitude level of the quantizer input signal, such as the amplitude level of the quantizer input voltage.

[0019] Scaling of the quantized output signal may comprise changing the quantized output signal to a scaled feedback signal using at least one scaling coefficient. The at least one scaling coefficient may depend on the gain scaling factor.

[0020] Changing the quantized output signal may comprise multiplying the quantized output signal with at least one scaling coefficient. In this case, the scaling element may comprise a multiplier for multiplication of the gain scaling factor with the feedback signal.

[0021] The scaling element may comprise a differential transistor pair, wherein two transistors are connected by their emitter junctions in order to multiply a "single-ended" current by "+1" or "-1" by making one or the other transistor conducting.

[0022] The scaling element may also comprise a Gilbert-cell type structure for multiplication with the feedback signal.

[0023] A programmable current source may be provided for generating a tail current for application to the differential transistor pair or to the Gilbert-cell type structure. Settings of the programmable current source may be determined by the scaling coefficient.

[0024] The scaling coefficient may be adjusted in an analogue manner. For example, the amplitude is detected in real-time and the at least on feedback coefficient is adjusted by a controller.

[0025] The scaling coefficient may also be digitally adjusted. For example, the feedback coefficient may be increased by at least one step, and thus the scaling of the feedback signal is reduced by one step, when the signal amplitude of the quantizer input signal passes a first predetermined level. When the signal amplitude of the quantizer input signal falls below a second predetermined level, the feedback coefficient may be decreased by at least one step and the scaling of the feedback signal is increased correspondingly.

[0026] In a further aspect, a computer program product is proposed that comprises instructions that enable a processor to carry out the method for delta-sigma modulation described above.

Description of the drawings

[0027] The teachings disclosed herein may be better understood when reading the detailed description and the figures, wherein identical numbers identify identical or similar objects and wherein:

Fig. 1 shows an analog-to-digital delta-sigma modulator according to the teachings of this application.

Fig. 2 shows an exemplary implementation of a scaling element and its adjacent circuitry according to the teachings of this application.

Detailed description of the invention

[0028] The following description of a detailed example of the teachings disclosed herein is given as a pure example that is not intended to limit the scope of protection as defined by the claims in any way.

[0029] Fig. 1 shows a 6 ^th order continuous-time bandpass analog-to-digital delta-sigma modulator 100 according to the teachings disclosed herein. The illustrated delta-sigma modulator 100 comprises a quantizer 110 for quantizing a first resonator output signal applied to the quantizer input 11. The first resonator output signal is provided by a first resonator 122 of a plurality of resonators. In the example shown, the plurality of resonators comprises the first resonator 122, a second resonator 124, and a third resonator 126 that are coupled in series.

[0030] The delta-sigma modulator may further comprise transconductance stages (GM) 121, 123, 125 before the first resonator 122, the second resonator 124 and the third resonator 126, respectively.

[0031] A quantizer output signal provided at a quantizer output 12 can be used as an output signal RFout of the delta-sigma modulator 100 and is, in the same time, applied to a digital-to-analog converter 130 in feedback loop 30 to obtain a feedback signal fb. The feedback signal fb is applied to each of a first scaling element 142, a second scaling element 144, and a third scaling element 146, wherein the feedback signal fb is scaled or modified. Each of the first scaling element 142, the second scaling element 144, and the third scaling element 146 apply a first scaling coefficient scl, a second scaling coefficient sc2, and a third scaling coefficient sc3, respectively, to the feedback signal fb to obtain a first scaled feedback signal fb 7, a second scaled feedback signal fb '2, and a third scaled feedback signal fb '3, respectively. The first scaled feedback signal fb 7 output by the first scaling element 142 is applied to the first resonator 122. In parallel, the second scaled feedback signal fb '2 output by the second scaling element 144 and the third scaled feedback signal fb '3 output by the third scaling element 146 are applied to the second

resonator 124 and to the third resonator 126, respectively. Thus the feedback signal Jb is individually scaled for each of the plurality of resonators using the respective scaling coefficients scl, sc2, sc3.

[0032] The delta-sigma modulator 100 further comprises a gain control loop 50 for changing or controlling the scaling coefficients scl, sc2, sc3. The quantizer input signal or the first resonator output signal at the quantizer input 11 are applied to a signal processing element 150. The signal processing element 150 analyses the quantizer input signal level and determines a gain scaling factor gsj. The signal processing element 150 is further connected to each of the first scaling element 142, the second scaling element 144, and the third scaling element 146 for providing the gain scaling factor gsf to each of the first scaling element 142, the second scaling element 144, and the third scaling element 146.

[0033] The signal processing element 150 may contain a level detector for monitoring the voltages at the quantizer input 11. A voltage at the quantizer input 11 higher than a predetermined value may be an indication for instability of the delta-sigma modulator 100. Instability can occur in 1-bit delta-sigma modulators when the voltage of the delta-sigma modulator input signal RFin becomes too large. The signal processing element 150 detects such high voltages and changes the gain scaling factor gsf accordingly.

[0034] For example, the gain control loop 50 can be a digital control loop. In this case, signal processing element 150 may increase or decrease the gain scaling factor gsf by a predetermined step when a level detector of the signal processing element 150 detects that the voltage level at the quantizer input 11 passed or has passed a first predetermined level. The signal processing element 150 may then decrease, respectively increase the gain scaling factor gsf by the predetermined step, when the level detector of the signal processing element 150 detects that the voltage level at the quantizer input 11 falls below a second predetermined level.

[0035] The gain control loop 50 can also be an analogue control loop with a continuous control. In this case the a level detector of the signal processing element 150 continuously

detects or monitors the voltage level at the quantizer output 11 and the gain scaling factor gsf ^' is adjusted accordingly.

[0036] The gain scaling factor gsf is used to scale the feedback signal fb via the first scaling coefficient scl, the second scaling coefficient sc2, and the third scaling coefficient sc 3 in the first scaling element 142, the second scaling element 144, and the third scaling element 146 in order to obtain the first scaled feedback signal fb 7, the second scaled feedback signal fb '2 and the third scaled feedback signal^δ '3, respectively.

[0037] The first scaled feedback signal fb 7 may be described as:

fb 'l = fb * scl (gsf), wherein the scl is a function of gsf

[0038] Accordingly, the second scaled feedback signal fb '2 may be described as:

fb '2 = fb * sc2(gsfi, wherein the sc2 is a function of gsf and

[0039] the third scaled feedback signal fb '3 may be described as:

fb '3 = fb * sc3(gsfi, wherein the sc3 is a function of gsf

[0040] Each of the first scaling element 142, the second scaling element 144, and the third scaling element 146 may comprise one or more multipliers for multiplying the feedback signal fb with the respective scaling coefficient scl, sc2, sc3.

[0041] Each of the first scaling element 142, the second scaling element 144, and the third scaling element 146 may also comprise a differential transistor pair. In this case, two transistors are connected on their emitter connections for multiplying a signal by "+1" or by "-1" depending on which of the transistors will be switched to a conducting state. The concept of a differential transistor pair is known to a person skilled in the art and will not be explained in detail here.

[0042] Each of the first scaling element 142, the second scaling element 144, and the third scaling element 146 may also comprise a Gilbert-Type structure as known in the art and described with respect to Fig 2.

[0043] The scaling coefficients may be provided as tail currents of differential amplifiers. In normal operation of the sigma-delta modulator 100, the tail currents may be fixed to a pre-determined value and can be supplied by a programmable digital-to-analog converter (DAC) or tunable current sources, such as a tuneable current source 23 in Fig. 2.

[0044] For example, the scaling coefficients may be determined as:

scl = cl * gsf sc2 = c2 * gsf and sc 3 = c3 * gsf.

wherein cl, c2 and c3 are coefficients provided at the first scaling element 142, the second scaling element 144, and the third scaling element 146, respectively. All scaling coefficients scl, sc2, and sc3 are thus scaled by the same gains scaling factor gsf

[0045] The coefficients cl, c2, and c3 can be equal, different and can be in a certain relation with each other. The coefficients cl, c2, and c3 can also be adjustable according to an application of the sigma-delta modulator 100. As an example, the coefficients cl, c2, and c 3 may be related according to:

cl = a * c2 = b * c3,

wherein a and b are variables.

[0046] The example shown in Fig.l shows a 6 ^th order bandpass sigma-delta modulator 100, with three resonators 122, 124, and 126 and, accordingly three gain scaling elements

142, 144, and 146. It will apparent to those skilled in that art that this arrangement is purely exemplary and by no means limiting. The teachings of this application may be equally

applied to 2 ^nd order lowpass or bandpass delta-sigma modulator with the first resonator 122 and the first scaling factor 142 but no further resonators. The teachings of this application may also be applied to 4 ^th order or higher lowpass or bandpass delta-sigma modulators with the corresponding arrangement of resonators.

[0047] Fig. 2 shows an exemplary implementation of a circuit 20 comprising the scaling element 142 and its adjacent circuitry of an automatic gain control according to the teachings disclosed herein. The adjacent circuitry are in particular a first resonator half 122a and a second resonator half 122b of resonator 122. It should be understood that the following description of Fig. 2 can also be applied in an analogue manner to the combination of scaling element 144 and resonator 124, or to the combination of scaling element 146 and resonator 126, respectively.

[0048] The circuit 20 has an input port for the input signal. Amplifier 203 is a voltage-to- current converter with the transconductance gm. Amplifier 203 has two outputs that form a differential pair.

[0049] The circuit 20 shown in Fig. 2 also has a pair of feedback ports FEEDBACK+, FEEDBACK- for a differential feedback signal.

[0050] Each of the two feedback ports FEEDBACK+, FEEDBACK- is connected to the base of a transistor 204 and 205, respectively, so that the differential data signal can control the flow of current through the transistors 204 and 205.

[0051] The dashed ellipsoid 207 represents the "subtraction point" at which the feedback signal is subtracted from the input signal in order to form an error signal. Since circuit 20 is designed for differential currents, the subtraction point 207 actually contains two wire junctions at which current superposition takes place. In the represented implementation the subtraction is performed by adding or superposing two pairs of differential currents of corresponding signs, i.e. the current corresponding to the data signal and the (inverted) current corresponding to the feedback signal FB, and vice versa.

[0052] The resulting difference currents flow through the first resonator half 122a and the second resonator half 122b, respectively. In a known manner, the first resonator half 122a and the second resonator half 122a filter the difference currents with respect to a resonance frequency of the resonator. Just beneath each resonator half 122a, 122b the respective electric potentials are tapped and the differential voltage signal is transmitted either to the quantizer 110 or to an amplifier 203'. Amplifier 203' belongs to a subsequent circuit that is similar to circuit 20. Amplifier 203' is a voltage-to-current converter with a transconductance gm (not necessarily the same as the transconductance of amplifier 203).

[0053] Transitors 21 and 22 are fed by a positive clock signal CLK+ and a negative clock signal CLK-, respectively. The current flowing through transistor 21 (when transistor 21 is open) is not needed and therefore discarded. The current flowing through transistor 22 is sent to the part of circuit 20 described above.

[0054] The current for the circuit is provided by a tuneable current source 23. The magnitude of the current delivered by tuneable current source 23 is adjusted as a function of the output of the signal processing element 150 (Fig. 1), which in turn evaluates the level of the quantizer input signal 11 (Fig. 1). The signal processing element 150 is not mandatory, but could be replaced e.g. by a direct connection.

[0055] The teachings of this application may also be applied to keep the sigma-delta modulator 100 in a mode with high signal-to-noise ratio and without any instabilities for a large range of possible radio frequency input signal Rfin amplitudes. In this case the gain control loop may sense a number of signal amplitudes at the quantizer input 11 in order to adjust the scaling coefficients scl, sc2, sc3.

[0056] It should be understood that the foregoing relates to exemplary embodiments of the teachings disclosed herein and that modifications may be made without departing from the spirit and scope as set forth in the following claims.

[0057] While various embodiments of what is taught have been described above, it should be understood that they have been presented by way of example, and not limitation.

It will be apparent to persons skilled in the relevant arts that various changes in form and detail can be made therein without departing from the scope of what is taught. For example, any bipolar transistors depicted in the drawings and/or described in the text could be field effect transistors, and vice versa. The resonators need not be a LC-type resonator, but also any other type of suitable resonator, such as a tank, a transmission line resonator, a cavity resonator or a surface wave resonator. In addition to using hardware (e.g., within or coupled to a Central Processing Unit ("CPU"), microprocessor, microcontroller, digital signal processor, processor core, System on Chip ("SOC"), or any other device), implementations may also be embodied in software (e.g., computer readable code, program code, and/or instructions disposed in any form, such as source, object or machine language) disposed, for example, in a computer usable (e.g., readable) medium configured to store the software. Such software can enable, for example, the function, fabrication, modelling, simulation, description and/or testing of the apparatus and methods described herein. For example, this can be accomplished through the use of general programming languages (e.g., C, C++), hardware description languages (HDL) including Verilog HDL, VHDL, and so on, or other available programs. Such software can be disposed in any known computer usable medium such as semiconductor, magnetic disk, or optical disc (e.g., CD-ROM, DVD-ROM, etc.). The software can also be disposed as a computer data signal embodied in a computer usable (e.g., readable) transmission medium (e.g., carrier wave or any other medium including digital, optical, or analog-based medium). Embodiments of the disclosed apparatus, method or computer-program product may include methods of providing the apparatus described herein by providing software describing the apparatus and subsequently transmitting the software as a computer data signal over a communication network including the Internet and intranets.

[0058] It is understood that the apparatus and method described herein may be included in a semiconductor intellectual property core, such as a microprocessor core (e.g., embodied in HDL) and transformed to hardware in the production of integrated circuits. Additionally, the apparatus and methods described herein may be embodied as a combination of hardware and software. Thus, the disclosed apparatus, method or computer-program producte should not be limited by any of the above-described

exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.