ASYNCHRONOUS NETWORK

TECHNICAL FIELD

[0001] The present embodiments relate generally to electronic communications, and specifically to time and frequency synchronization in communication systems.

BACKGROUND OF RELATED ART

[0002] Among the technologies that allow computers and/or other network devices to form a local area network (LAN), Ethernet has become the dominant networking technology and is standardized in the IEEE 802.3 family of standards. The Ethernet standard has evolved over time so that different variants of the Ethernet protocol now exist to support higher bandwidth, improved media access controls, different physical media channels, and/or other functionalities. For example, IEEE 802.3 now has variants covering speeds (or transmission rates) ranging from 10 Mbit/s, 100 Mbit/s, 1 Gbit/s, to 10 Gbit/s and even higher, and has variants that govern physical channels such as coaxial cables, fiber-optics, and unshielded or shielded twisted-pair cables.

[0003] Traditionally, Ethernet transmissions are asynchronous in nature, and therefore Ethernet packets typically do not carry clock synchronization information. However, a synchronous network may provide synchronized clocks with higher accuracy and is desirable in certain areas of application, for example, in measurement and control systems, or in "carrier Ethernet services" where telecommunication network providers provide Ethernet services over their carrier network. Precision time protocol (PTP), which is described in the IEEE 1588 standards, is a protocol that enables clock synchronization in an Ethernet network. Clock synchronization comprises two parts, time synchronization and frequency synchronization. The PTP uses a hierarchical, master-slave architecture to distribute clock information to achieve time synchronization, where the clock source is called a master device and the clock destination is called a slave device. Packets used by PTP to convey clock synchronization information (e.g., timestamps from the packets) between the master device and the slave device are called PTP messages. Once enough timestamps are collected by the slave device, the slave device can calculate a time difference between itself and the master device, and synchronize its time and clock frequency with the master device based on the time difference.

[0004] Frequency differences between the master device and the slave device vary with ambient temperature changes, supply voltage fluctuations, component degradations, and so on. Further, it is typically desirable to keep the PTP message traffic at a minimum (e.g., 2 to 4 packets per second) to reduce the adverse effect on the network's loading associated with clock synchronization. However, the effectiveness of conventional methods in frequency synchronization tends to drop to an unsatisfactory degree when the PTP message exchange rate becomes too low.

[0005] Accordingly, there is a need to provide a method and apparatus for automatic time and frequency synchronization over an asynchronous network (e.g., a packet-switched network such as an Ethernet network) that increase clock synchronization accuracy, allow for reduced clock synchronization traffic, and decrease the processing load of a network processor.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present embodiments are illustrated by way of example and are not intended to be limited by the figures of the accompanying drawings, where:

[0007] FIG. 1 is a block diagram of an exemplary communication network within which some embodiments may be implemented;

[0008] FIG. 2 is a diagram illustrating exemplary PTP message exchanges between the master device and the slave device of FIG. 1 in accordance with some embodiments;

[0009] FIG. 3 is a functional block diagram of the slave device of FIG. 1 in accordance with some embodiments;

[0010] FIG. 4 is a functional block diagram of the clock in the slave device of

FIG. 3 in accordance with some embodiments;

[0011] FIG. 5 is a functional block diagram of a clock servo which can be implemented within the processor in the slave device of FIG. 3 in accordance with some embodiments; [0012] FIG. 6 is an illustration of an exemplary state machine which can be implemented within the slave device of FIG. 3 to control the clock servo of FIG. 5 in accordance with some embodiments;

[0013] FIG. 7 is a flowchart illustrating adjustment of the clock of FIG. 4 in accordance with some embodiments;

[0014] FIG. 8 is a flowchart illustrating implementing synchronization over an asynchronous network in accordance with some embodiments;

[0015] FIG. 9 is a schematic diagram of an implementation of a real-time counter in accordance with some embodiments; and

[0016] FIG. 10 is a schematic diagram of an example of the PI controller in FIG.

5 in accordance with some embodiments.

[0017] Like reference numerals refer to corresponding parts throughout the figures.

DETAILED DESCRIPTION

[0018] A method and apparatus for enabling automatic time and frequency synchronization over an asynchronous network (e.g., an Ethernet network) are disclosed that increase clock synchronization accuracy, allow for reduced clock synchronization traffic, and decrease the processing load of a network processor. According to some embodiments, a method for implementing synchronization comprises obtaining a plurality of timestamps from messages exchanged between a master device and a slave device; determining one or more time differences between a clock of the master device and a clock of the slave device based on the plurality of timestamps; determining a synchronization index indicating a degree of synchronization between the clock of the master device and the clock of the slave device based on the one or more time differences; and synchronizing a frequency of the clock of the slave device with a frequency of the clock of the master device based on the synchronization index.

[0019] In the following description, numerous specific details are set forth such as examples of specific components, circuits, and processes to provide a thorough understanding of the present disclosure. Also, in the following description and for purposes of explanation, specific nomenclature is set forth to provide a thorough understanding of the present embodiments. However, it will be apparent to one skilled in the art that these specific details may not be required to practice the present embodiments. In other instances, well-known circuits and devices are shown in block diagram form to avoid obscuring the present disclosure. The term "coupled" as used herein means connected directly to or connected through one or more intervening components or circuits. Any of the signals provided over various buses described herein may be time-multiplexed with other signals and provided over one or more common buses. Additionally, the interconnection between circuit elements or software blocks may be shown as buses or as single signal lines. Each of the buses may alternatively be a single signal line, and each of the single signal lines may alternatively be buses, and a single line or bus might represent any one or more of a myriad of physical or logical mechanisms for communication between components. The present embodiments are not to be construed as limited to specific examples described herein but rather to include within their scope all embodiments defined by the appended claims.

[0020] FIG. 1 is a block diagram of an exemplary communication network 100 within which some embodiments may be implemented. Communication network 100 is shown to include two terminal devices 110(a) and 110(b), which are coupled to each other through a data link 120. Terminal devices 110(a) and 110(b) may include any electronic device capable of connecting to either a wired or a wireless network including, for example, a personal computer, a server, a laptop, a mobile phone, a personal digital assistant (PDA), or the like. Data link 120 may be any suitable physical media channel including, for example, coaxial cables, fiber-optics, and/or unshielded/shielded twisted pairs. Data link 120 may further include any number of intermediate network devices (not shown in FIG. 1), which may be any suitable devices including, for example, computers, switches, routers, hubs, gateways, access points, or the like. Of course, terminal devices 110(a) and 110(b) and data link 120, are just exemplary components of a network, as the network may further include any number of network-enabled devices (e.g., a hub, a switch, a router, a bridge, or other terminal devices) to form a larger network including, for example, a local area network (LAN), a wide area network (WAN), a wireless LAN (WLAN), and/or may be connected to the Internet.

[0021] Terminal devices 110(a)- 110(b) may communicate with each other through data link 120 using Ethernet technologies, as described in the IEEE 802.3 family of standards. Furthermore, terminal devices 110(a)- 110(b) may synchronize their clocks with each other using precision time protocol, such as PTP version 2 described in the IEEE 1588-2008 standard. As such, one terminal device (e.g., device 110(a)) can act as a master device which provides the clock reference, and another terminal device (e.g., device 110(b)) can act as a slave device whose clock can be synchronized with the master's clock through PTP message exchanges. A best master clock algorithm is used in PTP to decide, among a group of devices, which device is to be a "grandmaster." However, it is sufficient to understand that a master device is typically a device that is equipped with a reliable time source including, for example, a global positioning system (GPS) receiver or a receiver to receive a time signal from an atomic clock. For purposes of discussion herein, terminal device 110(a) is equipped with a GPS receiver 115 and is referred to as the master device. Similarly, terminal device 110(b) is referred to as the slave device.

[0022] According to the present embodiments, the slave device comprises a transceiver for exchanging messages between the slave device and the master device; a clock; and a processor configured to obtain a plurality of timestamps from messages exchanged between the slave device and the master device, determine one or more time differences between the clock of the slave device and a clock of the master device based on the plurality of timestamps, determine a synchronization index indicating a degree of synchronization between the clock of the slave device and the clock of the master device based on the one or more time differences, and synchronize a frequency of the clock of the slave device with a frequency of the clock of the master device based on the synchronization index.

[0023] In some embodiments, to synchronize the frequency, the processor in the slave device monitors the synchronization index, and the processor comprises a controller (e.g., a proportional-and-integral (PI) controller) that selectively adjusts the frequency of the clock of the slave device based on the monitoring. In some embodiments, the controller selectively adjusts the frequency of the clock of the slave device until the synchronization index is less than a first threshold. If a respective time difference is larger than a predetermined value, or if the synchronization index is larger than a second threshold, then the processor further synchronizes a time of the clock of the slave device with a time of the clock of the master device.

[0024] In this way, clock synchronization accuracy between the master device and the slave device increases, and clock synchronization traffic is allowed to be reduced, which in turn decreases the processing load of a network processor. Implementation techniques of various embodiments of the slave device such as terminal device 110(b) are described below in fuller detail.

[0025] To facilitate a better understanding, a diagram of an exemplary exchange flow 200 of PTP messages between the master device (e.g., device 110(a)) and the slave device (e.g., device 110(b)) illustrating how the timestamps may be received or known by the slave device is provided in FIG. 2. The PTP message exchange flow 200 is merely exemplary, as other suitable methods can be used in the present embodiments to retrieve timestamps and for achieving time synchronization via PTP message exchanges. In addition, the techniques of the present embodiments can be used to implement time and frequency synchronization on the slave devices as well as any suitable intermediate network devices including, for example, an end-to-end transparent clock, or a peer-to- peer transparent clock.

[0026] The exemplary PTP message exchange flow 200 is now explained with reference to both FIGS. 1 and 2.

[0027] First, the master device sends a first type of PTP message, called a synchronization ("Sync") message, to the slave device. The master device also records the time (as indicated by the master's clock) at which the Sync message is sent as timestamp t .

[0028] Second, the slave device receives the Sync message, and records the time of receipt (as indicated by the slave's clock) of the Sync message as timestamp t ₂ .

[0029] Third, the master device conveys the timestamp t _\ to the slave device.

This can be done by embedding the timestamp ti in the Sync message if the master device supports this method. Typically, some hardware processing is used to ensure the accuracy of timestamp t _\ should this method is adopted. Optionally, the master device embeds timestamp t _\ in a second type of PTP message, called a follow up ("Follow_Up") message, and sends the Follow_Up message to the slave device.

[0030] Fourth, the slave device sends a third type of PTP message, called a delay request ("Delay Req") message, to the master device, and records the time the message is sent (as indicated by the slave's clock) as timestamp t ₃ .

[0031] Fifth, the master device receives the Delay Req message and records the time of receipt (as indicated by the master's clock) of the Delay Req message as timestamp t ₄ . [0032] Sixth, the master device embeds the timestamp t ₄ in a fourth type of PTP message, called a delay response ("Delay_Resp") message, and sends the Delay_Resp to the slave device.

[0033] After these PTP message exchanges are completed, the slave device has all four timestamps t _ls t ₂ , t ₃ , and I4. These four timestamps can be used to calculate a time difference At and a mean path delay dA between the master device and the slave device.

[0034] More specifically, as illustrated in FIG. 2, the propagation delay from the master device to the slave device is denoted as t _ms , and the propagation delay from the slave device to the master device is denoted as t _sm . Then, the mean path delay dA, which is defined (t _ms + t _sm ) / 2, can be represented by:

d _A = (tms + t _sm ) / 2 = [(t ₂ - t ₃ ) + (t4 - ti)] / 2 (1)

and the time difference At can be represented by:

At = -offsetFromMaster= - (t ₂ - (ti + t _ms )) = ti - 1 ₂ + (2)

[0035] In this way, assuming t _ms is equal to t _sm , mean path delay dA and the time difference At can be deduced from timestamps t _ls t ₂ , t ₃ , and t ₄ once they are known by the slave device, and therefore time synchronization can be achieved by PTP message exchanges.

[0036] However, any asymmetry between t _ms and t _sm introduces an error into the clock offset correction. The present embodiments may take the asymmetry of path delays into consideration in order to achieve higher clock synchronization accuracy.

[0037] According to some embodiments, after achieving frequency and time synchronization (processes of which are described in fuller detail below), the master and the slave devices may each output a pulse-per-second signal, which can be measured to determine an asymmetric error between the master and the slave devices. Because the asymmetric error is characteristic to a particular combination of master and slave devices (e.g., a master device made by manufacturer A and a slave device made by manufacturer B), according to some embodiments, a terminal device (e.g., device 110(b)) can exchange the asymmetric error information so that another node in the network may know the chip type of its link partner and estimate a corresponding asymmetric error. The estimated asymmetric error may be used to further improve the accuracy of time and frequency synchronization. [0038] Furthermore, besides time synchronization, frequency synchronization plays an important role in implementing synchronization over an asynchronous network such as an Ethernet packet-switched network. Many factors, such as characteristics of local oscillators, ambient temperature changes, supply voltage fluctuations, component degradations, etc., contribute to frequency (or tick rate) differences between the clocks of the master device and the slave device. Therefore, the present embodiments can automatically track the changes in frequency differences between the master device and the slave device.

[0039] FIG. 3 is a functional block diagram 300 of a slave device 310 that is one embodiment of the terminal device 110(b) of FIG. 1. Slave device 310 includes a transceiver 320, a processor 330, and a clock 340. While FIG. 3 only shows a single transceiver 320 and a processor 330 for simplicity, slave device 310 may include a plurality of transceivers 320 and/or processors 330.

[0040] Transceiver 320 is coupled to data link 120 (see FIG. 1) to exchange network packets to and from another terminal device (e.g., a master device), and is coupled to processor 330 for data communication. In accordance with the present embodiments, transceiver 320 includes circuitry that implements physical layer (PHY) functionalities of the OSI model. As such, transceiver 320 may be one or more integrated circuits, a chip, a stand-alone device, a portion of an integrated circuit, or the like.

[0041] Memory device 335 may include any suitable type of storage device including, for example, an SRAM, a DRAM, a CAM, an EEPROM, a flash memory, latches, and/or registers. Processor 330 can be any suitable processor capable of executing scripts or instructions of one or more software programs stored, for example, in memory 335. Although not shown in FIG. 3 for simplicity, slave device 310 can also include a well-known cache memory that stores frequently used instructions and/or data.

[0042] While memory 335 is shown as a component of the processor 330. In some embodiments all or a portion of memory 335 is implemented outside of the processor 330. In some embodiments, the memory 335 includes a non-transitory computer-readable storage medium (e.g., one or more nonvolatile memory elements, such as EPROM, EEPROM, Flash memory, a hard disk drive, and so on) that stores instructions to be executed by the processor 330. The non-transitory storage medium stores a synchronization module 338, which includes instructions for performing time and frequency synchronization as described herein. For example, module 338 includes instructions that, when executed by the processor 330, implement all or a portion of the clock servo 510 (FIG. 5), the state machine 600 (FIG. 6), the method 700 (FIG. 7), and/or the method 800 (FIG. 8).

[0043] Clock 340 comprises a real-time counter (RTC), or a real-time clock, to provide current time information to various components of slave device 310. Depending on the application, clock 340 may include one or more clock sources for use as a working clock including, for example, a local reference clock, a recovered synchronous Ethernet (SyncE) clock, and/or an external clock input generated from a voltage- controlled oscillator (VCO). In the embodiments that have more than one clock sources, clock 340 may include inputs to receive a source select signal from processor 330 to select which source to use. More details on these clock sources are provided below with regard to FIG. 4. In some embodiments, clock 340 is coupled to transceiver 320 to provide time information to transceiver 320. Clock 340 is also coupled to processor 330 to receive an adjustment of a frequency (or a tick rate) of clock 340. According to some embodiments, the adjustment includes varying an increment value that is reflective of the clock 340's frequency. According to other embodiments, the adjustment includes controlling a voltage level on an input of the VCO.

[0044] FIG. 4 is a functional block diagram 400 of a clock 410 that is one embodiment of the clock 340 of FIG. 3. With reference to both FIGS. 3 and 4, clock 410 includes a real-time counter (RTC) 420 coupled to an output of clock 410 to provide a clock signal to various components in slave device 310. Clock 410 also includes three clock sources: a local reference clock 430 which is coupled to a fixed- frequency (e.g., 25MHz) oscillator or a crystal oscillator 402, an external clock input 440 generated from a voltage-controlled oscillator (VCO) 404, and a recovered reference clock (e.g., a recovered synchronous Ethernet (SyncE) clock) 450. The three clock sources 430, 440, and 450 are merely exemplary. One may select any suitable number and/or different types of clock source to fit the purposes of a particular application. Clock 410 further includes inputs to receive a source select signal Source_Sel[l :0] from processor 330 (FIG. 3) to instruct multiplexers MUX l and MUX 2 to select one of the clock sources 430-450 as the working clock. The selected working clock is provided to RTC 420 to generate the clock signal. The configuration of clock 410 in FIG. 4 is for illustration purposes only, as the scope of the disclosure may include other logically equivalent circuitry. For example, multiplexers MUX l and MUX_2 may be a single multiplexer, and the source select signal may be more or less than 2 bits.

[0045] RTC 420 is a circuit or a component that generates the clock signal based on the signals generated from the selected working clock. Optionally, RTC 420 may include a pulse-per-second (PPS) generator (not shown in FIG. 4) to generate a PPS signal for synchronization, precise timekeeping, or other purposes, based on the selected working clock. In some embodiments, RTC 420 is implemented in an Ethernet PHY. RTC 420 is further coupled to a frequency adjuster 460, which includes an input to receive an adjustment value ("Adjust Value") from (e.g., from processor 330 or PI controller 550, FIG. 5). In some embodiments, the frequency adjuster 460 adjusts the increment value of the RTC 420 by an amount corresponding to the adjustment value. In some embodiments, RTC 420 includes an input coupled to processor 330 to receive a time value for direct overwrite of the clock 410's time.

[0046] Frequency adjuster 460 may be implemented as a hardware component that is included in clock 410, or may be implemented as a software component that is stored in memory 335 (e.g., in the non-transitory storage medium of memory 335) and executed by processor 330 (FIG. 3). The increment value is reflective of the clock 340's frequency. For example, the IEEE1588 standard defines an RTC (e.g., RTC420) with a 48-bit field (the "seconds field") that indicates an integer number of seconds and a 32- bit field (the "nanoseconds field") that indicates a fractional amount of a second. The nanoseconds field of RTC 420 advances an amount that is indicated by the increment value each clock cycle. Thus, a first way for processor 330 to adjust clock 410's frequency (or tick rate) is varying the increment value.

[0047] In addition, because the frequency of the crystal or fixed-frequency oscillator fluctuates in very little amount, for example, ±100ppm, in some embodiments, the nanoseconds field is expanded to include a 26-bit "sub-nanoseconds field" to further accurately indicate the fractional amount of a second. In these embodiments, the increment value is expanded from 32 bits to 58 bits accordingly. Of course, one may select any suitable number of bits for the sub-nanoseconds field to fit the purposes of a particular application.

[0048] Local reference clock 430 is a free running clock that relies on a well- known crystal oscillator or other types of fixed-frequency (e.g., 25MHz) oscillator. Typically, there is no means to arbitrarily vary the oscillation frequency in order to adjust the frequency of clock 410. As such, if local reference clock 430 is selected as the working clock, processor 330 (FIG. 3) adjusts clock 410's frequency by varying the increment value.

[0049] External clock 440 is coupled to VCO 404 to receive a clock input. VCO

404 may be any suitable electronic oscillator including, for example, harmonic oscillators or relaxation oscillators. VCO 404 includes a control input that is responsive to different voltage levels. The frequency of the output of VCO 404 varies with the voltage level applied on the control input. Thus, a second way for processor 330 to adjust clock 410's frequency (or tick rate) is varying the voltage level on the control input of the VCO 404. As such, if external clock 440 is selected as the working clock, processor 330 adjusts clock 410's frequency by varying the increment value and/or by varying the voltage level on the input of VCO 404.

[0050] In one or more embodiments, slave device 310 (FIG. 3) is equipped with a transceiver 320 or another PHY device that is capable of achieving frequency (and time) synchronization through a "synchronous Ethernet" (SyncE). SyncE, which is different from the IEEE 1588 (PTP) standard, is a technique that provides frequency synchronization over a packet network based on physical layer clock distribution. In SyncE, every node in the network (e.g., network 100 of FIG. 1) is capable of recovering and re -transmitting the frequency for synchronization, in order to form a synchronization chain. As such, if the synchronization chain can be formed and SyncE is available, recovered reference clock 450 may receive SyncE data from transceiver 320 and generate (or recover) a SyncE clock, which is synchronous in frequency with the master device with high accuracy.

[0051] In some embodiments, if SyncE is available, recovered reference clock

450 is to be selected by processor 330 to provide SyncE clock as the working clock for RTC 420. However, if SyncE is not available (e.g., in situations where the synchronization chain is broken), then processor 340 may select either local reference clock 430 or external clock 440 as the working clock for RTC 420.

[0052] FIG. 5 is a functional block diagram 500 of a clock servo 510 which can be implemented within the processor 330 in the slave device 310 of FIG. 3 in accordance with some embodiments. With reference to FIGS. 3, 4, and 5, clock servo 510 includes a PTP process engine 520, a combiner 530, a proportional-and-integral (PI) controller 550, and a frequency adjuster 460. Optionally, one or more low pass filters such as filters 542 and 544 can be included in clock servo 510 to improve accuracy or for other suitable purposes. Depending on embodiments, clock servo 510 and its components, individually or combined, may be implemented as hardware components that are included in or coupled to clock 410 (FIG. 4), or may be implemented as software components that are stored (e.g., in memory 335) and executed by processor 330.

[0053] PTP process engine 520 is coupled to transceiver 320 and processes PTP messages that are received by transceiver 320. Using suitable techniques, such as the PTP message exchange flow 200 discussed above, PTP process engine 520 may collect a plurality of timestamps (e.g., timestamps t _ls t ₂ , t ₃ , and t ₄ of FIG. 2) from the received PTP messages. Thereafter, combiner 530 adds dA (e.g., as filtered by low pass filter 542) to (ti-t ₂ ) to determine a time difference At, which is output to PI controller 550. In some embodiments, low-pass filter 544 filters the value of time difference At.

[0054] PI controller 550 is a well-known controller that includes a proportional part, an integral part, and a feedback loop with selected coefficients that enable a convergence speed and precision as a particular application requires. In some embodiment, controller 550 may further includes a well-known derivative part, or may only include the integral part. According to the present embodiments, PI controller 550 receives the time difference At between the master device and the slave device, and, based on the time difference At, generates an adjustment value for appropriate frequency adjustment of RTC 420.

[0055] PTP process engine 520 also outputs a time interval T _sync , which indicates the time interval between two successive Sync messages sent by the master device, to PI controller 550. Time interval T _sync may function as an indicator, when frequency synchronization is not reached, of how much time drift could occur between the clocks of the slave device and the master device. For example, for an RTC with an oscillator of 125 MHz with ± 50 ppm variation tolerance, if T _sync = 100 milliseconds, the time drift may be within ±5 microseconds. According to the present embodiments, time interval T _sync may be used as a sampling interval for PI controller 550.

[0056] As previously mentioned, frequency synchronization takes an important role in implementing clock synchronization between the master device and the slave device. Further, because frequency differences often vary with ambient temperature changes, supply voltage fluctuations, component degradations, etc., according to some embodiments, frequency synchronization between the master device and the slave device is prioritized over time synchronization. For example, frequency synchronization is performed prior to time synchronization in some embodiments. In order to achieve high clock synchronization accuracy and to allow for reduced clock synchronization traffic, a synchronization index is used by the present embodiments to indicate the precision of the frequency and time synchronization. The synchronization index is also used to control a state machine, which in turn controls the adjustment of RTC 420.

[0057] The calculation of the synchronization index and/or the state machine can be implemented as a software program to be stored (e.g., in memory 335) and executed by processor 330, or can be implemented on one or more hardware circuits (e.g., a state machine). Also, the state machine and its states are merely exemplary; the scope of the disclosure herein includes other suitable types of control mechanism. The state machine and the synchronization index are described in fuller detail below with regard to FIG. 6.

[0058] FIG. 6 is an illustration of an exemplary state machine 600 which can be implemented within the processor of FIG. 3 to control the clock servo 510 of FIG. 5 in accordance with some embodiments. State machine 600 includes three exemplary states, unlock state 610, acquire state 620, and lock state 630. State machine 600 also includes a default start state 605. In other embodiments, state machine 600 may include any number of suitable states. For example, a two-state state machine can be used instead, in which unlock state 610 and acquire state 620 are combined into one state. As mentioned above, state machine 600 is controlled by a synchronization index, which indicates a degree of synchronization between the clock of the master device and the clock of the slave device.

[0059] According to the present embodiments, the synchronization index is a statistical function (e.g., a monotonically increasing statistical function). In one embodiment, the statistical function is a root-mean-square error (RMSE) of one or more time differences At obtained from, for example, PTP message exchange flow 200 of FIG. 2. In another embodiment, the statistical function is a mean of absolute values of the one or more time differences At. The time differences indicate the degree of error in synchronization between the master and slave devices. For the following calculations with regard to the synchronization index, it is assumed that the path (i.e., link) delay is symmetrical, and the mean path delay is defined as dA = t _ms .

[0060] For those embodiments whose statistical function is the RMSE, let n be the sequence number of Sync messages received by the slave device, and N be the number of Sync message recently received (e.g., received within a specified time period or window), then the synchronization index can be represented as:

- S! = lCC(e ^f I C«> * > ^? 2 1 1¾ 4- I * e¾ {« J & *

(3)

wherein the error signal e(n) can be represented as:

e(n) = Δί(η) = ti(n) - t ₂ (n) + d _A (4)

[0061] In some embodiments, after normal connection (e.g., IEEE 1588 connection) is established, the slave device refreshes the synchronization index as every Sync message is received from the master device (e.g., at a time interval of T _sync ). Processor 330 in slave device 310 monitors the synchronization index and controls state machine 600 so that the state machine advances its state based on the synchronization index's value after each time the synchronization index is refreshed. Further, PI controller 550 selectively adjusts the frequency of the clock of the slave device through frequency adjuster 460 based on the monitoring. With reference to FIGS. 2-6, each state of state machine 600 is now described.

[0062] In start state 605, for example, when slave device 310 first starts to receive PTP messages from the master device, mean path delay dA is assigned to a predetermined value (e.g., zero), and state machine 600 enters unlock state 610.

[0063] In unlock state 610, slave device 310 is not in synchronization with the master device. Mean path delay dA retains its previous value and thus remains the same value. State machine 600 jumps to acquire state 620 unconditionally.

[0064] In acquire state 620, slave device 310 tries to achieve frequency synchronization with the master device. Therefore, mean path delay dA is not updated and instead remains the same value. PI controller 550 continuously adjusts the frequency of the clock of slave device 310 until the synchronization index is less than a minimum threshold (e.g., which represents a desired synchronization accuracy such as 100 nanoseconds). If PI controller 550 successfully brings down the synchronization index to less than the minimum threshold, state machine 600 jumps to lock state 630. However, if PI controller 550 fails to bring down the synchronization index to less than the minimum threshold before a timeout occurs, state machine 600 jumps back to unlock state 610.

[0065] In lock state 630, frequency synchronization between slave device 310 and the master device is achieved. Slave device 310 continues to send Delay Req messages (see FIG. 2) to the master device periodically to measure the propagation delay. Mean path delay dA is updated with the receipt of corresponding timestamps. In accordance with the present embodiments, the updated mean path delay dA is then used in a later synchronization index calculation. Slave device 310 also receives Sync messages (see FIG. 2) periodically to get time differences At between the clocks of the master device and slave device 310. Thereafter, PI controller 550 receives the time differences At and generates frequency adjustments accordingly. If the synchronization index becomes larger than a maximum threshold, slave device 310 has lost frequency synchronization with the master device, and therefore state machine 600 jumps back to unlock state 610. The maximum threshold may be a value that is relatively large as compared to the minimum threshold. In one embodiment wherein N=16, the maximum threshold is set to be 10,000 times the minimum threshold.

[0066] FIG. 7 is a flowchart 700 illustrating adjustment for the real-time counter

420 of FIG. 4 in accordance with some embodiments. To facilitate a better understanding, flowchart 700 is described with reference to FIGS. 3-7. In some embodiments, there are two ways to adjust RTC 420 for the slave device (e.g., slave device 310) to achieve synchronization. A first way is to adjust the time value of RTC 420 directly (e.g., through the time value input), and a second way is to adjust the frequency of RTC 420 by frequency adjuster 460 or by varying the voltage level on VCO 404. As a general principle, if the time difference between the slave and the master devices exceeds a predetermined value and thus is large (e.g., >1 second), then direct time value adjustment is used to achieve time synchronization with a minimum time. However, direct adjustment of time value of RTC 420 may cause a time discontinuity in the slave device, which may in turn adversely affect many applications. Therefore, if the time difference between the slave and the master devices is less than the predetermined value and thus acceptably small (e.g., <1 second), then frequency adjustment (e.g., through frequency adjuster 460) of RTC 420 is more desirable. With this general principle in mind, flowchart 700 may be implemented on the slave device to improve the time and frequency adjustment processes.

[0067] First, the slave device receives a plurality of Sync messages (710). Next, processor 330 calculates a time difference At and a synchronization index based on the techniques described above (720). Then, if the time difference At exceeds a predetermined value (e.g., one second), or if the synchronization index is larger than a maximum threshold so that state machine 600 is in unlock state 610, then processor 330 directly adjusts the time value of RTC 420 based on the time difference At. Otherwise, processor 330 only adjusts the frequency of RTC 420 (e.g., through PI controller 550 and frequency adjuster 460).

[0068] FIG. 9 is a schematic diagram of an implementation 900 of a portion of the RTC 420 used in some embodiments of the method 700. A register 906 in the counter 900 stores the value of the nanoseconds field of the RTC 420 and a register 908 stores an increment value. An adder 910 adds the value of the nanoseconds field to the increment value and provides the sum to first inputs of a mux 916 and a comparator 914. A subtracter 912 subtracts the sum from 10 ⁹ (i.e., the maximum possible value of the register 906) and provides the resulting difference to a second input of the mux 916. The comparator 914 compares the sum from the adder 910 to 10 ⁹ and generates a control signal for the mux 916. If the sum is less than 10 ⁹ , the mux 916 outputs the sum, which is written back into the register 906 through a mux 902 and flip-flop 904, thereby incrementing the counter 900 by an increment equal to the increment value in the register 908. If the sum is greater than 10 ⁹ , the mux 916 outputs the difference provided by the subtracter 912, thereby incrementing and wrapping around the counter 900 in accordance with the increment value in the register 908.

[0069] To directly adjust the counter 900's time (e.g., as done in step 750, FIG.

7), a clock servo 920 provides a time value 928 to the register 906 via the mux 902 and flip-flop 904, thereby overwriting the previous time value in the register 906. The clock servo 920 provides a control signal 926 to control the mux 902. The clock servo 920 may be an example of the clock servo 510 (FIG. 5) and may be implemented in software. (The seconds portion of the RTC 420 may be updated in an analogous manner.)

[0070] To adjust the frequency of the counter 900 (e.g., as done in step 740, FIG.

7), the clock servo 920 may provide an updated increment value 924 to the register 908, thereby overwriting the previous increment value in the register 908. In addition, the clock servo may adjust the frequency of the counter 900 by supplying a signal 922 to a digital-to-analog converter (DAC) 918, thereby adjusting a voltage input to the VCO 404. The output of the VCO 404 clocks the flip-flop 904 and thus determines how frequently the counter 900 is incremented. The VCO 404 and the increment value in the register 908 together determine the frequency (i.e., tick rate) of the counter 900. The combination of counter 900, DAC 918, and VCO 404 thus corresponds to the combination of RTC 420 and frequency adjuster 460 (FIG. 4) in accordance with some embodiments.

[0071] FIG. 8 is a flowchart 800 illustrating implementing synchronization over an asynchronous network in accordance with some embodiments. First, with reference to FIGS. 2-5, a plurality of PTP messages is exchanged between a master device and a slave device (e.g., as shown in FIG. 2), and the slave device (e.g., device 310, FIG. 3) thereby obtains a plurality of timestamps from the PTP message (810). Next, the slave device determines (e.g., by using processor 330 within the slave device 310, FIG. 3) one or more time differences (e.g., using equations 1 and 2) between a clock of the master device and a clock of the slave device based on the plurality of timestamps (820). Then, the slave device determines (e.g., by using processor 330) a synchronization index indicating a degree of synchronization between the clock of the master device and the clock of the slave device based on the one or more time differences (830). In some embodiments, the synchronization index is calculated further based on a mean path delay (e.g., d _A ). Further, the synchronization index is determined by a statistical function (e.g., a monotonically increasing statistical function) including, for example, a root-mean-square error of the one or more time differences (e.g., equation 4). Thereafter, the slave device synchronizes a frequency of the clock (e.g., RTC 420, FIG. 4) of the slave device with a frequency of the clock of the master device based on the synchronization index (840).

[0072] While the method 800 includes a number of operations that appear to occur in a specific order, it should be apparent that the method 800 can include more or fewer operations, which can be executed serially or in parallel. An order of two or more operations may be changed and two or more operations may be combined into a single operation. [0073] In this way, automatic time and frequency synchronization over an asynchronous network (e.g., an Ethernet network) may be achieved that increases clock synchronization accuracy, allows for reduced clock synchronization traffic, and decreases the processing load of a network processor.

[0074] Attention is now directed to details regarding operation of the PI controller 550 (FIG. 5). FIG. 10 is a schematic diagram of a PI controller 1000 that is an example of the PI controller 550 in accordance with some embodiments. A time difference At is provided to both a proportional path 1002 and an integral path 1004. The proportional path 1002 includes a buffer 1006 with a variable amplitude K _p . The integral path 1004 includes a buffer 1008 with a variable amplitude K the output of which is provided to an input of an adder 1012. The output of the adder 1012 is fed back to another input of the adder 1012 through a delay stage 1010. The integral path 1004 thus integrates successive time differences. The outputs of the paths 1002 and 1004 are combined by an adder 1014 to generate the adjustment value.

[0075] In some examples (e.g., Gigabit Ethernet or Fast Ethernet), the RTC 420 has a 125MHz free running clock as its work clock, giving a nominal increment value of 8ns. Limits are applied to the output of integral path 1004 of PI controller 1000 and to the final output of PI controller 1000. Amplitude limits depend on the frequency difference between the work clocks of the slave RTC and master RTC. For Ethernet, this frequency difference is within ±200ppm. Accordingly, to set the limits in this example, a maximum drift is defined:

MAX DINCR « 8ns x 200ppm = 1.6 x 10 ^"3 ns (5)

Accumulated and observed drift are then defined as:

Accum( n) = ObservedDr ift(n - 1) + K _t ^■ At(n) (6)

0, n = 0

MAX DINCR, Accum(w) > MAX DINCR

ObservedDrift(w) (?)

- MAX DINCR, Accum(w) < -MAX DINCR

Accum(w), else

The observed drift, which is the output of the integral path 1004, is thus limited by equation 7. [0076] The amplitude of the final output (Adjust Value, referred to as Adj(n) below) of PI controller 1000 is limited as follows. The output in the absence of a limit and the actual final output respectively are:

Sumout(«) = K _p ^■ At(n) + ObservedDrift(«) (8) 0, n = 0

MAX DINCR, Sumout(w) > MAX DINCR

Adj(«) = - ' (9)

- MAX DINCR, Sumout(w) < -MAX DINCR

Sumout(w), else

[0077] The current RTC increment value (e.g., as stored in the register 908, FIG.

9) is then found to be:

Incr(w) = Incr ₀ + Adj(n) ( 10) where Incr ₀ is the nominal value of the increment value (e.g., 8ns when the clock frequency is 125MHz).

[0078] In some embodiments, K _p is chosen to be proportional to the bandwidth of the corresponding loop filter, which corresponds to the change rate of the frequency of the local crystal oscillator (e.g., oscillator 402, FIG. 4). This rate of change is generally on the order of seconds or more. K _p thus may be selected to be capable of tracking frequency change within Is (i.e., 10 ⁹ ns) given the clock period of 8ns. Accordingly:

K _p * 2 x Incr ₀ / T _{freq change} = 2 x Incr ₀ / 10 ⁹ = 1.6 x 10 ^s (1 1)

[0079] The above parameters are expressed as floating point numbers but may be scaled for expression as fixed point numbers to implement PI controller 1000. To use fixed point numbers, the parameters should be scaled appropriately. As an example, for a fractional part bit width of 26, the parameters are multiplied by 2 ²⁶ . In some embodiments, double precision numbers are used to represent the parameters of the PI controller 1000, which may be implemented in hardware or software.

[0080] In the foregoing specification, the present embodiments have been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.