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Title:
AXI2WB BUS BRIDGE IMPLEMENTATION METHOD AND DEVICE, EQUIPMENT AND STORAGE MEDIUM
Document Type and Number:
WIPO Patent Application WO/2020/177283
Kind Code:
A1
Abstract:
An AXI2WB bus bridge implementation method and device, equipment and a storage medium, the method comprising the following steps: latching an AXI write address channel signal and an AXI write data channel signal; determining the number of WB transmissions required for current AXI write data according to the magnifications of AXI write data bit width and WB write data bit width (S530); for each one-time WB write operation, converting the AXI write address into a WB write address for the one-time WB write operations, converting the AXI write data into WB write data for the one-time WB write operations, and on the basis of the WB write address and WB write data, executing one-time WB write operations until the number of WB write operations reaches the number of WB transmissions required for the AXI write data (S540). The present method may implement the design of a high-speed cache-free AXI2WB bus bridge suitable for use inside of an FPGA.

Inventors:
YU JINHUI (CN)
Application Number:
PCT/CN2019/103674
Publication Date:
September 10, 2020
Filing Date:
August 30, 2019
Export Citation:
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Assignee:
INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO LTD (CN)
International Classes:
G06F13/40
Foreign References:
CN109828941A2019-05-31
CN103761208A2014-04-30
US20110276735A12011-11-10
Other References:
YANG, SHUNQI: "Research and Implementation of AMBA AXI4 BUS", RESEARCH AND IMPLEMENTATION OF AMBA AXI4 BUS (DISSERTATION), 24 December 2012 (2012-12-24), pages 20 - 28, XP009523012
GAYATHRI, M. ET AL.: "A SV-UVM Framework for Verification of SGMII IP Core with Reusable AXI to WB Bridge UVC", 2016 3RD INTERNATIONAL CONFERENCE ON ADVANCED COMPUTING AND COMMUNICATION SYSTEMS (ICACCS), 10 October 2016 (2016-10-10), XP032977007
Attorney, Agent or Firm:
UNITALEN ATTORNEYS AT LAW (CN)
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