STRUCTURE AND FABRICATION METHODS

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of

photomult ipliers .

2. Prior Art

Growing demand on photo detectors capable of detecting small intensity light fluxes and counting of single photons facilitated designing novel solid state detectors. One of them is the so-called silicon photomult iplier (SiPM) , which was claimed to be able to replace traditional photomult iplier tubes (PMT) . Among the possible areas of application of such detectors are high energy physics and nuclear medicine, in which brief detection of a small number of optical photons produced by a single γ-quantum in a scintillator crystal is required. Due to the features of their structure, SiPM have advantages of low operating voltage (<50 V) , fast response time (-100 ps) , small size, etc. However, currently available designs have drawbacks that limit their application (see below) .

A silicon photomult iplier (SiPM) is a device, which is in fact a large number of small SPAD (single photon avalanche diode) pixels, connected in parallel to a single output circuit. The detailed description of the conventional device is presented in several recent works which describe the front illuminated device. Its operation is based on the idea that very small SPAD pixels, if assembled in a dense, two- dimensional (2D) array, can be fired separately by a single photon each. Therefore, the overall signal output is proportional to the number of pixels fired at a time and the dynamic range of such 2D array of m elements is proportional to m.

One of the possible versions of a conventional front- illuminated structure is presented in Figure 1. The

structure of each pixel can be either a regular reach-through structure built on a p-type substrate (as it is shown in Figure 1), or the other possible version that does not require reach-through effect. For example, the structure built on n-type substrate with a buried p+ layer can be applied. The operating voltage is several volts above the avalanche threshold, which drives each pixel in a Geiger operation mode.

The structure in Figure 1 is built using a p-type substrate 1 with a thin epi layer 2. The Geiger mode

avalanche pixels are represented by the cathode diffusion region 3 and avalanche region 4. The substrate 1 serves as the anode. The junction depth 1 is small enough to maximize quantum efficiency in the short wavelength range. The photo- generated carriers can be collected either from the avalanche region 4 solely, or from both the avalanche region 4 and depleted intrinsic layer w.

Two pixels of SiPM shown in Figure 1 can be fired simultaneously by two different photons. To avoid optical crosstalk generated by hot carriers in avalanche region, the narrow trenches 10 are made between the pixels to block the photons generated within the avalanche area of one pixel against reaching the neighboring pixels. Oxide layer 11 with Si interface forms a reflective and isolation layer. The trenches may be filled with light absorptive material. Each pixel is loaded with a resistive layer 12 that quenches the avalanche when the pixel photocurrent exceeds a certain level. The quenching time is important parameter since it determines the pixel recovery time. The cathode metal contacts 20 from each pixel of SiPM are connected together and are hooked to the SiPM front-end electronics (not shown in Figure 1) . The back surface of SiPM is coated with metal 21 that serves as the anode contact.

Since the active volume of each pixel can be made very small (thin epi-layer d in Figure 1), the thermally generated noise current can be minimized to the level when it does not interfere with detection of optical photons.

Among the drawbacks of the conventional front- illuminated structures like shown in Figure 1, are the low quantum efficiency for the short wavelengths (<500 nm) and relatively small fill factor (FF) . The latter parameter value is limited by the requirement to reserve a part of active area space for the avalanche quenching resistive layer, contacts, and metal traces.

Back-illuminated versions of SiPM may provide

advantageous solutions since back-illuminated detectors have inherently higher quantum efficiency at the short wavelengths of light and FF is not limited by the resistive layer and metal traces, which are deposited opposite to the light incident surface of the device. The example of the back- illuminated SiPM integrated with Si drift detector is

described in reference 16 (see Figure 2) . However,

structures like shown in Figure 2 have a significant

drawback: These structures are designed on thick, bulk Si wafers and a significant amount of thermally generated carriers hinder detection of optical photons. BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a schematic cross-section of the

conventional front-illuminated SiPM.

Figure 2 is comprised of schematics of a typical back- illuminated Si drift detector integrated with SiPM.

Figure 3 is a schematic cross-section of the back- illuminated SiPM in accord with the current invention.

Figure 4 is a schematic cross-section of the alternative version of the back-illuminated SiPM with the buried n++ layer and via interconnections extending from the buried layer to the die front side.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The current invention proposes the back-illuminated SiPM structure that combines the advantages of the conventional structures described above, but at the same time is free of the conventional structure drawbacks.

Figure 3 shows schematically two pixels of the present invention design and describes the main features of the structure. SiPM is made using thin p-type Si substrate 1. The thin substrate may be made either with thinning in the middle of the process after the front side diffusion is done or starting with a thinned wafer - typically depending on the availability of suitable fabrication processes. The cathode diffusion 3 is made from the front side and is driven deep to make the junction close to the back surface of the die. In the other embodiment, the cathode can be made utilizing the buried n++ layer and via interconnections extending to the die front side (see Figure 4) . The buried layer 3 in Figure 4 can be manufactured applying molecular beam epitaxy. Via connections 7 in Figure 4 may be made using dry etch methods followed by via filling with a conductive material. The other traditional techniques for via interconnects may also be allied.

The avalanche p+ layer 4 is implanted from the backside, typically made using high energy ion implantation. For example, one can make a boron implantation ~2 microns deep into the surface from the backside using 1.1. MeV Boron beam. This layer may either touch the cathode n++ region 3 or may lay underneath it (isolated avalanche region structure) . The width of the avalanche layer and the intrinsic layer width w are both small (several microns) to minimize the volume of thermally generated carriers' collection. A thin, uniform anode diffusion region 6 is formed on the die backside. This region may be electrically connected with the die front side via the through p++ diffusion region 5 at the edge of the die. Oxide layer 11 on the die backside serves as active area anti-reflection layer and isolation layer. Trenches 10 between the pixels of SiPM are made on the die backside.

They should be deep enough to block the optical cross-talk generated inside the avalanche regions. The avalanche quenching resistive layer 12 is connected to each pixel and signals from each pixel are routed through the cathode metal contacts 20 to the front-end electronics. The common anode metal contact 21 may be made on the front surface to allow for the flip-chip die attach.

Alternatively, the common anode contact may be made on the edge of the die backside, which allows wire bonding of the anode to the substrate.

The structures in Figures 3 and 4 operate at a complete depletion condition. The depletion region penetrates the avalanche region 4 and extends through the "intrinsic" π region to the die backside. This structure is characterized with a high quantum efficiency value within the wide

wavelength range, including λ<500 nm. It also ensures fast response time and may provide larger fill-factor than front- illuminated structures of Figure 1.

In fabrication of back-illuminated SiPM shown in Figures 3 and 4, selected steps of the baseline process used for fabrication of the backlit photodiode array described in reference 17, the disclosure of which is hereby incorporated herein by reference, can be used. These include but are not limited to the deep n++ (cathode) and through p++ (anode) diffusion regions.

The depth of the trenches is made sufficiently deep to block all optical photons from penetration the avalanche region from neighboring pixels' avalanche regions.

In the preferred embodiments, the substrate is a p substrate, which may be near intrinsic. However the

conductivity types can be reversed for the devices in which the ionization rate for holes is higher than that for

electrons .

Thus while certain preferred embodiments of the present invention have been disclosed and described herein for purposes of illustration and not for purposes of limitation, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.