Technical Field of the Invention The present invention relates to a back substrate for an opto-electronic device module and to a module of opto-electronic devices. The invention further relates to method for manufacturing an opto-electronic device module.

Background to the Invention

Dye-sensitised Solar Cells (DSC's), Organic PV cells (OPV) and Copper Zinc Tin Selenide cells (CZTS) are examples of 'Third Generation' Photovoltaic (PV) devices, which are based on low cost materials and can be produced by using processing steps that are feasible for high-throughput manufacturing lines.

Dye Solar Cells were first developed in the early 1990's by Michael Gratzel and co-workers. The conversion efficiencies (the percentage of the incident light that is converted into electrical power) of laboratory-produced DSC's were rapidly improved to around 10%, but the presence of a liquid electrolyte layer based on an Iodine/Iodide solution made the development of feasible manufacturing processes and robust devices very challenging. This situation led to the pursuit of solid state dye-sensitised solar cells, in which the liquid electrolyte was replaced by a solid state amorphous hole- transport material such as 2,2',7,7'-Tetrakis-(N,N-di-4-methoxyphenylamino)-9,9'- spirobifluorene, commonly referred to as Spiro-OMeTAD. The replacement of the liquid electrolyte with Spiro-OMeTAD had the further advantage that solid state dye- sensitised solar cells could be manufactured in high volumes using roll-to-roll processing. It also meant that it became easier to deposit well-defined layer patterns using mature technologies such as printing. Solid state devices were also easier to seal and encapsulate than liquid DSCs.

As the research into Third Generation PV technology progressed, it was found that conversion layer materials such as dye sensitised metal oxides could be replaced by organo-metal (methyl ammonium lead halide) 'Perovskite' structures (hereinafter referred to as 'Perovskites'), and when solid state devices were produced with Perovskite based conversion layers and spiro-OMeTAD hole transport materials, conversion efficiencies of between 8 and 10% were demonstrated in 2012. It was subsequently found that conversion efficiencies could be increased to 12.3% by coating Perovskite absorbers onto an inert meso-porous AI2O3 scaffold. This eliminated the need for scaffolds of interconnected semiconducting particles such as the nano-porous T1O2 that was commonly used in liquid DSCs. This omission is advantageous because T1O2 pastes are typically sintered at temperatures of around 500 °C so that the T1O2 particles fuse together and become electrically interconnected. In contrast, inert AI2O3 scaffolds can be processed at moderate temperatures (<150 °C), which makes it possible to use common polymer films, such as polyethylene terephtalate (PET) and polyethylene naphtalate (PEN), as photo-anode carrier substrates.

In 2014, it was demonstrated that conversion efficiencies of up to 15.5% could be obtained by laminating a polymeric film comprising an embedded nickel grid electrode (used as the cathode) to a photo-anode substrate using a conductive adhesive (Advanced Materials, Volume 26, Issue 44, pages 7499-7504, (November 26, 2014). In this work, the photo-anode substrate comprised a Perovskite coated AI2O3 scaffold conversion layer, a hole-extraction layer based on Spiro-OMeTAD and an interlayer comprising Poly (3,4-ethylenedioxythiophene) Polystyrene sulfonate (PEDOT:PSS) provided between the hole-extraction layer and the conductive adhesive. A similar device design is known from European patent application EP2808913 Al that was filed by Tata Steel in 2013.

The various emerging solid-state device designs described above are commonly referred to as 'Hybrid' PV technologies, because the active layers comprise a hybrid of organic and inorganic materials. Some examples of Hybrid PV devices are:

- solid state Dye Solar Cells (sDSC s),

- mesoscopic solar cells (Meso-Superstructured Solar Cells or MSSC's),

- Perovskite/metal-oxide heterojunction solar cells,

- Perovskite/metal-oxide scaffold solar cells, and

'thin film' or 'flat junction' Perovskite solar cells, which are characterised by extremely thin absorber (ETA) layers. Despite the inherent practical and economic advantages of Hybrid PV technologies and the emergence of low-cost and high performance conversion layer materials such as the Perovskites that have led to much improved conversion efficiencies, the additional cost of the module device infrastructure is still a significant contributor to the total cost per Watt for a finished PV module, and therefore poses a potential barrier to the commercialisation of Hybrid PV technologies. Module device infrastructures typically include;

(i) the electrical circuit that collects and transports energised electrons from the anode in one cell to the cathode in another cell, and

(ii) the barrier layers that prevent the leaking of organic materials from the device and minimise the diffusion of atmospheric moisture and gasses into the device.

It is an object of embodiments of the invention to provide a cost-effective module device infrastructure for collecting current in opto-electronic devices.

It is another object of embodiments of the invention to provide a cost-effective infrastructure for interconnecting opto-electronic devices in series.

It is a further object of embodiments of the invention to provide a cost-effective infrastructure for encapsulating opto-electronic devices.

It is also an object of embodiments of the invention to be able to produce a module infrastructure using high volume manufacturing processes and economically feasible materials.

Summary of the Invention

According to a first aspect of the invention, there is provided a back substrate for an opto-electronic device module, the back substrate comprising on a surface thereof a plurality of opto-electronic devices, said opto-electronic devices comprising a photo- anode and a cathode, wherein the back substrate additionally comprises a pattern of conductors, which in use, (i) collect current from the photo-anode, (ii) collect current from the cathode and (iii) provide an electrical interconnection between the photo- anode of one opto-electronic device and the cathode of an adjacent opto-electronic device. The pattern of conductors provided on the back substrate may be sub-divided into three portions, and each portion shall be named according to the function it performs in the device. For instance, the portion of the conductor pattern that collects current from the photo-anode or anode shall be referred to as the "anodic conductor", the portion of the pattern that collects current from the cathode shall be referred to as the "cathodic conductor" and the portion of the conductor pattern that interconnects the anodic conductor of a first opto-electronic device to the cathodic conductor of a second opto-electronic device shall be referred to the "interconnector".

In a preferred embodiment of the invention, current may be collected from the photo-anode via a conductive bonding material which is in electrical contact with the anodic conductors provided on the back substrate. The back substrate may comprise a glass carrier substrate that is preferably in the form of a glass pane. Alternatively, the back substrate may comprise a polymeric film carrier substrate. Preferred polymeric films include but are not limited to polyethylene terephthalate (PET) and Polyethylene naphthalate (PEN).

The back substrate may comprise a diffusion barrier layer. The diffusion barrier layer may be provided on a surface of the carrier substrate facing the opto-electronic devices, and the pattern of conductors may be provided on the diffusion barrier layer. It is particularly preferred to provide a diffusion barrier layer when the back substrate comprises a polymeric film carrier substrate, since this enables improved encapsulation of the module device.

The diffusion barrier layer may comprise one or more inorganic layers, one or more organic layers or a mixture of inorganic and organic layers.

A barrier protection layer may be provided on a surface of the diffusion barrier layer that is facing the opto-electronic devices. When the back substrate comprises the barrier protection layer, the pattern of conductors may be provided on the barrier protection layer instead of on the diffusion barrier layer.

The conductors may comprise either a metal or a metal alloy. Alternatively, the conductors may comprise either an allotrope of carbon or an organic conductor material. The conductors may be provided either as a single layer or as a multilayer structure. The photo-anode of each opto-electronic device comprises a conversion layer, the dimensions of which define a conversion region on the back substrate. Cathodic conductors are preferably located within or matched to the conversion region.

In a preferred embodiment, anodic conductors associated with a first opto- electronic device may be provided adjacent to at least one side of the conversion region associated with that device. When the conversion region is substantially square or rectangular in shape, the anodic conductors may be provided adjacent to at least two sides of the conversion region so as to maximise power output. For instance, if the conversion region is rectangular in shape, it is preferable to provide two parallel anodic conductor fingers that each extend along the longitudinal sides of the conversion region, in order to minimise the voltage loss.

It is particularly preferred that anodic conductors associated with a first optoelectronic device are provided adjacent to and in parallel with the anodic conductors associated with a second opto-electronic device, e.g. the anodic finger conductors of one pattern may be arranged adjacent to and in parallel with anodic finger conductors associated with a second opto-electronic device. In this way, voltage losses are minimised, thereby increasing the maximum power output.

In a second conductor pattern, anodic conductors associated with a first optoelectronic device substantially surround the conversion region associated with that device, to define a gap through which an interconnector is provided that interconnects the cathodic conductor, located within or matched to the conversion region, to anodic conductors that are associated with a second opto-electronic device. The conversion region may be substantially square or rectangular in shape and the anodic conductors of the first opto-electronic device may surround at least three sides of the conversion region. The anodic conductors may additionally surround at least a part of the fourth side of the conversion region.

In a third conductor pattern, anodic conductors associated with a first optoelectronic device surround the conversion region associated with that device and cathodic conductors, located within or matched to the conversion region, are connected through an interconnector to anodic conductors associated with a second optoelectronic device, via an insulating bridge, that separates the interconnector from the anodic conductors associated with the first opto-electronic device. In a fourth conductor pattern the back substrate comprises a first row of conversion regions and a second row of conversion regions, and anodic conductors are shared between at least two adjacent conversion regions in the same row to electrically connect the opto-electronic devices within the first row in parallel (so that they have the same voltage). The anodic conductors of conversion regions in the first row are then connected to the cathodic conductors in the second row through interconnectors, either by defining gaps in the anodic conductors of the first row (as described in the second conductor pattern) or by providing insulating bridges to separate the interconnectors from the anodic conductors of the first row (as described in the third conductor pattern).

In a fifth conductor pattern, the back substrate again comprises a first row of conversion regions and a second row of conversion regions, and anodic conductors are shared between at least two adjacent conversion regions in the same row to electrically connect the opto-electronic devices within the same row in parallel (so that they have the same voltage), but here the conversion regions of the first row may not be linear with those in the second row, but off- set by half of the width of the conversion region. This is advantageous because it simplifies the conductor pattern. Again, the interconnections are made by defining gaps in the anodic conductors of the first row (as described in the second conductor pattern) or by providing insulating bridges to separate the interconnectors from the anodic conductors of the first row (as described in the third conductor pattern).

Insulating bridges used in accordance with the present invention may comprise a bypass diode that is electrically connected to both the interconnector and to the anodic conductors associated the first opto-electronic device.

According to a second aspect of the invention there is provided an opto- electronic device module comprising:

- the back substrate according to the first aspect of the invention, wherein the photo-anode or anode comprises:

- a transparent carrier substrate

- a transparent conductive coating

- a blocking layer

- a conversion layer

- a hole extraction layer - a first conductive interlayer

- a second conductive interlayer, and

- a pattern of first and second conductive adhesives provided on the back substrate.

The transparent carrier substrate of the anode or photo-anode may comprise glass or a polymeric film. The transparent carrier substrate of the anode or photo-anode and the carrier substrate of the back substrate may comprise the same material, for instance they may both comprise glass. This may be preferred because glass has a high transparency to light and both substrates will have the same coefficient of thermal expansion, meaning that the module will not endure thermal stress when exposed to temperature cycling. In addition, the use of glass back and anode or photo-anode carrier substrates means that an anodic diffusion barrier and the back substrate diffusion barrier layer can be omitted from the opto-electronic device. With regard to the anode or photo-anode, the use of a glass carrier substrate also means that the transparent conductive coating and the blocking layer can be deposited in a cost-effective way, for example by using an atmospheric CVD process.

The transparent conductive coating, e.g. FTO or ITO, may be provided on the transparent carrier substrate or onto an anodic diffusion barrier that has been provided onto the transparent carrier substrate of the anode or photo-anode substrate. An anodic diffusion barrier may be provided if the transparent carrier substrate is a polymeric film.

When the anode or photo-anode comprises the anodic diffusion barrier on the device facing side of the transparent carrier substrate and the back substrate comprises the diffusion barrier, an edge sealant may be used to bond to both the anodic diffusion barrier and the diffusion barrier on the back substrate. This has been found to minimise the ingress of moisture and gasses into module device and prevent leakage of organic components out of it.

The blocking layer, provided between the transparent conductive coating and the conversion layer, prevents or at least substantially reduces the occurrence of energised electrons migrating back into the conversion layer from the transparent conductive coating. The blocking layer may comprise a dense metal oxide such as Sn0 ₂ or Ti0 ₂ . The conversion layer, which absorbs light to generate a plurality of energised electrons and electron holes, may comprise Perovskites or a dye- sensitised metal oxide, e.g. dye-sensitised T1O2. The hole-extraction layer is typically provided on top of the conversion layer so that it covers the surface of the conversion layer, which may be porous, for instance, when the conversion layer comprises nano-porous T1O2.

The hole-extraction layer may comprise a hole-transport material such as spiro- OMeTAD, which facilitates the migration of electron holes away from the conversion layer. A first conductive interlayer may be provided between the hole-extraction layer and a conductive adhesive.

The first and second conductive interlayers may be substantially transparent or at least semi-transparent in order to maximise the amount of light that passes through these layers, which can be reflected back towards the conversion layer by the pattern of conductors if these conductors contain metals. The first conductive interlayer preferably comprises a conductive polymer such as PEDOT:PSS. First conductive interlayers comprising PEDOT:PSS have been found to improve the electrical contact between the hole extraction layer and the first conductive adhesive.

The second conductive interlayer is provided in an interconnecting region located between two adjacent opto-electronic devices. The second conductive interlayer improves the electrical contact between the blocking layer and a second conductive adhesive located in the interconnecting region. The first and second conductive interlayers preferably comprise the same materials so that they can be deposited together in a single process step.

The first conductive adhesive may comprise a conducive polymer such as PEDOT:PSS and an adhesive material, for instance an adhesive material based on acrylic compounds. So that a greater proportion of reflected light can reach the conversion layer, the first conductive adhesive is preferably transparent or semi- transparent to light. The second conductive adhesive may comprise the same materials as the first conductive adhesive, which is advantageous because this enables the first and second conductive adhesives to be deposited in a single process step onto the back substrate. A pattern of an insulating spacer or adhesive material may be provided on the back substrate to mechanically bond the anode or photo-anode and the back substrate together.

The cathode may be provided in the form of a metallic grid or mesh, for example a nickel grid or a copper mesh. The grid or mesh cathode may be embedded in a polymer film, e.g. PET or PEN. Alternatively, the cathode may be in the form of a coated metal substrate, for example a nickel coated steel sheet.

In a preferred embodiment of the invention, there is provided a tandem optoelectronic device module which comprises an opto-electronic device module according to the second aspect of the invention and a second opto-electronic device module. The opto-electronic device module according to the second aspect of the invention may be laminated to the second opto-electronic device module so that the incident light is passing through both devices, maximizing the amount of electricity that is harvested from the light. The tandem opto-electronic device module may, as appropriate, incorporate any or all of the features described in relation to the back substrate according to the first aspect of the invention.

In another embodiment, the opto-electronic device module according the second aspect of the invention is electrically connected to one or more capacitor devices located between the transparent carrier substrate of the anode or photo-anode and the back substrate. The capacitor devices are charged by the opto-electronic device module, so that a burst of energy can be released when an electric device connected to the external contacts of the opto-electronic device module is engaged.

According to a third aspect of the invention, there is provided a method for manufacturing an opto-electronic device module according to the second aspect of the invention, wherein the first and second conductive adhesives and the insulating adhesive are cured in a single curing step. The method for manufacturing the optoelectronic device according to the second aspect of the invention may, as appropriate incorporate any or all of the features described in relation to the back substrate according to the first aspect of the invention, and any or all of the features described in relation to the opto-electronic device according to the second aspect of the invention.

According to a fourth aspect of the invention there is provided a back substrate for an opto-electronic device module, the back substrate comprising on a surface thereof a plurality of opto-electronic devices, said opto-electronic devices comprising an anode and a cathode, wherein the back substrate additionally comprises a pattern of conductors, which in use, (i) collect current from the anode, (ii) collect current from the cathode and (iii) provide an electrical interconnection between the anode of one optoelectronic device and the cathode of an adjacent opto-electronic device. The back substrate according to the fourth aspect of the invention may, as appropriate incorporate any or all of the features described in relation to the back substrate according to the first aspect of the invention, and any or all of the features described in relation to the optoelectronic device according to the second aspect of the invention and/or in relation to method according to the third aspect of the invention.

Detailed Description of the Invention

In order that the invention may be more clearly understood a number of embodiments thereof will now be described, by way of example only, with reference to the accompanying drawings, of which:

Figure 1A is a cross-sectional view of a module device according to a first embodiment of the invention.

Figure 2A is a top view of a back substrate according to the first embodiment of the invention.

Figure 2B is a cross-sectional view of the module device through line A-A shown in Figure 2A (identical to Figure 1 A).

Figure 3A is a top view of a back substrate according to a second embodiment of the invention.

Figure 3B is a cross-sectional view of the module device through line A-A shown in Figure 3 A.

Figure 4A is a top view of a back substrate according to a third embodiment of the invention.

Figure 4B is a cross-sectional view of the module device through line A-A shown in Figure 4A. Figure 5A is a top view of a back substrate according to the third embodiment of the invention (identical to Figure 4A, except now line A-A passes through the centre of the back substrate).

Figure 5B is a cross-sectional view of the module device through line A-A shown in Figure 5 A.

Figure 6A is a top view of a back substrate according to a fourth embodiment of the invention.

Figure 6B is a cross-sectional view of the module device through line A-A shown in Figure 6A.

Figure 7 is a top view of a back substrate according to the third embodiment if the invention showing opaque and semi-transparent cathodic conductors.

Figure 8 is a top view of a back substrate according to a fifth embodiment of the invention.

Figure 9 is a top view of a back substrate according to a sixth embodiment of the invention.

Figure 1 shows a laminated hybrid photovoltaic module in which a photo-anode substrate 20 of a left-hand cell 40 is connected to cathodic conductors 109c of the right- hand cell 60 via an interconnecting region 50. The photo-anode substrate 20 comprises a transparent carrier substrate 101 based on glass or on a polymer film, an anodic diffusion barrier 102, a transparent conductive coating 103, a blocking layer 104 located between the transparent conductive coating 103 and a conversion layer 105, with a hole extraction layer 106 provided adjacent to the conversion layer 105. The 'length' of the transparent conductive coating in a cell, running from one interconnection with a neighbouring cell to another, is an important parameter that contributes significantly to the cell's internal resistance; Its direction is indicated in Figure 1 by the double-headed arrow labelled 'L' for the left-hand cell (40). A first conductive interlay er 107 is provided between and in electrical contact with the hole-extraction layer 106 and a first conductive adhesive 108. In interconnecting region 50, a second conductive interlayer 113 is provided between and in electrical contact with a second conductive adhesive 115 and the blocking layer 104. Figure 1 additionally shows a back substrate 30. The back substrate 30 comprises a carrier substrate 112 based on glass or on a polymer film, a diffusion barrier layer 111 provided thereon and a barrier protection layer 110 for protecting the diffusion barrier 11. Figure 1 additionally shows that the transparent conductive coating 103 of the left-hand cell 40 is connected to the cathodic conductor 109c of the right-hand cell by interconnecting region 50. The interconnecting region 50 comprises a second conductive interlayer 113, a second conductive adhesive located between an anodic conductor 109a and the second conductive interlayer 113, and an interconnector 109b. An insulating spacer or adhesive 114 is provided on the back substrate 30 for strengthening the bond between the photo-anode substrate 20 and the back substrate 30, and to electrically insulate cells 40 and 60 from their surroundings. A top view of the back substrate 30 of the first embodiment of the invention is shown in Figure 2A and a cross-sectional view of the module device is shown in Figure 2B. These figures show a photo-anode substrate 220, a back substrate 230, a left hand cell, 240, an interconnection region 250, a right hand cell 260, a transparent carrier substrate 201, an anodic diffusion barrier 202, a transparent conductive coating 203, a blocking layer 204, a conductive coating 203, a conversion layer 205, a hole extraction layer 206, a first conductive interlayer 207, a first conductive adhesive 208, an anodic conductor 209a, an interconnector 209b, a cathodic conductor 209c, a barrier protection layer 210, a diffusion barrier layer 211, a carrier substrate 212, a second conductive interlayer 213, an insulating spacer or adhesive 214 and a second conductive adhesive 215. Figures 3 A and 3B show a second embodiment of the invention in which for cells X, Y and Z a photo-anode substrate 320 comprises a transparent carrier substrate 301, which is preferably made of glass or a polymeric film. An anodic diffusion barrier 302 is deposited onto the transparent carrier substrate 301 and a transparent conductive coating 303, for instance made of FTO or ITO, is provided on the anodic diffusion barrier 302. A conversion layer 305 is provided between the blocking layer 304 and a hole-extraction layer 306 adjacent to the conversion layer 305. A first conductive interlayer 307 is provided between the hole-extraction layer 306 and a conductive adhesive 308. The conductive adhesive 308 is provided adjacent to and in electrical contact with the cathodic conductor 309c. The back substrate 330 comprises a barrier protection layer 310, a diffusion barrier layer 311 and a transparent carrier substrate 312 adjacent to the diffusion barrier layer 311. The anodic conductors 309a associated with cells X, Y and Z are located adjacent to the barrier protection layer 310 and are in electrical contact with and collect current from the transparent conductive coatings 303 via the second conductive interlay er 313 and the second conductive adhesive 315 located in the interconnecting region 350. As shown in Figure 3 A, the anodic conductors 309a of device X are in the form of fingers that extend along each longitudinal side of the cathodic conductor 309c associated with cell X. It can also be seen from Figure 3 A that the anodic conductor fingers 309a are interconnected to a cathodic conductor 309c of an adjacent cell, e.g. cell Y, via interconnector 309b.

Since the conductor pattern 309 is deposited on the back substrate 330 together with the cathodic conductors 309c in a co-planar complementary pattern, and because the anodic conductors and the cathodic conductors comprise the same material, the cathodic conductors may be deposited co-currently in a single processing step. In addition, if the conductor pattern 309 of the present invention comprises metals, it will reflect light and therefore photons that have passed through the conversion layer 305 may be reflected back into the conversion layer 305, thereby increasing the overall efficiency of the device. Similarly, when the second interlayer 313 and the second conductive adhesive 315 comprise semi-transparent materials, e.g. PEDOT: PSS, a portion of the angular incident light entering the device in the interconnecting region 350 may be reflected back to the conversion layer 305. In contrast, conventional device designs typically have current collectors and bus bars that are provided directly onto a transparent conductive coating of a photo-anode substrate, resulting in reflection of incident light back out of the device, away from the conversion layer. Moreover, angular light will also be blocked from reaching the conversion layers.

The voltage loss that is incurred in a transparent conductive coating, which typically acts as an electrode in an opto-electronic device, has a significant influence on the overall performance of the opto-electronic device. For opto-electronic devices of the present invention, that generate a maximum power point current density of 10 mA/cm ² and comprise a transparent conductive coating 303 having a sheet resistance of 10 Ohm/sq, it has been found that the voltage loss incurred in the transparent conductive coating 303 of the photo-anode 320 can be limited to 300 mV when the anodic conductor fingers 309a are provided either side of a conversion region having a length (L) dimension of 49 mm or less. It has also been found that the voltage loss can be limited to 200 mV when the conversion region has a length dimension of less than 40 mm and that the voltage loss can be reduced to 100 mV when the conversion region has a length dimension of less than 28 mm. By providing anodic conductors 309a adjacent to each longitudinal side of the cathodic conductor 309c, the voltage loss in the transparent conductive coating 303 can be reduced by approximately 75 % compared to the voltage loss incurred in the design of the first embodiment, where only one anodic conductor 309a is provided adjacent to a longitudinal side of the cathodic current collector 309c, which is shown in Figures 2A and B. Figures 4A and 4B show a laminated hybrid photovoltaic device module according to a third embodiment of the invention. In Figure 4B, line A-A does not pass through the interconnect regions and for this reason interconnect 409b is not visible in Figure 4B. For cells X, Y and Z the photo-anode substrate 420 comprises in sequence; a transparent carrier substrate 401, an anodic diffusion barrier 402, a transparent conductive coating 403, a blocking layer 404, a conversion layer 405, a hole-extraction layer 406, a first interlayer 407, a first conductive adhesive 408 and a conductor 409. The photo-anode substrate 420 is provided on a back substrate 430, which itself comprises a transparent carrier substrate 412, a diffusion barrier layer 411 and a barrier protection layer 410. In the interconnecting regions 450 located between adjacent photovoltaic devices, a second conductive adhesive 415 is provided adjacent to an anodic conductor 409a. A second conductive interlayer 413 is provided on the blocking layer 404. The interconnecting region 450 also comprises insulating spacers or adhesives 414 that are provided on the back substrate 430 for strengthening the bond between the photo-anode substrate 420 and the back substrate 430. As shown in Figure 4A, the anodic conductors 409a associated with a first cell

(Y) substantially surround the cathodic conductors 409c of the same cell (Y), to define a gap through which an interconnector 409b is provided that connects the cathodic conductor 409c of cell Y to the anodic conductors 409a of an adjacent cell, in this case, cell X. For opto-electronic devices of the present invention that generate a maximum power point current density of 10 mA/cm ² and comprise a transparent conductive coating 403 having a sheet resistance of 10 Ohm/sq, it has been found that voltage losses in the transparent conductive coating 403 can be reduced significantly when the anodic conductors 409a have a grid-like pattern and substantially surround the conversion region as described above. In this configuration, it was found that the voltage losses incurred in the transparent conductive coating 403 can be limited to 300 mV if the conversion region has a length (L) dimension of less than 92 mm. It was also found that that voltage losses incurred in the transparent conductive coating can be limited to 200 mV when the when the conversion region has a length (L) dimension of less than 75 mm, and to 100 mV when the conversion region has a length dimension of less 53 mm. By providing anodic conductors 409a that substantially surround the cathodic conductor 409c, the voltage loss in the transparent conductive coating 403 can be reduced by approximately 70 % compared to the voltage loss incurred in the design of the second embodiment, where two parallel anodic conductors 409a are provided adjacent to longitudinal sides of the cathodic conductor, as shown in Figures 2A and 2B.

Figures 5A and 5B show a photo-anode substrate 520, a back substrate 530, an interconnection region 550, a transparent carrier substrate 501, an anodic diffusion barrier 502, a transparent conductive coating 503, a blocking layer 504, a conversion layer 505, a hole extraction layer 506, a first conductive interlayer 507, a first conductive adhesive 508, an anodic conductor 509a, an interconnector 509b, a cathodic conductor 509c, a barrier protection layer 510, a diffusion barrier layer 511, a carrier substrate 512, a second conductive interlayer 513, an insulating spacer or adhesive 514 and a second conductive adhesive 515. Unlike Figure 4B, line A-A of Figure 5B passes through the interconnect regions and therefore interconnect 509b is visible in Figure 5B.

Figure 6B shows a laminated hybrid photovoltaic device module according to a fourth embodiment of the invention. According to this embodiment, the photo-anode substrate 620 comprises a transparent carrier substrate 601, an anodic diffusion barrier 602, a transparent conductive coating 603, a blocking layer 604, a conversion layer 605, a hole-extraction layer 606, a first conductive interlayer 607, and a first conductive adhesive 608. The back substrate 630 comprises a transparent carrier substrate 612, a diffusion barrier layer 611 and a barrier protection layer 610. As shown in Figure 6A, the anodic conductors 609a associated with cell Y surround the cathodic conductor 609c of the same cell (Y). The cathodic conductors 609c of cell Y are connected through an interconnector 609b to the anodic conductors 609aassociated with an adjacent cell, e.g. cell X, via an insulating bridge 616, which separates the interconnector 609b from the anodic conductors 609a of cell Y. This enables the anodic conductors 609a to surround the cathodic conductors 609c in their entirety, and thus advantageously reducing the effective resistance of the anodic conductors 609a associated with each device. The insulating bridge 616 may comprise a bypass diode (not shown) that is electrically connected to both the anodic conductors 609a and the interconnector 609b of the opto-electronic device (and thus also to the cathodic conductor 609c associated with that device). This enables a malfunctioning cell to be excluded ('bypassed') from the electrical circuit of the module device. Figure 6B shows the cross-section of Figure 6A through the centre of the back substrate 630, which is indicated by line A-A in Figure 6 A.

Figures 7A and 7B show patterns of conductors according to the third embodiment of the invention, which comprise opaque cathodic conductors 709c (in Figure 7A) and semi-transparent grid cathodic conductors 709c (in Figure 7B). In both Figures 7A and B, the cathodic conductors 709c are deposited in the shape of a square, so that the length (L) of the cell is equal its width (W). Anodic conductors 709a substantially surround the cathodic conductors 709c to define a gap through which an interconnector 709b is provided that connects the anodic conductor 709a of one cell to the cathodic conductor 709c of an adjacent cell.

Figure 8 shows a conductor pattern design according to a fifth embodiment of the invention. In this design the back substrate comprises a first row of conversion regions and a second row of conversion regions. The anodic conductors 809a are gridlike and are shared between the conversion regions located within the same row to electrically connect these regions in parallel. According to this design, the cathodic conductors 809c of the conversion regions in the first row are connected to the anodic conductors 809a of the conversion regions in the second row through interconnectors 809b by defining gaps in the anodic conductors of the first row (as in the third embodiment) or alternatively by providing insulating bridges to separate the interconnectors from the anodic conductors of the first row (as in the fourth embodiment).

Figure 9 shows a conductor pattern according to a sixth embodiment of the invention and is similar to the design shown in Figure 8. In this design the conversion regions in the first row are not linear with those in the second row, but off-set by half of the conversion region width. Figure 9 shows an anodic conductor 909a, an interconnector 909b and a cathodic conductor 909c. This "off-set" design is advantageous because it simplifies the anodic conductor 909a pattern. EXAMPLE 1

To demonstrate the photovoltaic module device of the present invention, three photovoltaic module devices, based on the design according to Figure 1, were produced having different layer stack arrangements in the interconnecting region 50. Device 1

A glass substrate was used which functioned as both the transparent carrier substrate 101 and the anodic diffusion barrier 102. A 10 Ohm/sq FTO coating was deposited by a CVD process as the transparent conductive coating 103; A dense Sn0 ₂ coating (thickness -100 nm) was subsequently deposited onto this FTO coating to function as the blocking layer 104, also by a CVD process. The transparent conductive coating 103 and the blocking layer 104 were interrupted in the interconnection region 50 by a laser ablation process, to provide electrical insulation between cell 40 and cell 60.

A Ti0 ₂ containing paste (DSL18 RT, Dyesol) was then screen-printed on the blocking layer 104 and sintered at 500°C for 150 seconds in an infrared (IR) oven to obtain a nano-porous T1O2 layer. The dry film thickness of the sintered Ti0 ₂ layer was measured to be around 2 μπι. This sintered Ti0 ₂ layer was then immersed in a dye solution containing an organic dye (0.5 mMol of D102 (Mitsubishi Paper Mills Ltd) in a 1 : 1 mixture of tertiary butanol and acetonitrile). The coated glass substrate was immersed in the dye solution for 60 minutes at room temperature and then rinsed with acetonitrile to remove any excess dye. The coated glass substrate was then immersed in isopropyl alcohol (IP A) for 10 minutes and rinsed again with acetone to form the dye-sensitised TiC conversion layer 105.

A Hole Transport Material (HTM) solution containing spiro-OMeTAD (Luminescence Technology Corp.) in chloro-benzene (225mg/ml) was then prepared, to which 47 μΐ of a LiN(S02CF ₃ )2 stock solution (170 mg/ml in acetonitrile) and 22 μΐ of tert-butyl pyridine were added. 50 μΙ_, of this HTM solution was subsequently applied on the conversion layer 5. The HTM solution was allowed to penetrate the pores of the dye-sensitised T1O2 conversion layer 5 for 60 seconds before the excess was removed using a spin coater, to form a hole extraction layer 106 on the conversion layer 105, with a dry film thickness of -0.2 μπι.

A first conductive interlayer 107 based on PEDOT:PSS was then provided on the hole extraction layer 106 to improve the electrical contact between the hole extraction layer 6 and the conductive adhesive 108. In this example, a bespoke organic PEDOT:PSS solution has been used to form the interlayer 107. This 'dry' (<1% water) PEDOT:PSS ink was bar-coated on the surface of the hole extraction layer 106 at a wet film thickness of 45 μπι, and thereafter exposed to a temperature of 75 °C for 12 minutes in order to remove the solvents. It is thought that using a dry PEDOT:PSS formulation as the interlayer 107 is advantageous because the spiro-OMeTAD is not chemically stable when exposed to water.

A sample of the bespoke dry PEDOT:PSS ink was diluted with IPA (1 : 1 w/w) and this formulation was subsequently coated directly onto the blocking layer 104 in the interconnect region 50, to form the second interlayer 113 that functions as a 'contact layer' for the second conductive adhesive 115 in Device 1 (Table 1). Device 2

Device 2 was produced in the same way Device 1 except that a silver paste (AR Components) was applied to the blocking layer 4 in the interconnecting region (50) and subsequently dried to form the second conductive interlayer 113, which acts as an opaque metallic 'contact layer' for the second conductive adhesive 115. Device 3

Device 3 was produced in the same way as Device 1, except that no second interlay er 113 was applied to the blocking layer 104 in the interconnecting region 50. Consequently this device does not have a contact layer in the interconnecting region.

Devices 1-3 were laminated onto a back substrate 30 according to the present invention. 'Epimesh 300s', a product from Epigem Ltd, was used. This is a flexible transparent electrode, comprising a transparent polymer (PET) film that functions as the carrier substrate 112 and having two embedded metallic mesh conductors (consisting of electroplated Nickel and having a line width of 5 μπι, a thickness 5 μπι, in a square grid with a pitch of 300 μπι).

The material used for both the first and second conductive adhesive 108 and 115 was prepared by mixing a PEDOT:PSS ink (EL-P-3145, Agfa) with an acrylic adhesive (Styccobond F46) with in a 1.5: 1 ratio by weight. This mixture was stirred for approximately two minutes and then subjected to a low pressure environment to remove entrapped air. The transparent conductive adhesive was then deposited selectively onto the metallic mesh conductors of the back substrate 30, to form layers 108 and 115, in an identical pattern to that of the interlay ers 107 and 113 that were already deposited onto the photo-anode substrate 20 earlier. This applied transparent conductive adhesive pattern had a wet film thickness of 90 microns.

The back substrate 30, coated with the layer of the transparent conductive adhesive (108 and 115) was then subjected to a 60°C heat treatment in a convection oven for fifteen minutes to remove any low boiling point solvents. The temperature was then increased to 120°C for five minutes to remove the higher boiling solvents in the transparent conductive adhesive (108 and 115). After curing, the transparent conductive adhesive (108 and 115) exhibited a bulk conductivity of around 0.5 S/cm.

The back substrate 30, comprising the cured transparent conductive adhesive (108 and 115), was then laminated (at room temperature) onto the coated photo-anode substrate 20, such that the pattern of the first conductive adhesive 108 overlapped that of the first conductive interlay er 107 in the cell regions (40 and 60) and the interconnecting conductive adhesive 115 overlapped the second inter layer 113 in the interconnecting region 50. In the case of Device 3, there is no second inter layer, so here the interconnecting conductive adhesive 115 is in direct contact with the blocking layer 104 of the photo- anode substrate 20 in the interconnecting region 50.

The individual performances of the first and second photovoltaic cells (40 and 60) of Devices 1-3 were assessed by taking their I-V (current-voltage) measurements. The performance of the modules (comprising of cell 40, interconnecting region 50 and cell 60), produced by interconnecting these cells as described above, was also measured. A Newport Oriel IKW Large Area Light Source Model 9119X solar simulator and a BoTest LIV SMU source meter were used to characterize the performance of the individual cells and modules. Table 1 shows the measured performance characteristics and Power Conversion Efficiencies (PCE) of the individual cells 40 and 60, which are given in the first two rows for every device, and the measured performance characteristics and PCE of the module devices formed by the two cells connected in series via the interconnecting region 50.

Table 1

The results show that Device 1, where an organic PEDOT:PSS based contact layer was deposited as the second interlayer 113, has a Fill Factor of 0.39 for the interconnected device. This is better than the Fill Factor of 0.35 measured for the interconnected Device 2, where the second interlay er 113 is a metallic contact layer. The Fill Factor of a photovoltaic device is a measure of its internal resistance, so the Device 1 module shows a lower internal resistance than the Device 2 module. The individual cells of Device 2 have a lower Fill factor than those of Device 1, so this also contributes to a higher internal resistance in the module. However, the data demonstrate clearly that the current collection for the transparent conductive coating 103 through the blocking layer 104 of a photo-anode substrate 20 can be provided by a conductor 109a located on the back substrate, by electrically connecting this conductor 109a to the transparent conductive coating 103 through the second interlay er 113 and the second conductive adhesive 115.

Device 3, which has no second interlayer 13 in its interconnection region 50, shows a Fill Factor of 0.28 for the interconnected device, pointing at an ineffective electrical contact in the interconnect region 50. Here, the Fill Factors of the individual cells were higher than that of the interconnected device, so this shows that without a second interlayer 13, an efficient interconnection between the two cells has not been achieved.

EXAMPLE 2

To demonstrate the feasibility of producing back substrates 30 according to the present invention, and in particular the feasibility of depositing a pattern of conductors

109 onto a diffusion barrier layer 111, six back substrates 30 were prepared as follows; In a first step, a PEN film carrier substrate 112 (Teonex Q65HA) was coated with a transparent A10 _x diffusion barrier layer 111 (with a nominal thickness of 40 nm) using an Atomic Layer Deposition (ALD) process. A roll-to-roll ALD Web Coating System (WCS 600 supplied by Beneq) was used to deposit diffusion barrier layer layer (at a line speed of O. lm/min). The carrier substrate 112 coated with the diffusion barrier layer 111 was then split into six samples; on three of these, an barrier protection layer

110 was spin coated directly onto the A10 _x diffusion barrier layer 111 using a commercially available epoxy formulation (SU-8 2002 photoresist by Microchem). Then, an aerosol printing process (pneumatic atomizer, Optomec M3D 300CE) was used to deposit a square grid pattern of lines (with a 1mm pitch) of conductive nickel- based ink (Ni-IJ70, Applied Nanotech Inc.) directly onto the AlOx diffusion barrier layer 111 of one sample, and an identical pattern of lines was deposited on to a barrier protection layer 110 of another sample. These samples were then cured in a hot air oven for 30 minutes at 130 °C. After curing, the grid lines were measured to have a width of 0.14mm and a DFT of 0.1 μπι.

A sputtering process (Moorfield Minilab Sputter System with a 3" circular magnetron and a DC power supply, depositing from an aluminum target at 300W plasma power for 2 minutes) was then used to deposit a pattern of parallel lines of metallic aluminium, having a width of 1.8 mm and a pitch of 2.2 mm, directly onto an AlOx diffusion barrier layer of one sample. An identical pattern of parallel lines was deposited on to a barrier protection layer 110 of another sample. The lines were measured to have a thickness of 0.1 μιη.

One sample of the A10 _x diffusion barrier layer 111, and one of the A10 _x diffusion barrier layer 111 coated with the barrier protection layer 110 were kept as reference samples and not processed any further.

The six samples described above were subsequently tested for their water barrier properties by measuring their Water Vapour Transmission Rate (WVTR), which is expressed in grams of water per square metre per day. These tests were carried out using a Mocon ^® Aquatran 1 (at 38°C and 90% relative humidity). The results are shown in Table 2.

The WVTR of sample 1, which only has the A10 _x diffusion barrier layer 111 on the polymer film carrier substrate 112, was measured at 9.2* 10 ^"3 g/m ² /day, which is lower (better) than the values measured for sample 2 (1.3* 10 ^"2 ) and sample 3 (4.9* 10 ^{" 2} ) which have a printed nickel grid and sputtered aluminium line structures provided on the AlOx diffusion barrier respectively. This shows that the deposition of conductors directly onto an AlOx diffusion barrier layer adversely affects the WVTR of this diffusion barrier layer. It is thought that this is because the brittle A10 _x layer may be easily damaged by the handling and mechanical contact it is exposed to during the deposition of the printed grid or sputtered aluminium lines. The WVTR of sample 4, comprising the A10 _x diffusion barrier layer 111 and the additional barrier protection layer 110 on the polymer film carrier substrate 112, was measured at <5*10 ^"5 g/m ² /day, which is the detection limit of the Mocon ^® Aquatran 1 test method. Samples 5 and 6, where the printed nickel grid and the sputtered aluminium line structures were deposited onto the barrier protection layer 110, were also measured at the detection limit of <5* 10 ^"5 g/m ² /day.

Table 2

The fact that the WVTR of sample 4 was measured lower (better) than sample 1 demonstrates that the barrier protection layer 110 protects the A10 _x diffusion barrier 111 from getting damaged during the subsequent handling of the back substrate 30 with the AlOx diffusion barrier 111. It is also possible that by providing the barrier protection layer 111 onto the A10 _x diffusion barrier layer 111, the barrier performance or the diffusion barrier layer 111 may be improved in some way.

The fact that the WVTR of samples 5 and 6 were the same as that of sample 4 demonstrates that the presence of the barrier protection layer makes it possible to deposit a pattern of conductors onto a barrier protection layer 110, without affecting its barrier performance.

The above embodiments are described by way of example only. Many variations are possible without departing from the scope of the invention.