BACKSIDE CHARGE CONTROL FOR FET INTEGRATED CIRCUITS

Title:

BACKSIDE CHARGE CONTROL FOR FET INTEGRATED CIRCUITS

Document Type and Number:

WIPO Patent Application WO/2019/178004

Kind Code:

A3

Abstract:

Semiconductor-on-insulator field effect transistor (FET) integrated circuit (IC) structures and fabrication processes that mitigate or eliminate the problems caused by the secondary parasitic back-channel FET of conventional semiconductor-on-insulator FET IC structures. Embodiments enable full control of the secondary parasitic back-channel FET of semiconductor-on-insulator IC primary FETs. Embodiments include taking partially fabricated ICs made using a process which allows access to the back side of the FET, such as "single layer transfer" process, and then fabri-cating a conductive aligned supplemental (CAS) gate structure relative to the insulating layer jux-taposed to a primary FET such that a control voltage applied to the CAS gate can regulate the electrical characteristics of the regions of the primary FET adjacent the insulating layer. The IC structures present as a four or five terminal device: source S, drain D, primary gate G, CAS gate, and, optionally, a body contact.

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Inventors:

PAUL ABHIJEET (US)
WILLARD SIMON EDWARD (US)
YAMADA HIROSHI (US)
DUVALLET ALAIN (US)

Application Number:

PCT/US2019/021698

Publication Date:

November 07, 2019

Filing Date:

March 11, 2019

Export Citation:

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Assignee:

PSEMI CORP (US)

International Classes:

H01L29/786; H01L21/84; H01L27/12

Domestic Patent References:

WO2016183146A1	2016-11-17
WO2007120697A2	2007-10-25

Foreign References:

US20170373026A1	2017-12-28
EP1453093A1	2004-09-01
US5633182A	1997-05-27
US20080079037A1	2008-04-03
US20140342529A1	2014-11-20
US20060006496A1	2006-01-12
US20060012006A1	2006-01-19

Attorney, Agent or Firm:

CASH, Brian J. et al. (US)

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