ASSOCIATED SYSTEMS AND METHODS

BACKGROUND OF THE I VENTION

ί Various embodiments of the present invention relate to an input output balanced bidirectional buck-boost converter and associated system and method . 100021 As described herein, a DC/DC bidirectional buck-boost power converter has both input and output voltages centered around chassis, This converter allows for overlapping input and output voltages, and allows for use of offset based leakage fault detection (see, e.g., U.S. Patent No. 6,678,132).

J0003) Is one example, the converter (arsd associated system and method) may be used to interface any desired DC power source with arty desired energy storage system.

&Β8Β&& » of Related Art

[000 | Various conventional buck-boost converters are known. Some of these conventional buck-boos converters are bidirectional back-boost converters.

SUMMARY OF THE INVENTION

1 005] in one embodiment two three-phase inverters have their AC phases interconnected through line inductors and their DC links interconnected through capacitors. I this embodiment, the input inverter receiving DC power generates an optimal effective EMF source which regulates its output voltage in order to min mize line currents by maximizing po erfaeto . Further, in this embodiment, Ac output in verier out utting DC power regulates current in the AC link using a back EMF observer, phase -locked loop, field-oriented current controller, and a DC link voltage regulator. The capacitors between the .DC links provide passive common mode control, directing inverter drives common .mode voltages across the line inductors and controlling the return path for the common mode currents.

10000] In another embodiment, a bidirectional buck -boost converter is provided, comprising; a first inverter, the first inverter comprising a .first inverter positive DC terminal a first inverter negative DC terminal, a first, inverter phase one AC terminal a first inverter phase two AC terminal and a first inverter phase three AC terminal; a second inverter, the second inverter comprising a second inverter positive DC terminal, second inverter negati e DC terminal, a second inverter phase one AC terminal, a second inverter phase two AC terminal and a second inverter phase three AC terminal; a phase one inductor wound on a phase one inductor core, the phase one inductor being configured to electrically connect the first inverter phase one AC terminal with the second inverter phase one AC terminal; a phase two inductor wou.no on a phase two inductor core, the phase two inductor being configured to electrically connect the first inverter phase two AC terminal with the second inverter phase two AC terminal; a phase three inductor wound on. a phase three inductor core, the phase three inductor being configured to electrically connect the first inverter phase three AC terminal with the second inverter phase three AC terminal; a positive side DC capacitor configured to electrically connect the positive DC terminal of the first, inverter to the positive DC terminal of the second inverter; and a negative side DC capacitor configured to electrically connect the negative DC terminal of the first inverter to the negative DC terminal of the second inverter; wherein each of the phase one inductor core, the phase two inductor core and the phase three inductor core are independent cores.

|9007| In another embodiment, a powe system configured for use in a vehicle i provided, the power system comprising: a current source; a current sink; a controller; and a bidirectional bock-boost converter, the bidirectional buck-boost converter comprising: a first inverter, the first inverter comprising a first inverter positive DC terminal, a first, inverter negative DC terminal, a first inverter phase one AC terminal a first inverter phase two AC terminal and. a first inverter phase three AC terminal; a second inverter, the second inverter comprising a second inverter positive DC terminal, a second inverter negative DC terminal, a second inverter phase one AC terminal, a second inverter phase two AC terminal and a second inverter phase three AC terminal; a phase one inductor wound on a phase one inductor core, the phase one tnductor being configured to electrically connect the first inverter phase one AC terminal with the second inverter phase one AC terminal; a phase two inductor wound on a phase two inductor core, the phase two inductor being configured to electrically connect the first inverter phase two AC terminal with the second inverter phase two AC terminal; a phase three inductor wound on a phase three indnctor core, the phase three inductor being configured to electrically connect the first inverter phase three AC terminal with the second inverter phase three AC lerminai a positive side DC capacitor configured to electrically connect the positive DC terminal of the first inverter to the positive ^' DC terminal of the second inverter; and a negative side DC capacitor configured to electrically connect the negative DC terminal of the first inverter io the negative DC terminal of the secoad inverter; w e ein each of the phase one inductor core, the phase two inductor core and the phase three inductor core are independent core ^' s; and wherein the controller is configured to operate in. one of: (a) a first mode in which the current source is connected to the first inverter positive DC terminal and the first inverter negative DC terminal and the current sink s connected to the second inverter positive DC terminal and the second inverter negative DC terminal; aad.i ^' b) a second mode in which the current sink is connected to the first, inverter positive DC terminal and the first inverter negative DC terminal and the current source is connected to the second snverter positive DC terminal and the second inverter negative DC terminal; wherein, in the first mode the controller is configured to cause: (a) the first inverter to generate three-phase voltage at a fixed- frequency: and (h) the second inverter to generate ihree-phase current at the fixed- frequency; and -wherein, in the second xaode the controller is configured to cause: (a) the second inverter to generate three-phase voltage at a .fixed-f equency; and (b) the first inverter to generate three-phase current at the fixed-frequency.

I8008J in another embodiment a method of providing a bidirectional back-boost converter is provided, the method comprising: providing a first inverter, the first inverter comprising a first inverter positive DC terminal, a first inverter negative DC terminal, a first inverter phase one AC terminal, a first inverter phase two AC terminal and a first inverter phase three AC terminal; providing a second snverter, the second inverter comprising a second inverter positive DC terminal, a second inverter negative DC term inal a second inverter phase one AC terminal, a second inverter phase two AC terminal and a second inverter phase three AC terminal; providing a phase one odise tor wound on a phase one inductor core, the phase one inductor electrically connecting the first, inverter phase one AC terminal with the secoad inverter phase one AC terminal;, providing a phase two inductor wound on. a phase two inductor core, the phase two inductor electrically connecting the first inverter phase two AC terminal with the second inverter phase two AC terminal; providing & phase three inductor wound on a phase three inductor core, the phase three inductor electrically connecting the first inverter phase three AC terminal with the second inverter phase three AC terminal; providing a positive side DC capacitor electrically connecting the positive DC terminal of the first inverter to the positive DC terminal of the second inverter; and providing a negative side DC capacitor electrically connecting the negative DC terminal of the first inverter to the negative DC terminal of the second inverter, wherein each of the phase one inductor core, the phase two inductor core and the phase three inductor ore are independent cores.

BRIEF DESCRIPTION OF THE DRAWINGS

[ ^' 0809} The drawings are provided for illustrative purpose on.ly and do not necessarily represent practical examples of the present invention to scale, in the figures, same reference signs are used to denote the same or like parts.

f OlO) Fig. I is a high-level block diagram of an input output balanced buck-boost converter according to an embodiment of the present invention,

|0011 J Fig. 2 is a diagram showing details of the inverters of Fig. ! according to an embodiment of the present i n ven tion,

fSOO ^' j Fig. 3 is a diagram (showing power factor corrected V/Hz) of an example of converter control (input) according to an embodiment of the present invention, I00DJ Pig. 4 is a diagram (showing field oriented controller with. DC link regalation) of an example of converter control (output) according to an embodiment of the present invention .

[00141 Fig. 5 is a sample of a typical converte r control phase current waveform according to an embodiment of the present invention.

fC H.Sf Fig, 6 is a sample inverter common mode source waveform according to an embodiment of the present invention.

|8016| Fig- ? is a sample inverter-inverter common mode equivalent circuit (showing the equivalent circuit if capacitors 501 and 503 of Fig. 2 are mi used).

[iH)l?| Fig. 8 is a sample inverter-inverter common mode equivalent circuit (showing a common mode equivalent circuit if capacitors 501 and S03 of Fig. 2 are used). {0 18J Fig. 9 is a sample of common mode waveforms according to an embodiment of the present invention.

[8019J Fig. I OA is a sample plant controllability plot (showing a Bode Diagram, From: Vcmd, To: Transfer Fen 1 (of Fig. 1.08)) according to an embodiment of the present invention. |0020j Fsg. 1GB is a sample transfer function diagram associated wit the plot of Fig. H ⁾ A according to an embodiment of the present invention.

| 02ll Fig. HA is a sample open loop controllability plot ( ^' showing a Bode Diagram, From: Vcmd! , To: Transfer Fcn4 (of Fig. ί IB)) according to an embodiment of the present invention.

|W2 1 Fig, 1 iB is a sample transfer function .diagram associated with the ^' plot of Fig. 11 A according to an embodiment of the present invention.

8023| Fig. 12A is a sample device loss plot according- to an embodiment of the present invention.

| 24f Fig, 1.2B is a sample device loss densit plot according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

f _. 80251 For the purposes of describing and claiming the present invention the term "converter" is intended to refer to a mechanism (e.g., circuit and/or device) for changing an input direct current (DC) having an input voltage value and an input current value to an output direct current (DC) ha ving -an output voltage value and an output current value (wherein the output voltage value differs from the input voltage value and/or the output current value differs from the input current value).

0026 For the purposes of describing and claiming the present invention the erm "inverter" is intended to refer to a mechanism (e.g.. circuit and/or device) for: (a) changing direct current (DC) into alternating current (AC); and/or (b) changing alternating current (AC) into direct current (DC).

100 71 For the purposes of describing and claiming the present invention the term "current source ^* ' is intended to refer not only to an ideal textbook current source with infinite voltage compliance, but in some circumstances to other mechanisms capable of supplying current, such as. an ideal voltage source capable of supplying current, with or without series impedance, or one or more DC power sources connected in parallel, which can deliver power to the converter tet inals.

[0028] For the purposes of describing and .claiming the present invention the term "current: sink" is intended to refer not only to an ideal textbook current sink with infinite voltage compliance, but in some circumstances to other mechanisms capable of c nsumi g current, which can include one or more resistive or active electronic loads connected in parallel, or a voltage with or without series ixspedance. 1 _. 00291 With reference now to Fig. 1 , as input output balanced buck-boost converter 10! according to m embodiment of the present invention is shown. As seen in this Fig, I (which is a high-level block diagram), con erte 101 Includes inverters 103 and 105 and controller 107. Controller 10? is in operative communication with inverters 103,105 to control inverters 103,105 as discussed herein. Inverter 103 receives power from or provides power to power source/ power sink .104. Similarly, Inverter 105 receives power from or provides power to power source/ power sink 106. Of note, converter 101 is a bidirectional converter. Thus, when power source /power sink 104 acts as a power source (that is, supplying power to inverter .103), inverter 105 will supply power to power source / power sink 106 (which, in this instance, will act as a power sink that receives power from inverter 105). Conversely, when power source / power sink 106 acts as a power source (that is, supplying power to inverter 105), inverter 103 will supply power to power source / power sink 04 (which, in this instance, will act as a power sink that receives power from inverter 1.03). In one exam le, each of inverters 103 and 1.05 may utilize hardware structure similar to that of a conventional inverter.

| 03 With reference no to Fig. 2, details of inverters 103 and .105 according to this embodiment are shown. As seen in this Fig. 2, inverter 103 comprises positive DC terminal 201 , negative DC terminal 203, resistors 205A,205B, capacitors 207A- 207C, switches 209A-209F (e.g.. comprising solid state devices), voltage sensors 21 I -21 ID and etareni sensors 2.13 A, 213B,

| 03 ί] Similarly, inverter 105 comprises positive DC terminal 301, negative DC terminal 303, resistors 305A,3 5B, capacitors 307A-307C, switches 309A-309P (e.g., comprising solid state devices), voltage sensors 3 Π A-31 ID and current sensors 313A, 3! 3B.

1003.2] Further, inverter 103 comprises phase one AC terminal 2 ISA, phase two AC terminal 215B and phase three AC terminal 21 SC. i addition, inverter 105 comprises phase one AC terminal 3 ISA, phase two AC terminal 31 SB and phase three AC terminal 31 SC. inductor 4 1 electrically connects phase one AC terminal 215 A. with phase one AC terminal 3 ISA. Further, Inductor 403 electrically connects phase two AC terminal 21 SB with phase two AC terminal 31 SB. Further still, inductor 405 electrically connects phase three AC terminal 215C with phase three AC terminal 31 SC. 10033} In. this embodiment, each of inductors 401 , 403, 405 is separately wound on an independent core, {not shown). This configuration of separately winding on an independent core each of inductors 401 , 403, 405 remits in the nduct r 401, 403, 405 providing common mode and differential mode inductance.

10034) Still referring to Figs. ! and 2, converter 101 includes capacitor 50! configured to electrically connect positive DC terminal 201 with positive DC terminal 301. Further, converter 10! includes capacitor 503 configured to electrically connect negative DC terminal 203 with negative DC terminal 303.

| 83S| In this embodiment, the use of capacitor 5 1 between positive DC terminal 201 and positive DC terminal 301 along with the use of capacitor 503 between negative DC terminal 203 and negative DC terminal 303 provides for a common mode current return path that returns high frequency noisy current (instead of through the chassis).

!0036 ^' | Referring now to Fig. 3 (showing power factor corrected Wife), an example of converter control (input) is shown. This block diagram of Pig. 3 shows functionalit>' of the type that a be implemented in controller 107.

10 37) As sees in this Fig. 3, an input to the control mechanism is I*. When inverter 103 is receiving DC power (and inverter 105 is outputting DC power), this I _»h may be detected by current sensors 213 A and 2138. Conversely, when inverter 105 is receiving DC power (and inverter 103 is outputting DC power), this ½ may be detected by current sensors 313 A and 313B.

|0038| Another input to the control mechanism is frequency ω. As seen, this ω is input to 1/s block 381 and the output thereof is provided to both Coordinate

Transformation block 383 and Duty Cycle/Coordinate Transforman Deadtime Compensation block 385.

{W3§} Another istput to the control mechanism is Vdc / Sqrt{3) block 387. As seen, the output of this Vdc / Sqrtf 3) block 387 is provided to upper limit (VL) input of variable ihniter proportional integrator (VLPI) 389 (the output of this block 387 is also combined at block 391 as described below).

100 0} Still referring to Fig. 3, it is seen that is input to Coordinate Transformation block 383, Coordinate Transformation block 383 outputs ! _<j Fb (feedback) arid outputs its Fb (feedback). Fb is fed to Reactance block 393 and the output of Reactance block 393 is combined with h Fb and provided to error input of VIJPI 389. 00 11 Further, ¾F is provided to (s / w) / (s/ ω 1) block 395. The output of block 395 is combined at block 391 with the output: of block 387. The output of block 391 is then provided to FF input of VLPi 389.

j _. 0042] In. addition, a value of provided to lower limit (LL) input ofVLPi 389.

[8643] Finally, a -space vector 397 is provided as an output from block 3.85. This space vector 397 (which may be in the form of an industry standard switching protocol) may control switching intervals of various switches by, for example, pulse width modulation (PWM). Is one specific example, when inverter 103 is receiving DC power (and inverter 105 is ouiputtmg DC power), this space vector 397 may control switching of switches 209A-209F of inverter 103 of Fig. 2. In another specific example, when inverter 105 is receiving DC power (and inverter 103 is outputting DC power), this space vector 397 may control switching of switches 309A-309F of inverter 105 of Fig. 2.

flK 4f Still referring to Fig. 3, it is noted that in this example the control mechanism may be configured to generate 3-phase voltage at a fixed frequency (e.g., 60M?;). Further, the control mechanism may operate to make inverter 103 (when receiving DC power) or inverter 105 (when receiving DC power) output power as if it were a rotating machine. Further, it is noted that when boosting, a V/Hz with a maximum possible phase voltage mmiraiKes phase currents. Further still, it is noted that when bucking, the V !½ voltage should be selected to provide unity power factor. Finally,, it is noted that the feed forward path quickly compensates for increasing voltage overlap.

Ι _. 0Θ45) Still referring to Fig. 3. ® Is the commanded frequency of the AC link; in this example, eo is & constant and must be selected in order to minimize losses in the magnetics hut still maintain enough reactive drop that the field, weakening and power factor correct v/fe loops have enough control authority.

|0 o| Still referring to Fig. 3, Vdc is the measured value of the inverter's DC link voltage,

\ M7\ Referring now to Fig. 4 (showing field oriented controller with DC link regulation) an example of converter control (output) is shown. This block diagram of Fig. 4 shows functionality of the type that may be implemented in controller 107. 1 _. 0048 As seen in this Fig. 4, two inputs to the control mechanism are V _«v Ref (desired output voltage) and V,j ₍ . Fb (feedback). Other inputs to the control mechanism are from field weakening detection at block 481 and .from back EMF (8EMF) Observer at block 483 (in one example, the BEMF ⁽ Back Electromotive Force) Observer may recreate AC voltage based upon knows voltage, known current and known inductance (e.g., inductors 401, 403 and 405)).

|0849j Another input to the control mechanism is ^' ί , When inverter 105 is out acing DC power (and inverter 103 is recei ving DC power), this may be detected by current sensors 313 A and SB ^' S. Conversely, when inverter 105 is receiving DC- power (and inverter 103 is outpuitmg DC power), this ί¾χ may be detected by current sensors 213 A and .213B.

[ dS0| Further, as seen, Vy _c Re and V,.,,- Fb are combined at block 485 and the output of block 485 is smt to VPLi 48?. Further the output of block 487 is sent to current command block 489, The output of block 489, that is, ¾ Ref (along with 1 _¾ ef from block 48 ! ) is sent to VPLI 4 1.

[08$ I j Further; as seen, EMF from block 483 is sent to phase locked loop block 493 , From block 493 a magnitude EMF is sent to block 4S9, In addition, from block 493. a Theta EMF is sent to Coordinate Transformation block 495 and Duty

Cycle/Coordinate TramfornuttioaT adtime Compensation block 497.

10 52 Further, as seen, i _sfc is input to block 495 (along with. Theta EMF) and L _J¾ Fb is output .from block 495 and sent to VLPI 1. In addition, an output from VLP1 491 is scat (along with Theta EMF) to block 497.

|SQ53j Finally, a space vector 499 is provided as an output from block 497. This pace vector 499 ( which ma be in the form of an industry standard switching protocol) may control switching intervals of various switches by, for example, pulse width modulation (PWM). In one specific example, when inverter 103 is receiving DC power (and inverter 105 is outputting DC power), this space vector 419 may control switching of switches 309A- 309.P of inverter 105 of Fig. 2. In another specific example, when inverter 105 is receiving DC power (and inverter 1.03 is ootpuiting DC power), this space vector 439 may control switching of switches 209A-209F of inverter 103 of Fig. 2.

10054} Still referring to Fig. 4, it is noted thai in this example the control mechanism may be configured to treat the generated voltage at the phase inductors) (see, e.g., inductors 401 , 403 and 405 of Fig. 2) as a fixed frequency. In one specific example, the control mechanism may ^' be configured to provide, in effect, rotating machine control. In another specific example, the control mechanism may be configured to provide, in effect, regulation of current Further, in another specific example, the field oriented controller may utilize standard SMPM (Surface Mount Permanent Magnet) sensoriess control. Further, in. another specific example, the voltage loop may provide regulated DC output Further, in another specific example, the field weakening allows for overlapping input and Output DC voltages.

P>5§) Still .referring to Fig, 4, the BEMF observer is a back- electro motive force observer. The purpose of the BEMF observer is to observe commanded phase voltage, measured phase currents and known inductances in order to reconstruct the AC voltage source (BEMF),

[8856] Still referring to Fig. 4. Vdc Ref is the command into she converter for die value of the output voltage and Vdc fb is the measured output voltage.

|θθ5?| Still referring to Fig. 4, VLFI 487 and 49.1 are the same control structure (variable limiter proportional integrator regulators), the only difference being gains.

6581 Referring now again to Pigs. 3 and 4, in one example, blocks 383 and 495 provide coordinate transformations of the AC current measurements in order to allow the control law to operate in a reference frame which rotates at the electrical frequency of the AC link, A benefit of this is that the AC fundamental frequency is decoupled and control action is performed on .DC quantities.

10059} Referring now again to Figs. 3 aud 4. in one example, blocks 385 and 497 primarily provide a counter rotation of the commanded phase voltage. Each block transforms the reference frame back to a stationary frame in effect converting the regulated DC quantities into AC phase voltage to he commanded to the converter. Each, block then scales these voltages into switch duty cycles and compensated for the non- linearities caused by deadiirne and inverter drop.

jO06© Referring now again to Fig. 4, in one example, block 481 "field weakening' ^* calculates a required, reacts ve current needed in order to reduce the magnitude of the effective AC link source voltage seen by the current regulator such that stable control can be maintained when the magnitude of the AC link source voltage appr oaches the capability provided by the current regulator's DC link.

[066.1 f Referring now to Fig. .5, a sample of a typical converter control phase current waveform 510 according to an. embodiment of the present i ention is shown. As seen in this Fig. 5, phase currents 581, 583 and 585 (that is, corresponding to phases i to 3) axe sinusoidal and balanced,

(0862] Referring now to Pig. 6, a sample inverter common mode source waveform 600 according to an embodiment of the present invention is shown (the x-axis is pulse width modulation overtime and the y-axis is voltage). As seen in this Fig. 6, the inverter sources significant commoB mode voltages at PWM rate Thus, converter design should take into account where these voltages are dropped nd how the ^• resultant current flows.

[9i ⁾ 63| Referring now to Fig. 7, shows is a sample inverter-inverter common mod equivalent circuit 700 (showing the equivalent ^' circuit if capacitors 501 and 503 of Fig. 2 are not used). As seen, if inverters are simply tied together through inductors:

(a) Common mode current returns throug chassis; and (b) Small Ccm (common mode capacitance) values force large voltages on chassis. Of note, in this Fig. 7, 2*Ccmi corresponds to capacitors 207A and 207B of Fig. 2 and 2*€cm2 corresponds to capacitors 307 A and 3078 of Fig. 2.

|806 ^' j Referring now to Fig. 8, shown, is a sample inverter-inverter common mode equivalent circuit 800 (snowing a. common, mode equivalent circuit if capacitors 50! and 503 of Fig. 2 are used). As seen, capacitors 501 and 503 (shown in this Fig. 8 as 2*CC ) reduce or eliminate issues described with respect to Fig. 7. That is: (a) Common mode currents are directed back to their source though dedicated wires; and

(b) Common mode voltages drop across Sine inductance eliminate any significant common mode voltage from appearing on DC links.

f0CN>5] Refemng now to Fig. 9, a sample of common mode waveforms 900 according to an embodiment of the present invention is shown. More particularly, in this Fig. 9. common mode current 901 , phase current 903, phase current 905 and common mode voltage 907 are shown.

Reference will now be made to an example common mode capacitor selection according to an embodiment of the present invention. As seen in equation 1 (common mode attenuatio } and equation 2 (phase current controllability) shown below: the larger the value of Ccm (see, e.g., capacitors 501 and $03 of Fig. 2) the less the common mode voltage on the DC links also, as Ccm. increases the controllability of the converter decreases as uncontrolled neutral currents begin to flow.

j _. 0d<>?f Referring now to Fig. 10A, shown is a sample plant controllability plot 1000 according to an embodiment of the present invention (the upper chart has frequency on the x-axis and ma nitude on the y-axis and the l wer chart has frequency on the x~ axis and phase on the y-axis). In this Fig. I OA, lines 1001 are plotted for a common mode capacitance of 25 uF (and inductance of 300uH). Farther, lines 1003 are plotted for a c mmon mode capacitance of 50 uF (and inductance of 300uH). Further still fines 1005 are plotted for a common mode capacitance of 100 uF {and inductance of 300aH), As seen, as common mode capacitance increases, the circuit may become uncontrollable at lower frequencies because neutral currents acquire an uncontrolled feedback path.

|0β68| Referring now to Fig, 1 B, shown is a sample transfer function diagram 1.050 associated with the plot of Fig. !OA. In this Fig. 10B, the represents

multiplication; the s ts the complex lapiaee variable.

|0O$9 Referring now to fig. 1 1 A, shown is a sample open loop controllability plot according to an embodiment of the present invention (the chart has frequency on the x-axis and magnitude on the y-axis). fa this Fig. 1 1 A, line 101 is plotted for a common mode capacitance of 100 uF. Further, line 1103 is plotted for a common mode capacitance of 25 uF. As seen, for equivalent controllers high common mode capacitance eliminates open loop gain at lower frequencies.

}00?0) Referring now to Fig. 1 IB, shown is a sample transfer function diagram 1 150 associated with the plot of Fig. 11 A. In this Fig. 1 1 B, the represents

maltipiication; the s is the complex lapiaee variable.

IO07I5 Reference will now be made to Improved IGBTfhssuiated Gate Bipolar Transistor) Loss Distribution according to an embodimen of the present invention (in this regard, see Figs. 1 A and 1.2S). More particularly, it is noted that typical IGBT packages contain half as much silicon in the diode as they do in the switch. This construction leads to a desire to transfer losses out of the diode in order to maintain even loss densities. Additional benefits are realized from an overall decrease in the amount of power that needs to be processed as all inverter loads can consume unprocessed power. [§072] Referring now lo Fig. 12 A. shown is a sample device loss plot 1200 according to an embodiment of the present invention (the chart has boost ratio on the x-axis and device loss on the y-axis). In this Fig. 12 A. line 1201 is plotted for balanced buck boost, diode (W), line 1203 is plotted for balanced buck boost switch (W), line 1205 is plotted for boost diode (W), and line 120? is plotted for boost switch (W j.

[0973] Referring now to Fig, !2B, shown is a sample device toss density plot 1250 according to an embodiment of the present invention (the chart has boost ratio on the x-axis and device loss density on the y-axis). In this Fig. 12B, line 1251 is plotted for balanced buck boost diode (W / in ² }, line 1253 is plotted for balanced buck boost switch (W / in ² ), line 1255 is plotted for boost diode (W / in ² ), and line 1257 is plotted for boost switch (W / V ^" ).

j 807 } As described herein i an input output balanced bidirectional hack-boost converter. Benefits pro ided by various embo iments of the converter include: ( ) Standard power control: (a.) Only two current sensors per inverter; (b) BEMF position sensorless Vector Control provides phase current md dc voltage regulation; and/or (c) V/Hz provides effective inverter sourced E F iPFC (Power Factor Correction) loop can dynamically ptimize V ffe voltage); (2) Simple DC bos architecture: (a) Inherently supports overlapping DC bus voltages (buck / boost); and/or (b) Controlled common mode voltages and currents; (3) Independent isolation fault detection through balanced input and output; and/or (4) Reduced !GBT power density over certain conventional buck boost topologies.

f0O?Sj As described herein is a specific DC link architecture that may be used in the contex t of an input output balanced bidirectional buck-boost converter. Benefits provided by various embodiments of the DC link architecture include: (1) Both input and output. DC links are centered around chassis (balanced): (a) Allows for independent AC and DC isolation fault detection; and/or (b) Voltages with respect to chassis are minimi ed; (2) Minimum number of high vol tage DC links to manage; and/or (3) Inverter loads can consume unprocessed power reducing the load on the power converter.

|§S76| Of note, certain conventional DC/DC buck-boost topologies have input and output voltages which share a common reference. These converters may he inherently less safe because the two inverters will have different DC link offset voltages with respect to chassis, and the maximum voltage stress to chassis for either inverter and its loads will be greater than half of the DC link ^' value.

B [8Θ77] In contrast, a converter according to various embodiments of the present invention provides for the following: (a) is sin le fault tolerant; (b> because both the input and output voltages are balanced and independent, both. AC and DC leakage faults can be independently detected and isolated to each side of the converter: (c) handle common mode voltages and currents in order to provide input and output voltages with minimal common mode activity with respect to chassis; (d) utilize only two current sensors and standard motor control techniques in order to provide DC voltage regulation; (e) by controlling AC line currents, optimally utilizes the standard IGBT packaging in which die diode is undersized with respect to the IGBT by better distributing the loss density in the IGBT packages.

(0078} In one embodiment, a bidirectional buck -boost converter is provided, comprising: a first inverter, the first inverter comprising a first inverter positive DC terminal, a first inverter negative DC terminal, a first inverter phase one AC terminal, a first inverter phase two AC terminal and .a first inverter phase three AC terminal; a second inverter, _, the second inverter comprising a second inverter positive DC terminal, a second inverter negative DC terminal, a second inverter phase one AC terminal a second inverter phase two AC terminal and a second inverter phase three AC terminal; a phase one inductor wound on a phase one inductor core, the phase one inductor being configured to electrically connect the first inverter phase one AC terminal with the second inverter phase one AC terminal; a phase two inductor wound on a phase two inductor core, the phase two inductor being configured to electrically connect the first inverter phase two AC terminal with the second inverter phase two AC terminal; a phase three inductor wound on a phase three inductor core, the phase three inductor being configured to electrically connect the first inverter phase three AC terminal with the second inverter phase three AC terminal; a positive side DC capacitor configured to electrically connect the positive DC terminal of the first inverter to the positive DC terminal of the second inverter; and a negative side DC capacitor configured to electrically connect the negative DC terminal of the first inverter to the negative DC terminal of the second inverter; wherein each of the phase one inductor core, the phase two inductor core and the hase three inductor core are independent cores.

f(H ⁾ ?9 in one example, the converter further comprises a controller.

{0080} in another example, the controller is configured to cause the first inverter to generate three-phase voltage at a fixed-frequency. {¾H ^} § | In sno.th.er example, the fixed-frequency three-phase voltage of the first inverter is provided at the first inverter phase one AC terminal the first inverter phase two AC terminal and the first inverter phase three AC terminal.

| 082j In another example, the controller is configured to cause the second inverter to generate three-phase current at the fixed-frequency.

i#083] In another example, the controller is configured to cause the second inverter to generate the three-phase current at the fixed-frequency based upon die fixed- frequency three -phase voltage of the first inverter provided by the first inverter phase one AC terminal, the first inverter phase two AC terminal and the fust inverter phase three AC terminal

(008 J In another example: the first inverter positive DC terminal and the first inverter negative DC terminal are connected to a current source; and the second inverter positive DC terminal and the second inverter negative DC terminal are connected to a current sink.

[8 85] In another example, the current source is a battery.

In another example, the current sink is a battery and the current source is a fuel cell

|ίΜϊ 7] i another example, the controller comprises a processor.

J0088] In another ^' example, the controller comprises at least one of an ASIC and an

FPGA.

[0 $?>] in another example, the converter further comprises a memory storing computer readable instructions.

1 9 ] In another example, the memory comprises at least one of hardware and firmware.

(009 1 n another example, the memory comprises a computer readable medium and the computer readable instructions comprise a software program.

00 2] In another embodiment, a power system configured for use in a vehicle is provided, the power system comprising: a current source: a current sink; a controller; and a bidirectional buck-boost converter, the bidirectional back-boost converter comprising: a first inverter, the first inverter comprising a first inverter positive DC terminal, a first inverter negative DC terminal, a first inverter phase one AC terminal, a first inverter phase two AC terminal and a first inverter phase three AC terminal; a second inverter,, the second inverter comprising a second inverter positive DC terminal, a second inverter negative DC terminal a second inverter phase one AC terminal, a second inverter phase two AC terminal and a second inverter phase three AC terminal; a phase one inductor wound n a phase one inductor core., the phase one inductor being configured to electrically eoaoect the first inverter phase one AC terminal with the second inverter phase oue AC terminal; a phase two inductor wound on a phase two inductor core, the phase two inductor being configured to electrically connect the first inverter phase two AC terminal with the second inverter phase two AC terminal; a phase three inductor wound on a phase three inductor core, the phase three inductor being configured to electrically connect the first inverter phase three AC terminal with the second inverter phase three AC terminal; a positive side DC capacitor configured to electrically connect the positive DC terminal of the first inverter to the positive DC terminal of the second inverter; and a negative side DC capacitor configured to electrically connect the negative DC terminal of the first inverter to the negative DC terminal of the second inverter; wherein each of the phase one inductor core, the phase two inductor core and the phase three inductor core are independent cores; and wherein the controller is configured to operate in one of: (a) a first mode in which the current source is connected to the first inverter positive DC terminal and. the first inverter negative DC terminal and the current sink is connected to the second inverter positive DC terminal and the second inverter negative DC terminal; and (b) a second mode- in which the current sink is connected to the first inverter positive DC terminal and the first inverter negative DC terminal and the current source is connected to the second inverter positive DC terminal and the second inverter negative DC terminal; wherein, in the first mode the controller is configured to cause: (a) the first inverter to generate three-phase voltage at a fixed- frequency; and (b) the second inverter to generate three-phase current at the fixed- frequency: and wherein, in the second mode die controller is configured to cause: (a) the second .inverter its generate three-phase voltage at a fixed-frequency; and (b) the first inverter to generate three-phase current at the fixed-frequency.

In one example, in the fust mode, the current source is a battery.

10094} In another example, in the second mode, the current sink is a battery and the current source is a fuel cell

|O095] In another example, the controller comprises a processor.

|βδ ] In another embodiment, a method of providing a bidirectional buck-boost converter is provided, the method comprising: providing a first inverter, the first inverter comprising a first inverter positive DC terminal, a first inverter negative DC W terminal, a first smarter phase one AC terminal, a first inverter phase two AC terminal and a first inverter phase three AC terminal; providing a second inverter, the second inverter comprising a second inverter positive DC terminal a second inverter negative DC ter inal, a second inverter phase one AC terminal a second inverter phase two AC terminal and a second inverter phase three AC terminal; providing a phase one inductor wound on a phase one inductor core, the phase one inductor electric-ally connecting the first inverter phase one AC terminal with the second inverter phase one AC terminal; providing a phase two inductor wound on a phase two inductor core, the phase two inductor electrically connecting the first inverter phase two AC terminal with the second inverter phase two AC terminal; providing a phase three inductor wound on a phase three inductor core, the phase three inductor electrically connecting the first inverter phase three AC terminal with the second inverter phase three AC terminal providing a positive side DC capacitor electrically connecting tire positive DC terminal of the first inverter to the positive DC terminal of the second inverter; and providing a negative side DC capacitor electrically connecting the negative DC terminal of the first inverter to the negative DC terminal of the second inverter; wherein each of the phase one inductor core, the phase two inductor core and the phase three inductor core are independent cores.

in one example, the method further comprises: causing the first inverter to generate three -phase voltage at » fixed-frequency, wherein the fixed-frequency three- phase voltage of the first inverter is provided at the first inverter phase one AC terminal the first inverter phase two AC terminal and the first inverter phase three AC terminal; and causing the second inverter to generate three-phase current at the fixed frequency based upon the fixed-frequency three-phase voltage of the first inverter provided by the first inverter phase one AC terminal, the first inverter phase two AC terminal and the first inverter phase three AC terminal.

In other examples, any steps described herein may be carried out in any appropriate desired order.

|0099| In one example, one controller may control both inverters. In another example, each inverter may be controlled by a respective controller (that is, one controller for each inverter). |0I θθ] In another example, power may be shuttled back and fortfc without mode or "quadrant" sw tchin .

fOJ.01| In another example, loads may be one or more of: heaters, AC inverters for utility power, etc.

{QWlj Reference will now be made to a numbe of example configurations- associated with an embodiment of the invention (in connection with these example configurations, the following assumptions apply: (A) Inverter I DC terminals connected to DC Source 1 ; (B) Inverter 2 DC terminals Connected to DC Source 2; (C) Voltage sources are capable of ^* delivering or sinking current; (0) Voltage sources may or may not have series impedance; {£} Those familiar with the art will understand that an SVM inverter producing at* AC voltage vector can either absorb or produce AC power depending on the phase angle of the AC terminal load current). 101031 Configuration 1 - Power Transfer: Bidirectional; DC Source 1 Type;

Voltage; Source 1 Detail; Bidirectional Current; Inverter 1 Mode: AC Voltage Vector; DC Source 2 Type: Voltage; Source 2 Detail: Bidirectional Current; Inverter 2 Mode: Vector Controlled Sensorless; Inverter 2 Voltage Loop: No.

fOHMJ Configuration 2 - Power Transfer; Bidirectional; DC Source ] Type:.

Voltage; Source 1 Detail: Bidirectional Current; Inverter 1 Mode: AC Voltage Vector; DC Source 2 Type: Current/Power; Source 2 Detail; Motor Dnve(s), other; Inverter 2 Mode: Vector Controlled Sensorless; Inverter 2 Voltage Loop: Yes, f ί©5 ^" { Configuration 3 - Power Transfer. Bidirectional; DC Source 1 Type;

Voltage; Source I Detail: Fuel Cell // Loads: Inverter I Mode: AC Voltage Vector; DC Source 2 Type; Battery // Loads; Source 2 Detail: Bidirectional Current; inverter 2 Mode ^; c Controlled Sensorless; inverter 2 Voltage Loop; Optional

[0106] Configuration 4 - Power Transfer. Bidirectional; DC Source 1 Type:

Voltage; Source 1 Detail: Battery // Loads; inverter 1 Mode: AC Voltage Vector; DC Source 2 Type: Fuel Cell // Loads; Source 2 Detail: Bidirectional Current; Inverter 2 Mode: Vector Controlled Sensorless; Inverter 2 Voltage Loop: Optional.

fOiOTj Configuration 5 - Power Transfer: 1 ~ ^" 2; DC Source 1 Type: Voltage; Source 1 Detail Fuel Cell - current output only; Inverter 1 Mode: AC Voltage Vector; DC Source 2 Type: Voltage; Source 2 Detail: Battery; inverter 2 Mode: Vector Controlled Sensorless; Inverter 2 Voltage Loop: Optional. \i ⁾ 108] Config ration 6 ^■ - Power Transfer: 2 ^■ - 1 : DC Source 1 Type: Voltage;

Source ί Detail : Battery; Inverter I Mode: AC Voltage Vector; DC Source 2 Type: Voltage; Source 2 Detail: Fuel Ceil - output only, other; Inverter 2 Mode: Vector Controlled Sensoriess; Inverter 2 Voltage Loop: Optional.

{8109} As described herein, various embodiments may have the capability to evaluate composite leakage faults. In one example, this may require modification to a space vector which introduces a DC shift between the DC link offsets. In another example, independent chassis fault detection may be used for rue! cell isolation resistance measurement

|WI0] As will be appreciated by one skilled in the art. aspects of the present invention may be embodied as a converter, system, method and/or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment or an embodiment combining software and hardware aspects. ^' Furthermore, aspects of the present invention may take the form of a computer program, product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon. In one example, the computer readable medium may tangibly embody the program code in a non- transitory manner,

01111 As described herein, the disclosed converter may be used to interface any DC power source with an energy storage system, in one specific example, the converter may be applied m the context of a vehicle (e.g., a fuel cell bus), in another specific example, the disclosed inverter may be used in connection with a high voltage battery. In another embodiment, by replacing the line reactors and link capacitors with a 3 phase transformer, the converter may be used to provide an isolated balanced input balanced output bidirectional buck/boost converter.

{ ^' 0112) it is noted that the foregoing has outlined some of the embodiments of the present, mvent n. This invention may be used for many applications. Thus, although the description is made for particular arrangements and methods, the intent and concept of the invention is suitable and applicable to other arrangements and applications, ft will be clear to those skilled in the art that modifications to the disclosed embodiments can be effected without departing from the spirit and scope of the invention. The described embodiments ought to be construed to be merely illustrative of some of fee features and applications of the invention. Other beneficial 01 results can be realized by applying the disclosed invention m a different manner or modifying the invention in ways known to those familiar with the art. Farther, it noted (hat all examples disclosed herein are intended to be illustrative, and not restrictive.