Title:
BIAS CIRCUIT AND AMPLIFIER
Document Type and Number:
WIPO Patent Application WO/2021/182067
Kind Code:
A1
Abstract:
A bias circuit (10) comprising: a switching element (11) having a first terminal (11a) and a second terminal (11b), the first terminal (11a) being electrically connected to a gate terminal (1a) of an amplification element (1) that is a transistor and amplifies an amplification target signal inputted to the gate terminal (1a); and a trap compensation element (12) which has a third terminal (12a) and a fourth terminal (12b), and to which the second terminal (11b) and the third terminal (12a) are connected. The bias circuit (10) further comprises a control circuit (13) that performs: a control of applying a bias voltage to the gate terminal (1a), and, when the amplification target signal is a transmission signal, turning the switching element (11) into an open state; a control of establishing a non-conduction state between the third terminal (12a) and the fourth terminal (12b) of the trap compensation element (12), and, when the amplification target signal is a reception signal, turning the switching element (11) into a closed state; and a control of establishing a conduction state between the third terminal (12a) and the fourth terminal (12b). The bias circuit (10) further comprises a voltage application circuit (14) that, when the amplification target signal is a transmission signal, applies a first voltage to the fourth terminal (12b), and that, when the amplification target signal is a reception signal, applies a second voltage, which is a negative voltage, to the fourth terminal (12b).
Inventors:
YAMAGUCHI YUTARO (JP)
HANGAI MASATAKE (JP)
SHINJO SHINTARO (JP)
HANGAI MASATAKE (JP)
SHINJO SHINTARO (JP)
Application Number:
PCT/JP2021/006236
Publication Date:
September 16, 2021
Filing Date:
February 19, 2021
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
International Classes:
H03F1/00
Domestic Patent References:
| WO2012111451A1 | 2012-08-23 |
Other References:
ANDREI, C., BENGTSSON, 0., DOERNER, R., CHEVTCHENKO, S. A., RUDOLPH, M. ET AL.: "Robust stacked GaN-based low-noise amplifier MMIC for receiver applications", IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM, 2015, pages 1 - 4, XP033181218, DOI: 10.1109/MWSYM.2015.7166766
C ANDREI ET AL.: "Robust Stacked GaN-Based Low-Noise Amplifier MMIC for Receiver Applications", IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM, 2015
See also references of EP 4096090A4
C ANDREI ET AL.: "Robust Stacked GaN-Based Low-Noise Amplifier MMIC for Receiver Applications", IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM, 2015
See also references of EP 4096090A4
Attorney, Agent or Firm:
SANNO PATENT ATTORNEYS OFFICE (JP)
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