TECHNICAL FIELD

[0001 ] This disclosure relates generally to a bias circuits and more particularly to a low power consumption bias circuits for Radio Frequency (RF) Field Effect Transistor (FET) amplifiers.

BACKGROUND

[0002] As is known in the art, a Radio Frequency (RF) Transistor Amplifiers have a wide range of applications. In many of these applications it is highly desirable to reduce the power required to operate these amplifiers. As is also known, one type of RF amplifier includes a Group III-V semiconductor, depletion mode, Field Effect Transistor (FET), indicted as "R F FET" in FIG. 1 , arranged in a common source configuration requiring operation with both a positive voltage supply (+V _DD ) and a ground potential, as shown in FIG. 1. More particularly, the drain of the RF FET is coupled to +VDD, the source is coupled to ground, and the gate has a rectifying (diode) Schottky contact with the III-V semiconductor. The gate is fed by an RF input signal. The input RF signal at the gate is amplified by the RF FET and the amplified RF signal appears at the drain of the RF FET.

[0003] As is also known in the art, the RF FET gate of the RF amplifier requires a quiescent DC bias voltage in addition to quiescent DC gate current. This DC bias voltage comes from a DC voltage source with the amount of current supplied to the gate (a gate current) typically being a function of the RF signal fed to the gate of the RF FET. One such DC voltage source is shown in FIG. 1. Here, the DC voltage source is a current mirror bias network having a source follower (SF) transistor circuit connected between the positive supply +V _D D and a negative supply -Vss. More particularly, in response to the RF input signal at the gate of the RF FET, the gate of the common source configured RF FET must be supplied the current, commonly known as gate current, from the source follower section of the current mirror bias network. This gate current supplied to the RF FET must be sufficient to supply proper amounts current for the rectifying Schottky contact gate of the RF FET. SUMMARY

[0004] In accordance with the present disclosure, a bias circuit is provided for an output transistor. The output transistor has a control electrode for controlling a flow of carriers between a first electrode and a second electrode, the second electrode is connected to ground potential. The bias circuit includes a pair of source follower transistors circuits. A first one of the pair of two source follower transistor circuits is coupled between a first voltage supply having a first polarity relative to the ground potential and a second voltage supply having a second polarity relative to ground potential; the first polarity being opposite to the second polarity, the first one of the pair of the source follower transistor circuits supplying a control signal to a second one of the pair of source follower transistor circuits. The second one of the pair of source follower transistors circuits is coupled between the second voltage supply and the ground potential and wherein the second one of the pair of source follower transistor circuits produces a bias signal for the control electrode of the output transistor.

[0005] In one embodiment, the bias circuit includes: a current source for producing a reference current from the first voltage supply to ground potential; a current mirror transistor coupled to the current source, the current mirror transistor having a control electrode coupled to the control electrode of the output transistor and a source electrode connected to the ground potential; and the second one of the pair of source follower transistor circuits provides a feedback control voltage at a control electrode of the current mirror transistor.

[0006] In one embodiment, the output transistor is a Field Effect Transistor (FET) and the control electrode of the output transistor is a Schottky contact gate; the first voltage supply has a positive polarity relative to ground potential; and the second voltage supply has a negative polarity relative to ground potential.

[0007] In one embodiment, the output transistor is a depletion mode FET

[0008] With such an arrangement, the current supplied to the rectifying Schottky contact gate of the output FET is from the second one of the pair of source follower transistor circuits connected between ground and the negative voltage supply and reduces power consumption.

[0009] The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.

DESCRIPTION OF DRAWINGS

[0010] FIG. 1 is a schematic diagram of a bias circuit according to the PRIOR ART; and

[0011] FIG. 2 is a schematic diagram of a bias circuit according to the disclosure.

[0012] Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

[0013] Referring now to FIG. 2, an RF amplifier circuit 10 is shown. The RF amplifier circuit 10 is formed on a common semiconductor 12, here, for example, a III-V semiconductor such as, for example GaN. The RF amplifier 10 includes a output field effect transistor FET Q2, is here an n-channel depletion-mode FET, having a grounded source electrode (S) with a drain electrode (D) connected to a +V _DD supply, here for example +25 to +30 volts, through an RF choke, LI . The gate electrode (G) of the FET Q2 is used to control a flow of carriers between a drain electrode (D) and a source electrode (S) of FET Q2; the gate electrode (G) here being fed an RF signal through a capacitor CI to produce an RF output signal at the drain electrode (D) that is coupled to an output through a capacitor C2, as shown. It is noted that since the FET Q2 is here a depletion-mode FET, its gate electrode (G) is typically DC biased at a potential more negative than ground potential, here the gate electrode (G) of FET Q2 is fed from a bias circuit 13, to be described below.

[0014] More particularly, the bias circuit 13 provides a constant DC voltage to the gate of FET Q2. The bias circuit 13 includes: a pair of source follower transistors networks, SF 1 and SF 2. The source follower transistor network, SF 1 , is coupled between +V _DD and - Vss, where here, for example -V _S s is -8 volts. The source follower network SF 2 is coupled between ground and -Vss- The source follower network SF 2 produces the bias signal for the control electrode, gate, of the output transistor Q2. The bias circuit 13 also includes a current source, here a current source configured FET Q5, for producing a reference current from +V _D D to ground; a current mirror transistor FET Ql coupled to the current source, FET 5, the current mirror transistor Ql having: a control electrode, gate electrode (G) coupled to the control electrode, gate electrode (G) of the output transistor FET Q2; and, a source electrode (S) connected to ground, as shown. Thus, the current from the drain electrode (D) to the source electrode (S) of the output FET Q2 mirrors the current passing from the drain electrode (D) to the source electrode (S) of FET Ql . It is noted that the source follower transistor network SF 2 provides a feedback control voltage (FB) at a control electrode, gate electrode (G) of the current mirror transistor FET Ql .

[0015] More particularly, the transistor FET Ql having a grounded source electrode (S) and a drain electrode (D) connected to the +V _DD supply through the current source configured FET Q5; the drain electrode (D) of Q l also being connected to the gate electrode (G) of a source follower FET Q3 included in the source follower transistor circuit, FET SF1 . The drain electrode (D) of Q3 is also connected to the +V _D D supply. The source electrode (S) of FET Q3 is coupled to -V _S s through a voltage level shifting network having a plurality of serially coupled diodes Dl - DM (where M is an integer selected to provide a proper quiescent operating voltage at the drain (D) of Ql ) and a current source configured FET Q7. Thus, the source follower transistor network SF 1 includes the FET Q3, the voltage level shifting network (the plurality of serially coupled diodes Dl - DM), and current source FET Q7. It is also noted that the voltage level shifting network (the plurality of serially coupled diodes Dl - DM) is connected to the FET at a node 20, such node 20 providing an output of the source follower transistor network SF 1. The output of the source follower transistor network SF 1 (that is, node 20) is coupled to the source follower transistor network SF 2. The source follower transistor network SF 2 includes a grounded drain, source follower FET Q6 and a current source configured FET Q4. [0016] More particularly, the node 20 is connected the gate electrode (G) of a depletion mode FET Q6, as shown. The drain electrode (D) of the FET Q6 is connected to ground and the source electrode (S) of FET Q6 is connected to - Vss through as current source configured FET Q4, as shown. Thus, the FET Q6 and FET Q4 provide a source follower transistor network SF 2. The source electrode (S) of FET Q6 is connected to a node 22. Also connected to node 22 are: the gate of FET Q2, through a resistor R3 and RF choke L2 and the gate electrode (G) of FET Ql . Thus, output node 20 of source follower transistor network SF 1 provides a control signal to the source follower transistor network SF 2 and the source follower transistor network SF 2 supplies voltage and current to the rectifying Schottky contact gate electrode (G) of the FET Q2.

[0017] It is noted that a feedback loop FB, which is includes the control signal, is provided from the drain electrode (D) of FET Ql , to the gate electrode (G) of FET Q3 through the source electrode (S) of FET Q3, through the diodes Dl-DM, to the gate electrode (G) of FET Q6 node 22 and then back to the gate electrode (G) of \ FET Ql to establish a reference current through the FET Ql at a drain electrode (D) voltage determined by diodes Dl-DM. It is noted that FET Q5 is placed into saturation so that the current between its source electrode (S) and drain electrode (D) is substantially constant with variations in the voltage across its source electrode (S) and electrode drain (D). Thus, a substantially constant current passes through FET Q5. The FET Q5 is then biased by the feedback loop FB to a current chosen by the size of FET Q5 and the source voltage determined by the number of diodes, M, of the set of number of diodes, M, of Dl-DM. The voltage on Ql gate electrode (G) is connected to node 22 which is also connected to the gate electrode (G) of the RF output FET Q2. Due to the FET Q2 being of the same semiconductor 12 as FET Ql it will therefore be biased to the same bias point as FET Ql . The current through the M diodes Dl-DM, in this example, is in the order of 5 milliamps (mA). The FET Q6 is biased to produce in this example, about 400 milliamps between its drain electrode (D) and source electrode (S). This 400 milliamp current splits between the drain electrode (D)- source electrode (S) path of FET Q4, the gate electrode (G) path to FET Q2; and the gate electrode (G) of Ql ; however only a few milliamps pass to the gate electrode(G) of FET Ql . Thus, in this example, a plus or minus 200 milliamp DC bias current is available to the gate electrode (G) of FET Q2 and constant 200 milliamps passes through FET Q4. Therefore, the current supplied to the gate electrode (G) of RF output FET Q2 is used for conduction current and leakage current and such current is supplied from the smaller -8 volt (-Vss) and ground supply rather than the larger +28 volt, (+VDD) and -8 volt (-Vss)supply used by source follower transistor network SF 1. To put it another way, because the magnitude of the voltage across the source follower circuit in FIG. 1 supplying current to the output FET is (|VSS|+|VDD|) whereas the magnitude of the voltage across the source follower network SF 2 feeding current to the output FET Q2 in FIG. 2 is |VSS|, which is less than |VDD|+|VSS|, power consumption is reduced.

[0018] Therefore less power is used by the circuit 10 compared with the circuit of FIG. 1.

[0019] It should now be appreciated a circuit according to the disclosure includes: an output transistor, the output transistor having a control electrode for controlling a flow of carriers between a first electrode and a second electrode, the second electrode is connected to ground potential; and a bias circuit, comprising: a pair of source follower transistors circuits; a first one of the pair of two source follower transistor circuits being coupled between a first voltage supply having a first polarity relative to the ground potential and a second voltage supply having a second polarity relative to ground potential, the first polarity being opposite to the second polarity, the first one of the pair of the source follower transistor circuits supplying a control signal to a second one of the pair of source follower transistor circuits; wherein the second one of the pair of source follower transistors circuits is coupled between the second voltage supply and the ground potential and wherein the second one of the pair of source follower transistor circuits produces a bias signal for the control electrode of the output transistor.

[0020] The circuit may include one or more of the following features independently or in combination with another feature to include: wherein the bias circuit includes a current source for producing a reference current from the first voltage supply to ground potential, a current mirror transistor coupled to the current source, the current mirror transistor having a control electrode coupled to the control electrode of the output transistor and a source electrode connected to the ground potential and wherein the second one of the pair of source follower transistor circuits provides a feedback control voltage at a control electrode of the current mirror transistor; wherein the output transistor is a Field Effect Transistor (FET) and the control electrode of the output transistor is a Schottky contact gate, the first voltage supply has a positive polarity relative to ground potential and the second voltage supply has a negative polarity relative to ground potential; or wherein the output transistor is a depletion mode FET. [0021] A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. Accordingly, other embodiments are within the scope of the following claims.