Field of the Invention

[001 ] The present invention related to the field of photovoltaic (PV) cells, particularly to the field of bifacial photovoltaic cells and processes for the manufacturing thereof.

Background of the Invention

[002] Increased energy consumption has caused concern over expected rapid depletion of existing energy sources, such as petroleum and coal. Thus, alternative energy sources, as alternatives to the existing energy sources, have been the focus of attention in recent years. Among the alternative energy sources, solar cells or photovoltaic cells are at the center of attention. PV silicon cells have been manufactured for many years. However, there still remain problems related to manufacturing cost, conversion efficiency and lifetime of the PV cell. The demand for increasing the efficiency of PV cells has given rise to various solutions. One such solution is the bifacial PV cell wherein both the front and the back of the PV cell are utilized in the energy conversion process. Bifacial PV cells are 15% - 40% more energy productive than monofacial PV cells.

[003] A common type of photovoltaic cell is based on a silicon substrate with p-type or n-type conductivity. The substrate is doped on one surface with an n-dopant (e.g., phosphorus) thus forming a n ⁺ layer, and the second surface is doped with a p-dopant (e.g., aluminum or boron) so as to form a p ⁺ layer. The processed p-type substrate thus forms a n+- p-p+ structure, and a n-type substrate forms a p+-n-n+ structure. It is a common procedure to treat the semiconductor substrates (wafers) before commencing the process of doping. The two most common pre-process treatments are saw damage removal wherein the mechanically induced defects of the substrate are removed, and the second common procedure is texturing of the substrate. Texturing creates micro pyramid-like shapes on the surface of the substrate, thus ultimately increasing the light absorption.

[004] Adding electrical contacts to the PV cells enables current collection and are applied in various formats. Generally, said electrical contacts cover only a small fraction of the surface area in order to avoid impeding the passage of light. Electrical contacts are typically applied in a grid pattern in order to minimize covering of the surface area. Monofacial photovoltaic cells usually have such a grid pattern on only one side of the cell, whereas bifacial photovoltaic cells have such a pattern on both sides, and can therefore collect light from any direction. [005] Different methods of dopant source deposition are known. Gas phase processes using POCI3 for phosphorus deposition and BCI3 or BBr3 for boron deposition are commonly used. Using 2 different dopant sources may easily result in doping of inappropriate regions, such as cross-doping of two dopant types in a single area. Additional steps involving deposition of protective layers and/or etching to remove dopant from some regions may be introduced which complicate cell fabrication.

[006] Geminus™ bifacial cells line (Schmid Group) has been prepared using chemical vapor deposition (CVD) for depositing boron dopant-containing film.

[007] To date, the best results in industrial production of p-type silicon-based bifacial cells were realized using a spin-on technique to deposit a dopant source.

[008] The inventors have previously stated it would be desirable to achieve low effective back surface recombination (which may be facilitated in an n+-p-p+ structure by a back P+ layer), as well as high minority carrier bulk lifetime. It would be desirable to obtain p-type silicon-based bifacial cells using boron as a p-dopant for p ⁺ layer formation which have an effective back surface recombination of 55-95 cm/s, and an average back to front short circuit current ratio of 0.75.

[009] Boron is a well-known p-dopant, and has the advantage of being sufficiently soluble in silicon, thereby allowing a higher P+- p barrier (in an n+-p-p-i- structure) which is effective at reducing back surface recombination. However, boron diffusion is associated with considerable degradation of bulk lifetime, which reduces photovoltaic cell efficiency. This obstacle has encouraged the widespread use of aluminum as a p-dopant, although aluminum tends to be less effective than boron at reducing back surface recombination.

[010] n-type silicon (in an n+-n-p+ structure) has also been used in order to reduce boron diffusion-associated degradation. Although n-type silicon is generally more resistant than p-type silicon to defects introduced by industrial processing, it is also more expensive.

[Oi l] There remains the need for PV cells of improved efficiency and processes for the manufacturing thereof that overcome the disadvantages of the prior art.

[012] It is an objective of the present invention to provide a manufacturing process of a PV cell, a PV cell module and device which overcome the disadvantages of the prior art.

Summary of the Invention

[013] The present invention provides a process for the manufacturing of a bifacial photovoltaic cell comprising:

a. Coating a substrate with a boron containing layer. b. Forming a cap layer over the boron containing layer which is on the second surface of said substrate.

c. Removing said boron containing layer from the surfaces of said substrate which are not covered with a cap layer.

d. Effecting the deposition of a phosphorous containing layer on the surfaces of said substrate which are not covered by said cap layer, and effecting diffusion of the phosphorous and the boron into the substrate.

e. Removing said phosphorous containing layer.

f. Texturing the substrate where there is no cap layer.

g. Effecting the deposition of a phosphorous containing layer on the first surface of said substrate and effecting diffusion of phosphorous into the substrate to form a second n-doped layer.

h. Forming a passivating and/or antireflective coating layer covering the n-doped layer on said substrate’s first surface.

[014] According to an embodiment of the invention there is provided a process for the manufacturing of a bifacial photovoltaic cell comprising further steps of removing said cap layer from said substrate’s second surface (hereinafter“cap layer removal step”) and forming a passivating and/or anti-reflective layer on substrate’s second surface (hereinafter“second surface passivating step”), wherein cap removal step precedes second surface passivating and both of said steps can be conducted after step (f). Said process comprising the following steps: a. Coating a substrate with a boron containing layer.

b. Forming a cap layer over the boron containing layer which is on the second surface of said substrate.

c. Removing said boron containing layer from the surfaces of said substrate which are not covered with a cap layer.

d. Effecting the deposition of a phosphorous containing layer on the surfaces of said substrate which are not covered by said cap layer, and effecting diffusion of the phosphorous and the boron into the substrate.

e. Removing said phosphorous containing layer.

f. Texturing the substrate where there is no cap layer, followed by the steps of: removing said cap layer from said substrate second surface, and forming a passivating and/or antireflective layer on substrate second surface. g. Effecting the deposition of a phosphorous containing layer on the first surface of said substrate and effecting diffusion of phosphorous into the substrate to form a second n-doped layer.

h. Forming a passivating and/or antireflective coating layer covering the n-doped layer on said substrate’s first surface.

[015] In yet a further optional embodiment, step (a) is conducted with simultaneously partial drive-in of boron.

[016] Further provided by the present invention is a process for the manufacturing of a bifacial photovoltaic cell comprising:

i. Forming a coated substrate wherein said substrate comprises an n-dopant

containing layer on substrate’s first surface wherein said n-dopant containing layer on substrate’s first surface is coated with a cap layer.

ii. Effecting doping of the substrate with a p-dopant on the surfaces of said

substrate which are not protected by the cap layer, concomitantly with effecting the drive-in (diffusion) into the substrate of the n-dopant from said n-dopant containing layer.

iii. Removing the cap layer from said first surface of the substrate.

iv. Forming a passivating and/or antireflective layer on the substrate’s second

surface.

v. Texturing the surface and edges of the substrate which are not covered by a passivating and/or antireflective layer.

vi. Effecting the deposition of a n-dopant containing layer on the first surface of said substrate and diffusion of said n-dopant into the substrate to form a second n-doped layer.

vii. Forming a passivating and/or antireflective layer on the first surface of the

substrate.

[017] The present invention further provides a photovoltaic cell wherein said photovoltaic cell is prepared according to the process of the present invention.

[018] According to an aspect of some embodiments of the invention, there is provided a bifacial photovoltaic cell comprising a silicon substrate, said substrate comprising an n ⁺ layer on a first surface thereof and a p ⁺ layer on a second surface thereof, the n ⁺ layer comprising an n-dopant, preferably phosphorous and the p ⁺ layer comprising boron, wherein a surface concentration of boron in the second surface is less than 4.10 ²⁰ atoms/cm ³ .

[019] Further provided by the present invention is a photovoltaic module comprising more than one of the photovoltaic cell described herein, wherein said more than one photovoltaic cells being interconnected to one another.

[020] In yet a further embodiment of the invention, there is provided a power plant comprising the photovoltaic module described herein.

[021] The present invention further provides an electric device comprising the photovoltaic cell described herein.

Brief Description of the Figures

Figure 1 - A block diagram of the process (a) to (h).

Figure 2 - Boron doped layer profile relating to two separate runs according to example 1. Figure 3 - A block diagram of the process (i) to (vii).

Figure 4 A - the short circuit current density (Jsc) curve measurement results are shown for cells produced according to the invention.

Figure 4B - the Open circuit voltage (Voc) results are shown for one batch of cells produced according to the invention.

Figure 4C- the Fill factor (FF) results are shown for one batch of cells produced according to the invention.

Figure 4D - the Efficiency (h) results are shown for one batch of cells produced according to the invention.

Detailed Description of the Invention

[022] Embodiments of the present invention relate to processes for the manufacturing of bifacial photovoltaic cells, PV cells, modules of PV cells and power plants and devices comprising said PV cells thereof. The specific conditions and sequence of the presently described process provides a bifacial photovoltaic cell of improved efficiency at front and rear illumination.

[023] While researching and developing PV cells and processes for the manufacturing thereof, the inventors have found that the process described herein improves the performance of the PV cells obtainable by said process. The process of the present invention has a number of advantages over known methods of manufacturing bifacial solar cells. Examples of said advantages are: 1) Controlling the maximum concentration of boron doping; 2) Minimizing the formation of the B-Si compound which is responsible for the increased surface recombination; 3) According to certain embodiments, adjusting the boron doping profile, by carrying out simultaneously the deposition of the boron-containing layer together with the first stage of boron diffusion.

[024] The following description of embodiments of the invention is with reference to figure 1. Numbers in parenthesis e.g. (103) correlate to the block numbers in figure 1.

[025] The present invention provides a process for the manufacturing of a bifacial photovoltaic cell comprising:

a. Coating a substrate with a boron containing layer.

b. Forming a cap layer over the boron containing layer which is on the second surface of said substrate.

c. Removing said boron containing layer from the surfaces of said substrate which are not covered with a cap layer.

d. Effecting the deposition of a phosphorous containing layer on the surfaces of said substrate which are not covered by said cap layer, and effecting diffusion of the phosphorous and the boron into the substrate.

e. Removing said phosphorous containing layer.

f. Texturing the substrate where there is no cap layer.

g. Effecting the deposition of a phosphorous containing layer on the first surface of said substrate and effecting diffusion of phosphorous into the substrate to form a second n-doped layer.

h. Forming a passivating and/or antireflective coating layer covering the n- doped layer on said substrate’s first surface.

[026] According to a preferred embodiment of the present invention there is provided a process for the manufacturing of bifacial PV cells comprising:

a. Coating a substrate with a boron containing layer using BC or BBr3 in the gas phase and effecting partial drive in of boron into said substrate (103).

b. Forming a cap layer over the boron containing layer which is on the second surface of the said substrate (104).

c. Removing the boron containing layer from the surfaces of the substrate which are not covered with a cap layer (105).

d. Effecting the deposition of a phosphorous containing layer on the surfaces of said substrate which are not covered by said cap layer and effecting diffusion of the phosphorous and the boron into the substrate, wherein said deposition of said phosphorous containing layer is effected by using POCI3 in the gas phase (106).

e. Removing said phosphorous containing layer (107).

f. Texturing the substrate’s surfaces which are not covered with a cap layer, wherein said texturing also removes the boron and phosphorous doped substrate layers, followed by the steps of:

removing said cap layer from said substrate second surface (107), and

Forming a passivating and/or antireflective layer on said substrate’s second surface (108).

g. Effecting the deposition of a phosphorous containing layer on the first surface of said substrate and effecting diffusion of phosphorous into the substrate to form a second n-doped layer, wherein said deposition of said phosphorous containing layer is effected by using POCI3 in the gas phase (109). Forming a coating layer covering the n-doped layer on the substrate’s first surface wherein said coating layer is a passivating and/or antireflective layer (110).

[027] According to a further embodiment of the invention the cap layer formed in step (b) may function as an anti-reflective and or passivating layer on the second surface of the substrate. In such an embodiment there is no need for cap layer removal and second surface passivating steps.

[028] In another embodiment of the invention a step of chemical edge isolation is carried out after step (g) or step (h). Chemical edge isolation can be carried out according to any method known in the art. The terms“silicon substrate”,“substrate” and“wafer” are used interchangeably and have the same meaning in the context of the present invention. The substrates which are suitable for use in the present invention can be selected from groups of silicon wafers with n or p type conductivity.

[029] According to some embodiments of the present invention the substrate used in the process is a silicon wafer which undergoes pre-process treatment which includes inspection (101) and saw damage removal (102). According to certain embodiments of the present invention said substrate may also undergo texturing as a pre-process treatment. However, according to some embodiments said pre-process texturing is not necessary.

[030] The term texturing refers to the operation of creating a texture of the surface of the substrate which can be carried out according to known methods in the art. Typically, texturing creates micro pyramid-like shapes on the surface of the substrate. Said texturing also can remove doped layers from the substrate.

[031] The term drive-in refers to a process of diffusion wherein atoms of p-dopant and/or n-dopant diffuse from p and/or n dopant containing layers on the surface of the substrate into the substrate.

[032] According to certain embodiments of the present invention suitable boron deposition techniques for forming a boron-containing layer are selected from among known boron deposition techniques. Non-limiting examples of said techniques are: chemical vapor deposition and physical vapor deposition. Gas phase deposition methods with BBr3 or BCI3 as boron carriers are the preferred techniques.

[033] According to some embodiments of the invention during the step of boron deposition some diffusion of boron into the substrate can occur.

[034] According to the present invention the deposition of boron occurs on all surfaces of the substrate.

[035] Step (b) of forming a cap layer is carried out such that the cap layer coats the boron containing layer on the second surface of the substrate. Said cap layer is effected as described herein.

[036] Herein the phrases "n-dopant containing layer" and "boron-containing layer" encompass layers containing the indicated ingredient (e.g., phosphorous, n-dopant and boron, p-dopant) and which are not part of the substrate (e.g., layers of a substance deposited onto a surface of the substrate).

[037] In contrast, the phrase "n-doped layer" refers herein to a portion of the semiconductor substrate which has been doped with an n-dopant (e.g., upon diffusion of an n- dopant from an n-dopant containing layer into the substrate), and the phrase "boron-doped layer" refers herein to a portion of the semiconductor substrate which has been doped with boron (e.g., upon diffusion of boron from a boron-containing layer into the substrate).

[038] In some embodiments a thickness of the boron-containing layer is in a range of from 1 to 80 nm (optionally from 2 to 80 nm). In some such embodiments, the thickness of the deposited layer is in the range of from 1 to 40 nm (optionally from 2 to 40 nm). In some such embodiments, the thickness of the deposited layer is in the range of from 1 to 20 nm (optionally from 2 to 20 nm).

[039] In some embodiments a thickness of the boron-containing layer is selected such that the boron-containing layer contains an amount of boron (per surface area) which is suitable for providing a desired concentration of boron in a p ⁺ layer (according to any of the respective embodiments described herein) after effecting diffusion of boron (according to any of the respective embodiments described herein).

[040] For any given composition of the boron-containing layer, a thickness (of the boron-containing layer) may readily be selected so as to provide a desired boron concentration.

[041] According to some embodiments of the invention, subsequent to cap layer coating of the boron containing layer on the second surface, said boron containing layers on the substrate which are not protected by a cap layer, and can be on the surfaces and edges are removed by methods known in the art. A non-limiting example of said methods is etching in an HF water solution.

[042] In some embodiments of the invention, subsequent to step (c), the substrate obtained is coated on the second surface with a boron containing layer that is coated with a cap layer. The other surfaces of the substrate, i.e. the first surface and the edges are clear from boron a containing layer

[043] According to some embodiments of the invention step (d) of the process comprises the deposition of a phosphorous containing layer and driving-in (diffusion) into the substrate of boron from the boron containing layer and phosphorous from the phosphorous containing layer.

[044] According to specific embodiments of the invention, the deposition of a phosphorous containing layer can be effected by methods known in the art. Preferably, said phosphorous containing layer is effected by exposing the substrate to POC in the gas phase. Drive-in (diffusion) into the substrate of the boron and phosphorous is effected using the temperature range of 700 to 1050°C, preferably at a temperature in the range of 750 to 1020°C.

[045] In some embodiments of any of the embodiments described herein, forming an n-doped layer (steps (d) and (g)) is effected in two stages: first - forming on the surface of the substrate the phosphorous containing layer (which could be a phosphosilicate glass) for example under a POCI3 containing gaseous atmosphere at moderate temperatures and second - diffusion of phosphorous into the substrate by elevating the temperature.

[046] According to certain aspects of the invention the deposition of a phosphorous containing layer and the diffusion of the phosphorous into the substrates is simultaneous.

[047] The phrase simultaneous in the meaning of step (d) and (g) of the present process refers to operations which occur in the same process stage. It is understood that at least initial deposition of the phosphorous containing layer is required before the diffusion of the n- dopant (phosphorous) commences. [048] In some embodiments of the present invention, subsequent to carrying out step (d), the substrate comprises a second surface coated with a boron containing layer which is protected by a cap layer, and a first surface and edges of the substrate coated with phosphosilicate glass (PSG) and containing n-doped layer with some boron impurities.

[049] According to some embodiments of the invention the process further comprises a step (step (e)) of removing said PSG (where formed) and n-doped layers from all surfaces of the substrate (including edges) which are not protected by a cap layer. Said PSG and n-doped layers are removed by acidic etching and by alkaline texturing (step (f)) respectively (107).

[050] In some embodiments, removing said first n-doped layer (e.g., an n ⁺ layer) on the first surface is effected so as to concomitantly remove any n-doped layer (e.g., n-doped islands) present elsewhere.

[051] Methods of etching and texturing of the substrate are known in the art. In some embodiments, etching and texturing of (e.g., of an n-doped layer) is effected by an alkaline solution (e.g., a solution that comprises sodium hydroxide).

[052] According to certain embodiments of the invention the cap layer is removed from the second surface of the substrate (cap layer removal step). Removal of the cap layer can be carried out according to methods known in the art. In some embodiments of the invention the cap layer is removed by HF solution etching.

[053] In accordance with certain embodiments of the invention, subsequent to the removal of the cap layer from said second surface, said second surface is coated with a passivating and/or antireflective layer (second surface passivating step). Passivating and/or antireflective coatings are effected as described hereinafter.

[054] According to certain embodiments of the invention said cap layer may function as a passivating and/or antireflective coating. In such an embodiment, cap layer removal and second surface passivating steps are optional.

[055] In accordance to some embodiments of the invention subsequent to step (f) the substrate comprises a second surface doped with boron wherein said second surface is coated with a passivating and/or antireflective coating, and the first surface and edges of said substrate are texturized.

[056] According to some embodiments of the invention, subsequent to the cap removal layer and second surface passivating steps, phosphorous deposition and phosphorous diffusion by a gas phase process are effected (step (g)) herein referred to as second n-doped layer [057] Said second n-doped layer may be formed by any suitable technique known in the art for n-doping (e.g., any n-doping technique described herein), including, without limitation, gas phase diffusion, ion implantation, and/or use of an n-dopant containing layer (e.g., according to any of the respective embodiments described herein).

[058] Preferably, said second n-doped layer is effected by exposing the substrate to POCI3 in the gas phase at a temperature in the range of 700°C to 950°C, preferably 750°C to 900°C

[059] In some embodiments of any of the embodiments described herein, forming an n-doped layer (steps (d) and (g)) is effected in two stages: first exposing the substrate to POCI3 in the gas phase at a temperature in the range of 700 °C to 900 °C -and second - diffusion of phosphorous into the substrate by elevating the temperature up to 950°C.

[060] In accordance with some embodiments of the invention, subsequent to forming the second n-doped layer on said first surface, said first surface is coated with a passivating and/or antireflective coating in accordance with passivating and/or antireflective coating techniques known in the art or described herein. Optionally, a phosphosilicate glass (PSG) layer which may have formed on said first surface is removed prior to forming a passivating and/or antireflective coating on said first surface. Said removal of PSG can be carried out according to methods known in the art or described herein.

[061] In some embodiments of the present invention a second n ⁺ layer prepared according to any of the respective embodiments described herein, is characterized by a sheet resistance in a range of from 70 to 150 Ohms/a.

[062] As used herein and in the art, the term "Ohms" in the context of a sheet resistance is interchangeable with the terms "Ohms per square" and "Ohms/D", an accepted unit of sheet resistance which is used in the art to differentiate units of sheet resistance from units of resistance of a bulk material (although Ohm units and Ohm per square units are dimensionally equal).

[063] In some embodiments of the present invention, a first n ⁺ layer which is removed according to any of the respective embodiments described herein is characterized by a sheet resistance of less than 70 Ohms, optionally less than 40 Ohms, for example, in a range of from 8 to 25 Ohms.

[064] In some embodiments of the invention, texturing is carried out in order to remove a first n-doped layer from the substrate and provide the substrate surface with a relief decreasing optical reflectance and to prevent shunting at the substrate edges. [065] According to some embodiments of the invention, the process further comprises removing the cap layer subsequently to removing the n-doped layer on the first surface by texturing, and prior to forming the passivating and/or antireflective coating on the second surface.

[066] Herein, a "passivating and/or antireflective coating" refers to one or more dielectric coatings, each of which has a passivating effect and/or an antireflective effect.

[067] Forming a passivating coating on the second surface may optionally comprise leaving a SiB layer on said surface arisen during the boron drive-in process

[068] Herein, the term "SiB" refers to a combination of silicon and boron atoms, wherein a concentration of the boron atoms exceeds the solubility of boron atoms in Si at diffusion temperature (up to about 1100 °C), e.g., above about 5· 10 ²⁰ atoms/cm ³ . The term "SiB" is not intended to imply a 1:1 stoichiometry of Si to B. SiB may optionally be identified as a substance in which an absolute concentration of boron atoms (e.g., as determined by secondary ion mass spectrometry (SIMS)) is significantly greater than a concentration of electrically active (i.e., dissolved) boron atoms (e.g., as determined by electrochemical capacitance- voltage profiling (ECV)).

[069] Additional examples of a passivating coating according to any of the respective embodiments described herein include, without limitation, layers of aluminum oxide (e.g., AI2O3) and/or silicon oxide. A passivating and/or antireflective coating (e.g., an aluminum oxide, silicon oxide, silicon nitride and/or silicon oxynitride coating) may optionally be deposited (e.g., using sputtering and/or chemical vapor deposition) and/or formed by a reaction on the substrate surface, for example, by chemical and/or thermal oxidation of silicon in the substrate to form silicon oxide and/or diffusion of boron into silicon to form SiB (e.g., as described herein). The passivating and/or antireflective may have any suitable thickness (e.g., according to any of the respective embodiments described herein).

[070] The passivating and/or antireflective coating on the second surface may comprise a layer of silicon nitride on top of a layer of silicon oxide which coats the substrate surface. According to a further option of the invention, said passivating and/or antireflective coating comprises a silicon nitride layer on top of a layer of boron silica glass (BSG). Said BSG may be formed under elevated temperature conditions, e.g. the temperature under which diffusion of boron occurs.

[071] The terms "silicon nitride" and "SiN", which are used herein interchangeably, refer herein to a family of substances composed substantially of silicon and nitrogen, with various stoichiometries of Si and N (e.g., S13N4), although some amounts of additional atoms (e.g., hydrogen) may be present as impurities.

[072] The phrase“silicon oxynitride” refers to SiN _x O _y , wherein each of x and y is a positive number of up to 2 (e.g., between 0.1 and 2), and x and y are in accordance with the valence requirements of Si, N and O. Some amounts of additional atoms (e.g., hydrogen) may be present as impurities.

[073] In some embodiments, the passivating and/or antireflective coating is formed such that a border of the passivating and/or antireflective coating corresponds to a desired border of a subsequently formed second n-doped layer (according to any of the respective embodiments described herein). The passivating and/or antireflective coating may determine the border of a second n-doped layer by preventing n-doping across the border (i.e., in a region covered by the passivating and/or antireflective coating), facilitating separation (i.e., reducing overlap) of an n-doped layer and a boron-doped layer, providing high shunt resistance.

[074] In some embodiments, forming the passivating and/or antireflective coating is effected such that the passivating and/or antireflective coating covers an edge of the substrate (i.e., a surface between the first surface and the second surface, which is optionally perpendicular to each of the first surface and second surface),. In some such embodiments, the passivating and/or antireflective coating prevents formation of a n-doped layer (according to any of the respective embodiments described herein) on an edge of the substrate.

[075] In some embodiments of any of the embodiments described herein, diffusion of the n-dopant and diffusion of the boron are effected simultaneously. In some embodiments, simultaneous diffusion of n-dopant and boron are effected by heating, optionally by exposure to a temperature in a range of from 850 °C to 1050 °C.

[076] In some embodiments of the present invention, the boron-containing layer (e.g., the thickness, boron-concentration, and composition of the layer) and conditions of diffusion (e.g., temperature and/or time of diffusion) are selected such that a concentration of boron in said doped layer is less than 10 ²¹ atoms/cm ³ , optionally less than 3· 10 ²⁰ atoms/cm ³ , optionally less than 10 ²⁰ atoms/cm ³ , optionally less than 3· 10 ¹⁹ atoms/cm ³ and optionally less than 10 ¹⁹ atoms/cm ³ .

[077] Herein, a concentration in a doped layer, in units of amount (e.g., atoms) per volume (e.g., cm ³ units) refers to a maximal concentration in a doped layer of the substrate (e.g., a maximal concentration at any depth up to a depth of about 1 pm).

[078] In some embodiments the boron-containing layer (e.g., the thickness, boron- concentration, and composition of the layer) and conditions of diffusion (e.g., temperature and/or time of diffusion) are selected such that doping of that layer with boron forms an p ⁺ layer characterized by a sheet resistance according to any of the respective embodiments described herein, e.g., in a range of from 15 to 300 ohms, from 30 to 300 ohms, from 30 to 200 ohms and/or from 30 to 150 ohms.

[079] The skilled person will be readily capable of modulating conditions (e.g., temperature and/or duration of thermal treatment, and/or amount of dopant in a dopant- containing layer) to arrive at a desired amount (e.g., concentration) of dopant (e.g., boron) and/or sheet resistance (which is affected by amount of dopant) in that p ⁺ layer, according to any of the respective embodiments described herein.

[080] In some embodiments wherein a boron-containing layer is formed prior to an n- dopant-containing layer, the process further comprises etching the first surface subsequent to formation of the boron-containing layer and prior to formation of the n-dopant-containing layer. In some embodiments, such etching is performed so as to remove any boron-containing layer present on the first surface. In some embodiments the process comprises forming a cap layer (according to any of the respective embodiments described herein) above the boron- containing layer on the second surface, for example, a cap layer selected to protect the boron- containing layer on the second surface during etching of the first surface.

[081] The present invention further provides a process for the manufacturing of a bifacial photovoltaic cell comprising the following step with reference to Figure 3 (Numbers in parenthesis correlate to the block numbers in the figures):

i. Forming a coated substrate wherein said substrate comprises an n-dopant containing layer on substrate’s first surface wherein said n-dopant containing layer on substrate’s first surface is coated with a cap layer.

ii. Effecting doping of the substrate with a p-dopant on the surfaces of said substrate which are not protected by the cap layer, concomitantly with effecting the drive- in (diffusion) into the substrate of the n-dopant from said n-dopant containing layer (301).

iii. Removing the cap layer from said first surface of the substrate (302).

iv. Forming a passivating and/or antireflective layer on the substrate’s second surface (303).

v. Texturing the surface and edges of the substrate which are not covered by a passivating and/or antireflective layer (304). vi. Effecting the deposition of a n-dopant containing layer on the first surface of said substrate and diffusion of said n-dopant into the substrate to form a second n- doped layer (305).

vii. Forming a passivating and/or antireflective layer on the first surface of the substrate (306).

[082] In accordance with certain embodiments of the present invention with reference to Fig. 3, step (i) of forming a coated substrate wherein said substrate comprises an n-dopant containing layer on substrate’s first surface wherein said n-dopant containing layer on substrate’s first surface is coated with a cap layer, is carried out by effecting the deposition of an n-dopant containing layer on the first surface of the substrate (Oi l) and coating said n-dopant containing layer with a cap layer (012).

[083] In accordance with further embodiments of the present invention, step (i) of forming a coated substrate wherein said substrate comprises an n-dopant containing layer on substrate’s first surface wherein said n-dopant containing layer on substrate’s first surface is coated with a cap layer, is carried out by exposing the substrate to an n-dopant in the gas phase to deposit an n-dopant containing layer on said substrate (021) and coating said n-dopant containing layer on the first surface of the substrate with a cap layer (022). Said substrate is then subjected to etching (023) which removes the n-dopant containing layer where there is no cap layer coating and may remove n-doped layers from the substrate where there is no cap layer coating.

[084] According to certain embodiments of the invention, the cap layer formed on the first surface of the substrate also coats the edges of the substrate.

[085] In accordance with certain embodiments of the present invention, step (i) of forming a coated substrate wherein said substrate comprises an n-dopant containing layer on substrate’s first surface wherein said n-dopant containing layer on substrate’s first surface is coated with a cap layer, is carried out by coating the substrate on the second surface with a cap layer (031), exposing the substrate to an n-dopant in the gas phase to deposit an n-dopant containing layer on the substrate surfaces which are not coated with a cap layer (032), remove said cap layer from said second surface (033), coat the first surface of the substrate with a cap layer (034). According to the present embodiment of the invention, the cap layer formed on the first surface of the substrate also coats the edges of the substrate. [086] In some embodiments of any of the embodiments described herein, the process further comprises forming electrical contacts on each of the first surface and the second surface. Electric contacts may be formed according to methods well known in the art.

[087] In order to allow light to reach the substrate of a bifacial photovoltaic cell, the contacts on both surfaces are preferably configured so as to allow most of the light to pass through to the substrate, thereby allowing the photovoltaic cell to produce electricity from illumination on either side of the cell. For example, the contacts may optionally be configured in a grid pattern.

[088] In some embodiments, contacts are selectively formed (optionally using a mask) on regions of the second surface which have a greater concentration of boron than the rest of the second surface. In some embodiments, such regions are formed using a boron-containing layer which has a greater thickness and/or concentration in such regions (according to any of the respective embodiments described herein).

[089] According to an aspect of some embodiments of the invention there is provided a bifacial photovoltaic cell prepared by the process of any one of respective embodiments described herein.

Cap layer:

[090] Herein, the terms "cap" and "capping" refer to a layer being above ("capping") a boron-containing layer (i.e., farther from the substrate than the boron-containing layer)and are not intended to be further limiting.

[091] In some embodiments of the invention, a thickness of the cap layer is in a range of from 2.5 to 80 nm. In some embodiments, the thickness is in a range of from 5 to 40 nm. In some embodiments, the thickness is in a range of from 5 to 20 nm.

[092] The cap layer may be formed according to any suitable technique known in the art for forming a cap layer according to any of the respective embodiments described herein. Examples of suitable techniques include, without limitation, sputtering (e.g., DC sputtering and/or radio frequency sputtering), physical vapor deposition and chemical vapor deposition.

[093] Herein and in the art, "radio frequency sputtering" refers to sputtering whereby a sputtering target may optionally be subjected to a charged plasma particles, such as ionized gas (optionally using strong electric and/or magnetic fields to direct plasma particles in the general location of the target), with an alternating voltage bias (e.g., alternating at a radio frequency, such as 13.56 MHz) accelerating the plasma particles. [094] Herein and in the art, " DC sputtering" refers to sputtering whereby ions in a plasma are directed towards a sputtering target (to thereby bombard the target). Accelerated ions in the plasma are optionally neutralized (by an electron source) such that the target is bombarded by neutrally charged particles.

[095] The thickness of a cap layer may be controlled, for example, by controlling the duration of a deposition process (e.g., duration of sputtering). Control over the thickness of the cap layer may optionally be utilized to allow control over properties of the cap layer, for example, permeability to boron, n-dopant and/or etching solution.

[096] In some embodiments the cap layer comprises an inert substance. The cap layer is optionally formed by deposition of a layer of the inert substance, optionally by sputtering (e.g., DC and/or radio frequency sputtering).

[097] Examples of inert substances suitable for forming a cap layer include, without limitation, silicon nitride, silicon oxynitride and silicon oxide.

[098] In some embodiments of the present invention the selection of a cap layer having certain properties (according to any of the respective embodiments described herein), may optionally be by effecting formation of a cap layer having a thickness sufficient to result in the indicated properties, for example, a thickness of at least 5 nm (optionally up to 40 nm, according to any of the respective embodiments described herein). Alternatively or additionally, selection may optionally be effected by comparing results of different cap layer compositions (e.g., silicon nitride, silicon oxide and/or silicon oxynitride) and/or different methodologies of cap layer formation (according to any of the respective embodiments described herein).

[099] In some embodiments forming a cap layer above the boron-containing layer is effected prior to effecting diffusion (e.g., by thermal treatment). In some embodiments, forming the cap layer above the boron-containing layer is effected prior to deposition of phosphorus- containing (n-dopant-containing) layer. In such embodiments, the cap layer protects the boron- containing layer (e.g., until diffusion is effected).

[100] In some embodiments according to any of the embodiments described herein, the cap layer is selected such that it prevents removing of the boron doped layer from the second surface by texturing (according to any of the respective embodiments described herein), except of the border around the edge.

[101] In some embodiments the process further comprises removing the cap layer according to any of the respective embodiments described herein subsequently to removal of an n-doped layer by texturing (according to any of the respective embodiments described herein). In according with a further embodiment of the invention said cap layer removal is prior to forming a passivating and/or antireflective coating according to any of the respective embodiments described herein. Removal of the cap layer can be carried out by means and methods known to the skilled person in the art, for example by chemical means, including but not limited to the use of an HF solution. In some such embodiments, the cap layer protects the boron-doped layer from the texturing process.

[102] In some embodiments described herein, the cap layer is selected such that it reduces an amount of boron which escapes into the surrounding atmosphere upon effecting diffusion of boron according to any of the respective embodiments described herein (i.e., in comparison to an amount of boron which escapes into the surrounding atmosphere, under the same conditions, in the absence of the cap layer).

[103] In some embodiments, the cap layer is selected such that no more than 5 % of boron in the boron-containing layer escapes into the surrounding atmosphere upon effecting the diffusion of said boron. In some embodiments, the cap layer is selected such that no more than 3 % of boron in the boron-containing layer escapes into the surrounding atmosphere upon effecting the diffusion of said boron. In some embodiments, the cap layer is selected such that no more than 2 % of boron in the boron-containing layer escapes into the surrounding atmosphere upon effecting the diffusion of said boron. In some embodiments, the cap layer is selected such that no more than 1 % of boron in the boron-containing layer escapes into the surrounding atmosphere upon effecting the diffusion of said boron. In some embodiments, the cap layer is selected such that no more than 0.5 % of boron in the boron-containing layer escapes into the surrounding atmosphere upon effecting the diffusion of said boron. In some embodiments, the cap layer is selected such that no more than 0.3 % of boron in the boron- containing layer escapes into the surrounding atmosphere upon effecting the diffusion of said boron. In some embodiments, the cap layer is selected such that no more than 0.2 % of boron in the boron-containing layer escapes into the surrounding atmosphere upon effecting the diffusion of said boron. In some embodiments, the cap layer is selected such that no more than 0.1 % of boron in the boron-containing layer escapes into the surrounding atmosphere upon effecting the diffusion of said boron. In some embodiments, the cap layer is selected such that no more than 0.05 % of boron in the boron-containing layer escapes into the surrounding atmosphere upon effecting the diffusion of said boron. In some embodiments, the cap layer is selected such that no more than 0.03 % of boron in the boron-containing layer escapes into the surrounding atmosphere upon effecting the diffusion of said boron. In some embodiments, the cap layer is selected such that no more than 0.02 % of boron in the boron-containing layer escapes into the surrounding atmosphere upon effecting the diffusion of said boron. In some embodiments, the cap layer is selected such that no more than 0.01 % of boron in the boron- containing layer escapes into the surrounding atmosphere upon effecting the diffusion of said boron.

[104] In some embodiments, the cap layer is selected such that it reduces an amount of boron which diffuses into the first surface of the substrate upon effecting diffusion of boron according to any of the respective embodiments described herein (i.e., in comparison to an amount of boron which diffuses into the first surface, under the same conditions, in the absence of the cap layer).

[105] In some embodiments, forming each of the boron-containing layer and cap layer above the boron-containing layer (on the second surface of the substrate) is effected prior to forming the n-dopant-containing layer (on the first surface of the substrate). In some such embodiments, the cap layer (which is formed prior to the n-dopant-containing layer) is selected such that it reduces an amount of n-dopant (e.g., phosphorus) which diffuses into the second surface of the substrate upon effecting diffusion of the n-dopant and boron according to any of the respective embodiments described herein (i.e., in comparison to an amount of n-dopant which diffuses into the second surface, under the same conditions, in the absence of the cap layer).

[106] In some embodiments, the cap layer is formed such that a border of the cap layer corresponds to a desired border of an n-doped layer (according to any of the respective embodiments described herein). The cap layer may optionally determine the border of an n- doped layer by preventing n-doping across the border (i.e., in a region covered by the cap layer), for example, facilitating separation (i.e., reducing overlap) of an n-doped layer and a boron-doped layer, which can enhance shunt resistance.

[107] In some embodiments described herein, forming the cap layer is effected such that the cap layer covers an edge of the substrate (i.e., a surface between the first surface and the second surface, which is optionally perpendicular to each of the first surface and second surface), and optionally covers all of the edges of the substrate. In some such embodiments, the cap layer prevents formation of an n-doped layer (according to any of the respective embodiments described herein) on an edge of the substrate. The photovoltaic cell:

[108] According to some embodiments of the present invention there is provided a bifacial photovoltaic cell comprising a semiconductor substrate (e.g., silicon), the substrate comprising an n ⁺ layer on a first surface thereof and a p ⁺ layer on a second surface thereof, the n ⁺ layer comprising an n-dopant (e.g., phosphorus) and the p ⁺ layer comprising boron. Preferably, the photovoltaic cell further comprises electrical contacts on each of said first surface and said second surface, which are suitable for a bifacial cell (e.g., the contacts do not cover a large proportion of either surface). In some embodiments, the bifacial photovoltaic cell is prepared by a process described herein in any of the respective embodiments and any combination thereof

[109] In some embodiments described herein for a bifacial photovoltaic cell, a concentration of boron in a p ⁺ layer is less than 3· 10 ²⁰ atoms/cm ³ , optionally less than 10 ²⁰ atoms/cm ³ , optionally less than 3· 10 ¹⁹ atoms/cm ³ and optionally less than 10 ¹⁹ atoms/cm ³ .

[110] According to some embodiments, a specific shunt resistance of the photovoltaic cell is at least 5,000 Ohm*cm ² (i.e., Ohm multiplied by cm ² ), optionally at least 5,500 Ohm*cm ² , optionally at least 6,000 Ohm*cm ² , optionally at least 6,500 Ohm*cm ² , and optionally at least 7,000 Ohm*cm ² . As specific shunt resistance may depend on the area and shape of a photovoltaic cell, the aforementioned specific shunt resistance may be determined for a photovoltaic cell having an area of about 240 cm ² and being substantially square (i.e., having a circumference of about 61 cm).

[111] Without being bound by any particular theory, it is believed that known techniques for enhancing shunt resistance (e.g., laser edge isolation) are less effective (and even deleterious) in high-efficiency cells.

[112] In some embodiments the p ⁺ layer is characterized by a sheet resistance according to any of the respective embodiments described herein, e.g., in a range of from 15 to 300 Ohms, from 30 to 300 Ohms, from 50 to 200 Ohms and/or from70 to 150 Ohms.

[113] In some embodiments, the first surface is texturized.

[114] In some embodiments described herein, the second surface is texturized. Optionally the first and second surfaces are both texturized.

[115] In some embodiments of the present invention the photovoltaic cell further comprises a passivating and/or antireflective coating (according to any of the embodiments described herein) on at least a portion of the second surface, optionally the entire second surface. In some embodiments, this passivating and/or antireflective coating covers also at least a portion of, and optionally all of, the edges of the substrate; and optionally covers a portion of the first surface bordering an edge of the substrate (e.g., an area of the first surface having a width of up to 0.5 mm, optionally from 0.1-0.5 mm, bordering the edge).

[116] In some embodiments, the photovoltaic cell further comprising another passivating and/or antireflective coating (according to any of the embodiments described herein) on at least a portion of the first surface, optionally the entire first surface. In some embodiments, the same passivating and/or antireflective coating covers at least a portion of each of the first surface and the second surface, and optionally the entire first surface and second surface. A passivating and/or antireflective coating on the first surface may be the same as, or different than a passivating and/or antireflective coating on the second surface.

[117] In some embodiments, a total thickness of passivating and antireflective coating (according to any of the embodiments described herein) is in a range of from 1 to 90 nm, optionally in a range of from 2 to 80 nm, and optionally in a range of from 5 to 75 nm.

[118] Examples of passivating and/or antireflective coatings according to any of the respective embodiments described herein include, without limitation, coatings comprising silicon oxide, silicon nitride, silicon oxynitride, T1O2, ZrC , and/or Ta ₂ 0s. When more than one layer is present in a passivating and/or antireflective coating, the different layers may differ, for example, in refractive index (e.g., an upper layer having a lower refractive index than a lower layer) and/or components (e.g., one layer comprising silicon oxynitride and another layer comprising silicon nitride).

[119] In some embodiments an n ⁺ layer of the photovoltaic cell prepared according to any of the respective embodiments described herein, is characterized by a sheet resistance in a range of from 70 to 150 Ohms.

[120] In some embodiments a concentration of boron in a p ⁺ layer (according to any of the respective embodiments described herein) is greater in regions underlying said electrical contacts on said second surface. In some embodiments, a concentration of boron in regions underlying said electrical contacts is at least 100 % (twice) greater than a concentration of boron in the rest of the p ⁺ layer. In some embodiments, a concentration of boron in regions underlying said electrical contacts is at least 200 % (3-fold) greater than a concentration of boron in the rest of the p ⁺ layer. In some embodiments, a concentration of boron in regions underlying said electrical contacts is at least 400 % (5-fold) greater than a concentration of boron in the rest of the p ⁺ layer. In some embodiments, a concentration of boron in regions underlying said electrical contacts is at least 900 % (10-fold) greater than a concentration of boron in the rest of the p ⁺ layer. [121] In some embodiments the photovoltaic cell further comprises a SiB layer on the second surface, optionally a SiB layer prepared according to any of the respective embodiments described herein. The SiB layer may optionally be a passivating coating according to any of the respective embodiments described herein.

[122] According to some embodiments of the present invention, a p ⁺ layer (according to any of the respective embodiments described herein) is characterized by a sheet resistance of at least 15 Ohms/p. In some embodiments, the sheet resistance of a p ⁺ layer is in a range of from 15 to 300 Ohms/n. In some embodiments, the sheet resistance of a p ⁺ layer is in a range of from 50 to 200 Ohms/D. In some embodiments, the sheet resistance of a p ⁺ layer is in a range of from 70 to 150 Ohms/D.

[123] According to some embodiments, a p ⁺ layer of the photovoltaic cell does not cover an area bordering an edge of the substrate thereof, the area having a width in a range of 0.1-0.5 mm. Such an area may optionally be prepared by masking and/or etching the second surface, according to any of the respective embodiments described herein.

[124] In any of the embodiments described herein (according to any of the aspects described herein), the semiconductor substrate comprises silicon, and optionally consists essentially of doped silicon (e.g., p-type or n-type silicon).

[125] In any of the embodiments described herein (according to any of the aspects described herein), the semiconductor substrate may optionally be an n-type semiconductor (e.g., n-doped silicon), such that the photovoltaic cell has a p ⁺ -n-n ⁺ structure; or a p-type semiconductor (e.g., p-doped silicon), such that the photovoltaic cell has a n ⁺ -p-p ⁺ structure.

[126] In some embodiments described herein, an effective back surface recombination of the photovoltaic cell (according to any of the respective embodiments described herein) is less than 150 cm/second. In some embodiments, the effective back surface recombination is less than 100 cm/second. In some embodiments, the effective back surface recombination is less than 60 cm/second. In some embodiments, the effective back surface recombination is less than 30 cm/second. In some embodiments, the effective back surface recombination is less than 20 cm/second. In some embodiments, the effective back surface recombination is less than 10 cm/second. In some embodiments, the effective back surface recombination is less than 5 cm/second.

[127] Effective surface recombination (e.g., of the back surface) may be determined according to any suitable technique known in the art, for example, by measuring spectral internal quantum efficiency upon illumination (e.g., of the back side). Optionally, effective surface recombination is determined as described in Eisenberg et al. [ Energy Procedia 2016, 92:16-23], the contents of which are incorporated herein by reference (especially contents relating to measurement of surface recombination).

[128] In some embodiments, a front side efficiency of the photovoltaic cell (according to any of the respective embodiments described herein) is at least 19 %. In some embodiments, the front side efficiency is at least 19.5 %. In some embodiments, the front side efficiency is at least 20 %. In some embodiments, the front side efficiency is at least 20.5 %. In some embodiments, the front side efficiency is at least 21 %. In some embodiments, the front side efficiency is at least 21.5 %. In some embodiments, the front side efficiency is at least 22 %.

[129] Herein, the phrase "front side efficiency" refers to efficiency (as described herein) of the photovoltaic cell under conditions wherein only one (front) side of the cell is exposed to illumination (e.g., wherein the other side is placed on a black opaque surface). The "front side" exposed to illumination is defined as whichever side is characterized by the higher efficiency.

[130] The efficiency of a cell (e.g., with respect to illumination of any given side thereof) may be determined by determining the maximal power output of the cell, and dividing by the input light irradiance, at standard test conditions.

[131] In some embodiments described herein, an open circuit voltage of the photovoltaic cell (according to any of the respective embodiments described herein) is at least 620 mV. In some embodiments, the open circuit voltage is at least 630 mV. In some embodiments, the open circuit voltage is at least 640 mV. In some embodiments, the open circuit voltage is at least 650 mV. In some embodiments, the open circuit voltage is at least 660 mV. In some embodiments, the open circuit voltage is at least 670, mV. In some embodiments, the open circuit voltage is at least 680mV In some embodiments, the open circuit voltage is at least 690 mV

[132] Physical parameters described herein relating to photovoltaic cell performance are determined by measurements at standard test conditions used in the art to evaluate photovoltaic cells. Standard test conditions include solar irradiance of 1,000 W/m ² , solar reference spectrum at AM (air mass) of 1.5 and a cell temperature 25 °C.

[133] In some embodiments, a ratio of back side short circuit current to front side short circuit current is at least 0.75. In some embodiments, the ratio of back side short circuit current to front side short circuit current is at least 0.8. In some embodiments, the ratio of back side short circuit current to front side short circuit current is at least 0.85. In some embodiments, the ratio of back side short circuit current to front side short circuit current is at least 0.9. [134] Herein, the phrase "front side short circuit current" refers to short circuit current (as described herein) of the photovoltaic cell under conditions wherein only the front side of the cell is exposed to illumination (e.g., wherein the back side is placed on a black opaque surface), and the phrase "back side short circuit current" refers to short circuit current (as described herein) of the photovoltaic cell under conditions wherein only the back side of the cell is exposed to illumination (e.g., wherein the front side is placed on a black opaque surface). The "front side" is defined as whichever side is characterized by the higher efficiency and the "back side" is defined as whichever side is characterized by the lower efficiency (determined as described herein).

[135] Short circuit current (Isc) may be determined, for example, by measuring the current produced by the photovoltaic cell at short circuit (i.e., voltage = 0) using standard techniques of the art.

[136] As the back side is (by definition) less efficient than the front side, a ratio of back side short circuit current to front side short circuit current is typically less than 1, optionally less than 0.95.

[137] Without being bound by an particular theory, it is believed that a relatively high ratio of back side short circuit current to front side short circuit current (e.g., as described herein) is associated with a superior rear side design (e.g., the p ⁺ layer in a p ⁺ -p-n ⁺ structure), characterized by reduction and even elimination of over-doping, and/or low effective back side recombination. It is further believed that values of other parameters described herein, such as relatively high front side efficiency, may also be improved by a superior rear side design.

[138] According to another aspect of embodiments of the invention, there is provided a photovoltaic module comprising a plurality of any of the photovoltaic cells described herein, the photovoltaic cells being interconnected to one another.

[139] As used herein, the phrase “photovoltaic module” describes a module comprising an array of photovoltaic cells, which are interconnected in series and/or in parallel. Connection of the cells in series creates a higher voltage. Connection of the cells in parallel results in a higher current. Thus, a skilled artisan can connect the cells in a manner which will provide a desired voltage and current.

[140] The module may optionally further combine additional elements such as a sheet of glass or transparent plastic back sheet to protect the photovoltaic cell from the environment without blocking light from reaching the photovoltaic cell.

[141] Said module may further comprise a tracking holder which orients the module in the direction of a source of light (e.g., for tracking the daily movement of the sun. [142] According to another aspect of embodiments of the present invention, there is provided a power plant comprising the photovoltaic modules described herein. The power plant optionally comprises a plurality of photovoltaic modules positioned so as to maximize their exposure to sunlight.

[143] It is to be appreciated that an optimal position and orientation of a photovoltaic module including the bifacial photovoltaic cells described herein may be different than an optimal position of an array of monofacial photovoltaic cells.

[144] According to another aspect of embodiments of the present invention, there is provided an electric device comprising a photovoltaic cell according to any of the respective embodiments described herein. The electric device may be configured such that both sides of the bifacial photovoltaic cell are exposed to light (e.g., being at a surface of the device). In some embodiments, the photovoltaic cells are a power source for the electric device.

[145] Exemplary applications of the photovoltaic cells and/or photovoltaic modules described herein include, but are not limited to, a home power source, a hot water heater, a pocket computer, a notebook computer, a portable charging dock, a cellular phone, a pager, a PDA, a digital camera, a smoke detector, a GPS device, a toy, a computer peripheral device, a satellite, a space craft, a portable electric appliance (e.g., a portable TV, a portable lighting device), and a cordless electric appliance (e.g., a cordless vacuum cleaner, a cordless drill and a cordless saw).

[146] According to another aspect of embodiments of the present invention, there is provided a detector of electromagnetic radiation, the detector comprising any photovoltaic cell described herein, wherein the electromagnetic radiation is selected from the group consisting of ultraviolet, visible and infrared radiation. The detector may be used, for example, in order to detect the radiation (e.g., as an infrared detector) and/or to measure the amount of radiation (e.g., in spectrophotometry).

[147] It is expected that during the life of a patent maturing from this application many relevant doping techniques will be developed and the scope of the term "doping" are is intended to include all such new technologies a priori.

[148] As used herein the term“about” refers to ± 10 %.

[149] The terms "comprises", "comprising", "includes", "including",“having” and their conjugates mean "including but not limited to".

[150] The term“consisting of’ means“including and limited to”.

[151] The term "consisting essentially of' means that the composition, method or structure may include additional ingredients, steps and/or parts, but only if the additional ingredients, steps and/or parts do not materially alter the basic and novel characteristics of the claimed composition, method or structure.

[152] As used herein, the singular form "a", "an" and "the" include plural references unless the context clearly dictates otherwise. For example, the term "a compound" or "at least one compound" may include a plurality of compounds, including mixtures thereof.

[153] Throughout this application, various embodiments of this invention may be presented in a range format. It should be understood that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the invention. Accordingly, the description of a range should be considered to have specifically disclosed all the possible subranges as well as individual numerical values within that range. For example, description of a range such as from 1 to 6 should be considered to have specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6 etc., as well as individual numbers within that range, for example, 1, 2, 3, 4, 5, and 6. This applies regardless of the breadth of the range.

[154] Whenever a numerical range is indicated herein, it is meant to include any cited numeral (fractional or integral) within the indicated range. The phrases “ranging/ranges between” a first indicate number and a second indicate number and“ranging/ranges from” a first indicate number“to” a second indicate number are used herein interchangeably and are meant to include the first and second indicated numbers and all the fractional and integral numerals there between.

[155] It is appreciated that certain features of the invention, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub-combination or as suitable in any other described embodiment of the invention. Certain features described in the context of various embodiments are not to be considered essential features of those embodiments, unless the embodiment is inoperative without those elements.

[156] Various embodiments and aspects of the present invention as delineated hereinabove and as claimed in the claims section below find experimental support in the following examples.

[157] Although the invention has been described in conjunction with specific embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and broad scope of the appended claims.

[158] It will be appreciated that the embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art.

EXAMPLES

Reference is now made to the following example, which together with the above descriptions illustrate some embodiments of the invention in a non-limiting fashion.

EXAMPLE 1

Cell structures were prepared as per the fabrication process described in Fig. 1.

Starting material: p-type monocrystalline Czochralski silicon with resistivity in the range 3-4 Ohm.cm; pseudo-square wafers with size 6”X6” and starting thickness 180 microns.

Boron deposition was performed in BBr3 atmosphere in quartz tube furnace, (no. 103)

Boron doping was performed in POC13 atmosphere in quartz tube at temperature 1020°C (no. 106)

p ⁺ layers sheet resistance obtained were in the range 60-100 Ohm/sq.

n ⁺ layers sheet resistance obtained were about 120 Ohm/sq.

Figure 2 shows the boron doped layer profile for two runs of the process.

Implied open circuit voltage, iV _0c , was measured using Quasi Steady State Photoconductivity Decay (QSSPCD) technique. The measurement tool was WCT-120 Silicon Wafer Lifetime Tester (Sinton Consulting Inc.). Table 1 reflects the results of measurements of solar cell structures with sheet resistivity of n ⁺ -layer 120 Ohm/D and different sheet resistivity values of p ⁺ -layer. The data shown in the table, demonstrate the high recombination quality of the structures, fabricated according to described technology.

The corresponding lifetime of the bulk minority carrier lifetime, at injection level of 2.10 ¹⁵ are in the range 0.4 to 0.7 ms.

Table 1

Efficiency of the fabricated solar cells using these structures is in the range of 20.7 to 20.9 % with a bifaciality factor above 90%.

EXAMPLE 2 - Bifacial PV Cell Preparation

Cell structures were prepared as per the fabrication process described in Figure 3.

Starting material: p-type monocrystalline Czochralski silicon with resistivity in the range 3-4 Ohm.cm; pseudo-square wafers with size 6”X6” and starting thickness 180 microns.

Boron doping was performed in BBr3 atmosphere in quartz tube at temperature 1020°C.

p ⁺ layers sheet resistance obtained were in the range 100-110 Ohm/sq.

n ⁺ layers sheet resistance obtained were about 120 Ohm/sq.

Implied open circuit voltage, iV _0c , was measured using Quasi Steady State Photoconductivity Decay (QSSPCD) technique. The measurement tool was WCT-120 Silicon Wafer Lifetime Tester (Sinton Consulting Inc.). Table 2 reflects the results of measurements of solar cell structures with sheet resistivity of n ⁺ -layer 120 Ohm/D. The data shown in the table, demonstrate the high recombination quality of the structures, fabricated according to described technology.

The corresponding lifetime of the bulk minority carrier lifetime, at injection level of 2.10 ¹⁵ cm ³ are in the range 450 to 780 ps.

Table 2

Referring to Figures 4a-d, IV curve measurement results for several cells are shown.