|1.||A fast bit blitter circuit for shifting the location of an image as it is transferred from a first plurality of bytes in memory to a second plurality of bytes in memory, said bytes having a particular number of bits, said circuit comprising: memory output means for serially reading bytes which store said image in said memory; a register for temporarily storing bytes previously read from said memory during a prior cycle, said register having said particular number of bit positions; a multiplexer bank having a number of multiplexers equal to said particular number of bits, each multiplexer being able to independently gate for each bit position from said memory output means and said register; a barrel shifter, said barrel shifter having said particular number of bits; and a multiplexer selector for selectively gating bits from said memory output means and from said register through said multiplexer bank to said barrel shifter; whereby said image is shifted as it passes through said register, multiplexer and barrel shifter.|
|2.||A fast bit blitter system for shifting the location of an image as it is transferred from a first plurality of bytes in memory to a second plurality of bytes in memory, said bytes having a particular number of bits, said system comprising: reading means for reading bytes from said memory and for temporarily storing the last read of said bytes; a barrel shifter having as many bit positions as said bytes; and multiplexer means for selectively gating bits from bytes that are read from said memory and bytes that are temporarily stored to said barrel shifter; whereby said image can be selectively shifted by a desired number of bits.|
|3.||The system recited in claim 2 wherein said means for temporarily storing the last read of said bytes is a temporary register which is one byte wide.|
|4.||In a system which stores images in a memory, said images being stored utilizing a plurality of bytes each of which has a plurality of bits, a subsystem for shifting an image across a byte boundary comprising: an input register and a temporary storage register; means for transferring data from said memory to said input register, and then to said temporary storage register; an end around shift register; and a multiplexer for gating selected bits from said temporary storage register and said input register to said end around shifter; whereby data can be shifted across a byte boundary by gating selected bits from said two registers to said shifter and by then shifting said selected bits a selected amount.|
|5.||The system recited in claim 4 wherein said end around shifter is one byte wide.|
|6.||The system recited in claim 4 wherein said temporary storage register is one byte wide.|
|7.||The system recited in claim 1 including means for providing a control signal to said barrel shifter, and means for generating the two's complement of said control signal.|
|8.||The system recited in claim 2 wherein said multiplexer means has as many bit positions as said particular number of bits.|
|9.||The system recited in claim 2 wherein said means for temporarily storing has as many bit positions as said particular number of bits.|
|10.||The system recited in claim 2 wherein data is gated from said multiplexer means to said barrel shifter.|
|11.||The system recited in claim 2 wherein data is gated from said barrel shifter to said multiplexer means.|
|12.||A fast bit blitter circuit for shifting the location of an image as it is transferred from a first plurality of bytes in memory to a second plurality of bytes in memory, said bytes having a particular number of bits, said circuit comprising in combination: a barrel shifter, said barrel shifter having said particular number of bits; memory output means for serially transferring bytes from said memory to said barrel shifter; a temporary storage register for temporarily storing said bytes from the output of said barrel shifter, said register having said particular number of bit positions; a multiplexer bank, said multiplexer bank having said particular number of bits; and a multiplexer selector for selectively gating bits from said barrel shifter and from said temporary storage register; whereby said image is shifted as it passes through said register, multiplexer and barrel shifter.|
FIELD OF THE INVENTION
The present invention relates to digital computers and more particularly to a system and method for shifting data across byte boundaries.
BACKGROUND AND PRIOR ART
There are many commercially available text books that explain the general operation of displays for personal computers. Two such books are "Inside the IBM PC" by Peter Norton, published by Prentice Hall Press, 1986, and "Programmer's Guide to PC and PS/2 Video
Systems" by Richard Wilton, Microsoft Press, 1988. These books describe the general operation of video displays in personal computers.
As explained in the above, computers generally store video data in multibit bytes. For example, many computers use eight bit bytes. Each bit in a byte can represent the "on" or "off" status of one pixel on the display. Thus an eight bit byte can represent the "on" or "off" status of eight pixels on the display. One way to display alpha-numeric characters in such systems is to mandate that each character will not cross a byte boundary. Thus each character or letter fits within a block which is for example, eight bits wide and several lines high. In such a system, wide characters and narrow characters must fit within the same size box.
More sophisticated systems require that characters cross byte boundaries. In these systems a character can be positioned starting at any bit position across the screen. Circuitry generally known as "Bit
Blitter" circuitry is provided to move characters or other images across byte boundaries.
Existing bit blitters generally utilize a shift register which is twice as wide as the main data path. For example if the system includes eight bit data words, a 16 bit shift register is used. Figure 1A shows an example of a prior art bit blitter circuit. In the circuit shown in Figure 1A an image is shown as going from a location in memory bank Ml-1 to a shifted position in a memory bank M2-1. In many practical systems, memory bank Ml-1 and memory bank M2-1 in fact would be the same memory; however, they are shown separate in Figure 1A for ease of explanation.
In the circuit shown in Figure 1A data from the image in memory bank Ml-1 goes through the memory register MR1-1 into two registers Rl-1 and R2-1. Adjacent bytes from memory bank Ml-1 are placed in registers Rl-1 and R2-1 and then both bytes from registers Rl-1 and R2-1 are transferred to shift register Sl-1. The data is shifted the desired number of positions and then gated out of the eight high order positions of the shift register to memory register MR2-1. As shown in Figure 1A the positions of the characters "L" and "T" are shifted by four bit positions as they move from memory bank Ml-1 to memory bank M2-1. In memory bank M2-1 each of the characters "L" and "T" crosses a byte boundary. Circuitry which is not shown is usually provided to transfer data between registers Rl-1 and R2-1 so that a particular byte of data only need be read out of memory Ml-1 once.
The operations which occur as byte 2, byte 3, and byte 4 are shifted are shown in Figure IB. The special initialization operations that occur with byte 1 are not shown since they are not relevant to the present invention. During the steps designated Step One, Step
Two and Step Three, the contents of each of the Registers Rl-1, R2-1, and MR2-1 is shown. Furthermore the contents
of shift register Sl-1 are shown in each step both before and after the shift operation. The data in registers Rl- 1 and R2-1 coincides with the data in memory bank Ml-1, while the data in register MR2-1 coincides with the data in memory M2-1. Figure IB also shows the data in the shift register SI before and after the shift operation.
An example of a commercially available Bit Blitter is a circuit marketed by National Semiconductor Corporation and designated the "DP8511 BITBLT Processing Unit". As shown in the specification sheet published by National Semiconductor Corporation for the DP8511 circuit it is designed to handle 8 bit bytes and it includes a sixteen bit shift register.
Other prior art bit blitters are implemented in software. Bit blitters implemented in software are inherently slower than bit blitters implemented in hardware.
SUMMARY OF THE INVENTION The present invention provides a fast bit blitter method and circuit which requires less logic than prior art bit blitter circuits.
A circuit built in accordance with the present invention includes four main components each of which has only as many bit positions as do the data bytes that are being shifted. The four main components are a storage register, a multiplexer bank, a multiplexer selector and a barrel shifter. As data words are serially read out of memory, they are temporarily stored in the register. The multiplexer gates selected bits from the word stored in the register, together with selected bits from the next word that appears on the data bus to the barrel shifter. The barrel shifter does the appropriate shifting. The shifter can be located either before or after the multiplexer in the data path.
The time required to shift an image using the present invention is approximately the same as that
required with the prior art, however, substantially less hardware is required.
DESCRIPTION OF THE DRAWINGS Figure 1A shows a prior art circuit.
Figure IB is a table showing how the circuit in Figure 1A moves specific bits.
Figure 2A shows a logical diagram of a preferred embodiment of the invention. Figure 2B is a table showing how the circuit in
Figure 2A moves specific bits.
Figure 3 is a circuit diagram showing the details of how a bank of multiplexers are controlled by a selector. Figure 4 is a circuit diagram of a single multiplexer stage.
Figure 5 is a circuit diagram of an alternate embodiment of the invention.
A preferred embodiment of the present invention is shown in Figure 2A. The embodiment shown in Figure 2A includes an input memory Ml, an output memory M2, memory registers MR1 and MR2, a temporary storage register R, a multiplexer MX, a barrel shifter S, a selector circuit SE, and a two's complement circuit T.
For ease in explanation two memory banks Ml and M2 are shown in Figure 2A. Memory bank Ml contains an original image of the letters "L" and "T" and memory bank M2 contains a shifted image of the letters "L" and "T". In Figure 2A, the memory Ml and M2 are shown as having six rows, each row with thirteen bytes, and each byte with eight bits. The bit positions in the memories Ml and M2 are shown by the dashed lines. It should be understood that most actual computer memories will be much larger than the memories as shown herein; however, the size of the memory is not relevant to the present
invention and memories of the size shown are sufficient to explain the present invention. It should be noted that in the shifted image in memory bank M2, the letters "L" and "T" cross byte boundaries. As explained, in many practical applications, both the original image and the shifted image would be in the same memory bank; however, whether the two images are stored in the same or in different memory banks is not relevant to the present invention. The situation where one desires to place the shifted image not only in the same memory bank as the initial image, but in exactly the same location in memory as the location of the initial image will be discussed later.
The bytes of data are supplied from memory Ml serially via a memory register MR1 and the shifted data bytes are serially placed in memory M2 via a memory register MR2. These memory "read out" and "read in" operations are conventional.
In the embodiment shown in Figure 2A, each byte of data has eight bits. In Figure 2A the bytes and bits are labeled across the top of memory Ml and the rows in the memory Ml are labeled along the left hand side of the memor .
The circuit shown in Figure 2A has a register R, a bank of multiplexers MX and a shifter S, each eight bits wide. This contrasts to prior art systems, such as shown in Figure 1, where the shifter is sixteen bits wide. The multiplexer MX is controlled by a selector SE, and barrel shifter S has a two's complement control circuit T.
The barrel shifter S always shifts to the right. A left shift is accomplished by shifting right an appropriate number of positions. For example, a left shift of 2 is achieved by shifting to the right 6 positions. This is a conventional technique.
Selector SE receives three binary signals SO, SI and S2 which indicate the amount of shift desired, and
a direction signal that indicates the direction of the shift. Selector SE decodes the signals on lines SO, SI, and S2 into seven control signals for the bank of multiplexers MX. Two's complement circuit T receives the three binary signals SO, SI and S2 and a direction signal. Circuit T performs the following functions:
(a) passes signals SO, SI and S2 directly to shifter S when a right shift is being performed,
(b) generates a two's complement of the signals on lines SO, SI and S2 and passes the complemented signals to shifter S when a left shift is desired. The manner in which a barrel shifter designed to do a right shift will perform a left shift when given two's complement input signals is well known.
The details of the bank of multiplexers MX and the manner in which the output of selector SE controls the multiplexer are shown in Figure 3. The selector SE generates signals on lines LI to L8 in response to the signals on lines SO, SI and S2. Signals on lines LI to L8 in turn control multiplexers MXl to MX8, each of which either gates a bit from byte Wl or W2 to the output W3. The signals generated by selector SE in response to signals SO, SI and S2 are shown in the following tables:
For a Riαht Shift
Shift Signals 3 desired SO > SI S2 LI L2 L3 L4 L5 L6 L7 L
0 0 0 0 0 0 0 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0 0
2 0 1 0 1 1 0 0 0 0 0 0
3 1 1 0 1 1 1 0 0 0 0 0
4 0 0 1 1 1 1 1 0 0 0 0
5 1 0 1 1 1 1 1 1 0 0 0
6 0 1 1 1 1 1 1 1 1 0 0
For a Left ShiJet
Shift Siignal: 5 desired SOι SI S2 LI L2 L3 L4 L5 L6 L7 L
0 0 0 0 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0 0 0 1
2 0 1 0 0 0 0 0 0 0 1 1
3 1 1 0 0 0 0 0 0 1 1 1
4 0 0 1 0 0 0 0 1 1 1 1
5 1 0 1 0 0 0 1 1 1 1 1
6 0 1 1 0 0 1 1 1 1 1 1
7 1 1 1 0 1 1 1 1 1 1 1
The signals LI to L8 control the multiplexers MXl to MX8 to generate the amount of shift desired as shown above.
Importantly the present invention does not add any additional delay into the operation of the circuit even though it only requires a shift register which is one byte wide (in contrast to the prior hardware technique art,which requires a shift register which is two bytes wide) . Thus, the present invention requires less circuitry than does the prior art, yet does not increase the time required to operate on the data.
The manner in which the entire circuit operates can be summarized as follows: The input data from memory register MRl is sent to an end around rotator which consists primarily of register of MRl, temporary register R, multiplexer MX, and barrel shifter S. Every byte which comes out of register MRl is thus combined with some bits of the previous byte and then written to the destination MR2. Only one read cycle is required regardless of the shift direction and the shift amount. The amount of hardware required, and the amount of delay in the circuit can be defined by considering a one bit multiplexer such as that shown in Figure 4. The one bit multiplexer shown in Figure 4 has two AND gates 41A and 4IB, an OR gate 42, and an Inverter 43. Assume the time required for a signal to pass through the multiplexer shown in Figure 4 is one unit of delay. Furthermore, assume the hardware in the circuit shown in Figure 4 is one unit of hardware.
Thus a 16 bit (two byte) multiplexer introduces four units of delay whereas an 8 bit (one byte) multiplexer introduces three units of delay. Selector SE and multiplexer MX each introduce one unit of delay. A comparison of the delay introduced by the prior art and the delay introduced by the present invention is given by the "Table C" below. Table C also compares the amount of hardware required by the prior art to the amount of delay required by the present invention.
Prior Art Present Invention
Delay Hardware Delay Hardware
Shift Reg. 4 4x16 = 64 3 3X8 = 24
Decoder 1 8
Selector 0 8
Total 4 64 4 40
The two's complement circuitry is not included in the above comparison since it is required by both circuits. Furthermore, since the complementing operation is performed infrequently, in many practical applications, the complementing will be done under program control and no additional hardware will be provided for this function. It is herein shown as a hardware block primarily for the ease of explanation. The special operations required for handling the first byte in each row and for handling the last byte in each row are done in the same way that they are done in the prior art.
Figure 5 shows an alternate embodiment of the invention. The various components in the embodiment in Figure 5 are designated by letters followed by the number 5. The letters correspond to the letters used to designate the similar component in Figure 2A and the number indicates Figure 5.
In the embodiment in Figure 5, the shift register S-5 is located in front of both (a) the temporary storage register R-5 and (b) multiplexer MX-5. The memories Ml and M2 are not shown in Figure 5 since they are identical to the memory shown in Figure 2A. In the second embodiment the selector SE-5 and the two's complement circuit T-5 are identical to the corresponding components in the first embodiment.
The system shown in Figure 5 operates in substantially the same manner as the previously described system; however, the function of previously given Tables A and B is reversed. With the embodiment in Figure 5, Table A gives the input signals for a "right" shift and Table B gives the input signals for a "left" shift.
The embodiment shown in Figure 5, has one advantage over the embodiment shown in Figure 2, namely, the operation associated with the first byte in a row can be handled more easily. Assume, for example, that characters are being shifted right four bit positions and assume that the first four bit positions in destination memory M2 have information stored therein which is to remain unchanged since the first bit position in memory Ml will be placed in memory position five in memory M2. The operation on the first byte proceeds as follows: the line indicating a shift of zero is activated and the first byte is read from memory M2 into register R-5. Now when the first byte is read from memory Ml, it can be combined with the byte in register R-5 in a normal manner to produce the desired result. The same final result with respect to the first byte can be obtained with the first embodiment; however, using the first embodiment additional steps of moving the data under conventional program control are required.
While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that changes in form and detail may be made therein without departing from the spirit and scope of the invention.