Title:
BIT-LINE SENSE CIRCUIT, AND MEMORY
Document Type and Number:
WIPO Patent Application WO/2022/057438
Kind Code:
A1
Abstract:
A bit-line sense circuit, and a memory. The bit-line sense circuit comprises: L storage unit groups, each of the storage unit groups comprising H bit lines, and L and H both being positive integers equal to or greater than 2; and M sense amplifier groups that are configured to write storage data into the bit lines in the storage unit groups or read the storage data from the bit lines in the storage unit groups, the M sense amplifier groups being electrically connected to the L storage unit groups, and M being an integral multiple of L or L being an integral multiple of M, wherein any two adjacent bit lines in the H bit lines are connected to different sense amplifier groups. By means of connecting any two adjacent bit lines to different sense amplifier groups, when a read error occurs on both of the adjacent bit lines, error data can be detected and corrected by an error detecting and correcting circuit.
Inventors:
CHI SUNGSOO (CN)
WANG JIA (CN)
WANG YING (CN)
JIN SHUYAN (CN)
ZHANG FENGQIN (CN)
WANG JIA (CN)
WANG YING (CN)
JIN SHUYAN (CN)
ZHANG FENGQIN (CN)
Application Number:
PCT/CN2021/107924
Publication Date:
March 24, 2022
Filing Date:
July 22, 2021
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C29/42
Foreign References:
| CN107430879A | 2017-12-01 | |||
| CN101136242A | 2008-03-05 | |||
| CN105931666A | 2016-09-07 | |||
| US20110085364A1 | 2011-04-14 | |||
| CN202010987632A | 2020-09-18 |
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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