Title:
BIT SEQUENCE GENERATION DEVICE AND BIT SEQUENCE GENERATION METHOD
Document Type and Number:
WIPO Patent Application WO/2011/086688
Kind Code:
A1
Abstract:
A bit sequence generation device (200) is provided with a glitch generation circuit (205) for generating glitches; a sampling circuit (220) for sampling glitch waveforms generated by the glitch generation circuit (205); and a glitch form assessment circuit (211) for generating 1-bit data representing either 1 or 0 on the basis of the glitch waveform that has been sampled by the sampling circuit (220), and generating a bit sequence comprising the generated plurality of 1-bit data. By way of the bit sequence generation device (200), it is possible to provide a PUF circuit that is capable of generating highly randomized secret information and that does not violate design rules, even for a device with a low degree of freedom for placing and routing thereof.
Inventors:
SUZUKI DAISUKE (JP)
Application Number:
PCT/JP2010/050422
Publication Date:
July 21, 2011
Filing Date:
January 15, 2010
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
SUZUKI DAISUKE (JP)
SUZUKI DAISUKE (JP)
International Classes:
H03K3/84
Foreign References:
| JP2008517365A | 2008-05-22 | |||
| JP2004280486A | 2004-10-07 | |||
| JP2002366347A | 2002-12-20 | |||
| JP2007034836A | 2007-02-08 | |||
| JP2009524998A | 2009-07-02 |
Other References:
ALTERA, DESIGN RECOMMENDATIONS FOR ALTERA DEVICES AND THE QUARTUS II DESIGN ASSISTANT, 2009
Attorney, Agent or Firm:
MIZOI, Shoji et al. (JP)
Shoji Mizoi (JP)
Shoji Mizoi (JP)
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Claims: