BIT SYNCHRONIZATION ADJUSTER

DESCRIPTION

This invention relates to a data processing system of the kind (hereinafter referred to as the kind set forth) in which there is a transmission of data of a code format having a pattern that provides a plurality of reversals 1011010 etc. from which it is desirable to maintain bit synchronization for the incoming data once initial synchronization is obtained.

This desideratum is achieved according to the present invention by a data processing system of the kind set forth wherein after a first synchronization codeword is recognized at least a part of any following synchronization codeword is sampled at least twice per bit and compared with the known structure of the bits of known synchronization codeword to enable the bit structure of best fit with the known bit structure to be accepted by the system to derive the best sample instant of the transmission of said data.

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The best fit may conveniently be a running total or summation of least errors when compared with the structure.

In a preferred embodiment the codewords are sampled not twice but three times of which one time is both early and late of the other times and comparison is performed with the known structure of the synchronization codeword. -

Ideally the said one time is taken substantially at the position corresponding to the optimum sampling time obtained from the previous synchronization.

One satisfactory analysis of a 32 ^" bit synchronization codeword, for example, is to take three samples, of which the inner is both early and late of the two other samples by say l/8th of a bit width. Other spacings than l/Sth may be used to advantage but owing to drift error it should not come too close to the value of the said error. For example where the drift error is about l/l3th of a bit width, the sample spacing should exceed that value.

The invention will be more fully understood from the following description given by way of example only with reference to the figures of the accompanying drawing in which Figure 1.shows seven bits of a 2 bit synchronization codeword. Figure 2 is a functional block diagram of one bit synchronization adjuster

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of the invention and Figure s a flow diagram of operations to be performed by the memory and microprocessor of Figure 2.

The substantially centrally placed sample is conveniently called the inner sample (l) and the sample early of I (E) and the sample late of I (L) . Error computation is given with relation to Figure 1 of the drawing and this is compared with the known bit structure of the synchronization codeword which is shown as K. It is readily seen from the figure that the received synchronization codeword R has blemishes due to noise and is sampled three times at I.E. and L where I is substantially centrally placed of the bit width 3,- the distances between I and Ξ and I and L beins -: in each case l/S 3,'.It..

The error of the sampled structure from the known structure K is taken to be unity e.. ^" Where the error is non-existent and the structure correct as in the error is zero, eo.

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-5-

The following table is then readily constructed:

B1 B2 B2 B4 B5 B6 B6 Total Errors

E e e o o ^e 1 ^e ι e e 3 o ^e 1 o

I e e e 3 ^e 1 o o ^e ι e o ^β 1 o

L e e e 2 ^e o ^e o ^e 1 o o ^e 1 o

Clearly the sample or version at L has the least errors in comparison with the bit structure of and thus L is the best fit and gives the optimum sampling instant and is subsequently accepted for use in the system.

The circuitry of one data processing system operates as follows: During the reception of the codeword a number of separate sampling instants are used and repeated in the same relationship for each bit of the codeword. In this way a number of versions of the received codeword may be built-up one corresponding to each .of the sampling instants used. The version of the codeword having the least errors and giving the best fit with the known structure of the code- - word will then

be accepted by the system to indicate the best sampling instant. This instant and its repeat once every bit is then used to sample the incoming data.

One specific embodiment of this function utilizes a microprocessor based system (Figure 2). The flow chart associated with this function is Figure 3 and a listing is attached in the appendix A.

In Figure 2 a radio pager comprises a receiver board 10 having an aerial 11 by which a signal enters a radio frequency amplifier 12 a 1st mixer 13 coupled to a 1st oscillator l to a 1st intermediate frequency amplifier 15," from which it passes inter alia via a 2nd mixer 16 to an audio limiter 1~ connected to the input/output of the microprocessor IS (>ΪC l ⁱ i6S05E2) which is related to the memory of ROM (MCM65516) 19. The MPϋ will receive from the ROM a logical sequence set out in the flow sheet of Figure 2 wherein:-

101 is input first bit initialize error registers

102 is retain LS3 invert initialize bit count

103 is advance timer l/δth of a bit

104 is initialize X for three samples

105 is wait

106 i s input data

107 i s EOR wi th exnected bit

10S is add result to error register

109 is three samples in?

110 is thirty two bits in?

111 is initialize for early (E) sample selection

112 is does late (L) sample have less errors?

113 is SET accumulator and index register for late (L) timing

11 is does late (L) sample have same errors?

115 is set accumulator and index register for inner timing (I) llβ is does inner (l) sample have less errors? 117 is put next expected bit into V2SVB IIS is reset dead man timer

119 is minimum error count less than V2ER0R?

120 is adjust timer according to accumulator contents

121 is set for BF AG

122 is RETURN

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