TECHNICAL FIELD OF THE INVENTION

The invention relates to body biasing in system-on-chip (SoC) integrated circuits having one or more power domains.

BACKGROUND ART

The integ ration density of I nteg rated Circu its (ICs) has approximately doubled every 18 months. At current rates of progress, advanced IC manufacturing will enable over 1 billion transistors to be integrated on a single silicon chip. Such chips are at the heart of a new generation of devices that are changing our daily lives fundamentally. Power consumption of conventional electronic devices is a major concern because such dense devices produce a significant amount of heat, imposing constraints on circuit performance and IC packaging. The case for portable devices is clear, as an important goal is to maximize battery life. Designing ICs for low power is therefore a key practical challenge.

One particular challenge in current integrated circuit design is that of how to deal with an increasing sensitivity to process parameter variations as the feature sizes on an IC become smaller. This is motivated by the fact that nanometre-scale IC manufacturing technologies (particularly at the sub-100 nm scale) tend to exhibit a larger dependence on parametric and systematic yield losses. Other factors including current leakage due to direct tunneling and gate-induced drain leakage also become more significant at smaller scales. Transistor orientation, stepper field dependence, and intra-die electrical parameter variations including those relating to threshold voltage and via resistance pose potentially serious problems for designs based on low-voltages and low-power requirements. Such variations can result in, for example, clock skews, excessive leakage current, out of specification critical-path delays, loss of stability of flip flops and memory cells. An open design challenge is how to implement built-in "process regulators" to help a SoC (system-on-chip) deal with the impact of process variability during normal operation. Known examples of process regulators include control systems for, amongst other things, minimization of threshold voltage mismatch, leakage current, and clock skew. In recent years the application of adaptive circuit techniques to control power supply (V _DD ) and threshold voltage (V _th ) has gained increased attention. Chip demonstrators with V _DD and V _t h scaling capabilities have been reported [References 1 -3]. Other reported uses of V _DD and V _t h scaling, besides power management in processors, are in testing [4], product binning [5], and yield tuning [6].

Control of threshold voltage of PMOS and NMOS transistors can be achieved through the application of transistor body-biasing schemes [7]. Such schemes make use of biasing the transistor body node to a desired potential, instead of shorting it to V _DD (for PMOS) or ground (for NMOS). We will now illustrate the conventions used by considering the case of an NMOS transistor. For such a device, the threshold voltage is increased when the source-body voltage is biased to be positive. This is referred to as Reverse Body Biasing (RBB). Conversely, the device threshold voltage is reduced when the source-body voltage is biased to be negative. This is referred to as Forward Body Biasing (FBB). Body biasing can be applied, altered and removed while the IC is operational. Power leakage can be reduced when using RBB, through device U tuning, at the expense of circuit speed. Body biasing can also be used to improve the run-time performance of the IC when using FBB, through device I _0n tuning, although at the expense of leakage power.

There exist two basic control approaches to perform body biasing, namely: i) Dynamic Body Biasing (DBB); and ii) Adaptive Body Biasing (ABB). Dynamic body biasing is an open-loop control technique, in which a pre-defined operation profile is set for the circuit. Examples of DBB include the use of low-leakage states with RBB, or speed enhancement with FBB. Reference values for DBB can be defined when the IC is designed, or can be obtained from chip calibration during production testing. Adaptive body biasing, on the other hand, is a closed-loop control technique for which circuit parameters (such as speed) are monitored, compared and controlled against desired values in real-time. This control can be achieved while considering changes in workload to determine and to set optimum body biasing conditions during chip operation. This can result in ABB being a more flexible and efficient control technique than DBB, although a more complex control system is required.

Nowadays, integrated circuits tend to be equipped with multiple power domains for power management reasons. Each power domain can operate from its own power supply voltage, which may be static or adaptive. Body biasing schemes will tend to be more effective when a dedicated bias is applied for each power domain, because this allows for leakage power versus performance optimisation for each domain. Further optimization may also be possible by applying dedicated bias voltages on a sub-power domain level. Quantitative pointers for the expected benefits of using joint V _DD and V _t h control through a combination of Adaptive Voltage Scaling (AVS) and ABB for state-of-the-art chip technologies are presented in [7], which shows that substantial reductions in leakage can be achieved through such a combination.

In a scenario where body biasing is to be performed for each power domain in a multiple power domain IC, a body bias generator will be a key circuit component. A modular solution would be preferred, from a component re-use and chip architectural perspective, especially when applied to multiple power domain SoCs. A scalable solution is also preferred in order to match the body bias generator for a given system size. Furthermore, the body bias generator must be tolerant to an environment having an adaptive power supply, and should have a low, or preferably negligible, power consumption to be applicable in low-power ICS. OBJECT OF INVENTION

It is an object of the invention to address one or more of the above problems.

SUMMARY OF INVENTION

According to a first aspect of the invention there is provided a body bias generator circuit operable to provide a body bias voltage to a core of an integrated circuit, the body bias generator circuit comprising: an input for receiving a digital bias code; a digital to analog converter operable to provide an analog signal from the digital bias code; a voltage buffer configured to receive the analog signal from the digital to analog converter and to supply a body bias voltage to the core of an integrated circuit connected to an output of the voltage buffer.

The voltage buffer preferably comprises an operational amplifier. The body bias generator circuit may comprise a voltage scaling circuit connected between a circuit voltage supply line and a core voltage supply line, the voltage scaling circuit configured to provide the core voltage supply scaled relative to the circuit voltage supply. The voltage scaling circuit optionally comprises a variable resistance between the circuit voltage supply and the core voltage supply.

The digital to analog converter preferably comprises a resistor network connected to the core voltage supply line and configured to provide the analog signal to the voltage buffer dependent on the digital bias code. The circuit may thereby be configured to supply a bias voltage relative to the core voltage supply.

The body bias generator circuit optionally comprises a feedback loop connecting the core to a power mode controller, the feedback loop configured to provide a measure of core performance to the power mode controller, the power mode controller adapted to adjust the digital bias code to alter the body bias voltage according to the measure of core performance. The power mode controller may be adapted to operate the circuit in a mode in which the circuit voltage supply is provided to the core as the body bias voltage. The power mode controller may additionally or alternatively be adapted to operate the circuit in a mode in which the core voltage supply is provided to the core as the body bias voltage.

A reference voltage supply circuit is optionally provided, connected to an input of the digital to analog converter and configured to supply an reference current through the resistor network in proportion to a reference voltage. The body bias generator circuit may be adapted to switch between applying the reference current from the reference voltage supply circuit and from an external reference voltage supply.

One or more expansion circuits may be connected to the body bias generator circuit, the extension circuits configured to extend the current driving capability of the body bias generator circuit.

The body bias generator and extension circuits may be incorporated into an integrated circuit, each circuit being provided in a modular form, connections between the generator and extension circuits being provided along adjoining edges of the circuit modules. In accordance with a second aspect of the invention there is provided a body bias generator circuit operable to provide body bias voltages to n-well and p-wells of a core of an integrated circuit, the body bias generator circuit comprising: a first input for receiving a digital n-well bias code; - a first digital to analog converter operable to provide an analog signal from the first digital bias code; a first voltage buffer configured to receive the analog signal from the first digital to analog converter and to supply a body bias voltage to an n- well of the core of the integrated circuit; - a second input for receiving a digital p-well bias code; a second digital to analog converter operable to provide an analog signal from the second digital bias code; and a second voltage buffer configured to receive the analog signal from the second digital to analog converter and to supply a body bias voltage to a p-well of the core of the integrated circuit.

In accordance with a third aspect of the invention there is provided a method of applying a body bias voltage to a core of an integrated circuit, the method comprising: providing an digital bias code to an input of a digital to analog converter; converting the digital bias code by the digital to analog converter to provide an analog signal to a voltage buffer; supplying a body bias voltage to the core of an integrated circuit connected to an output of the voltage buffer.

The invention allows for a body bias generator having differentiating properties as compared with prior art solutions. Advantages of the invention include one or more of the following: i) Body bias generation can be fully integrated and digitally- controlled, resulting in there being no need for voltage supplies other than the nominal V _DD supply. This lowers overall system costs, since no additional external components or package pins are needed. ii) A low-power design with integrated power-management features, such as programmable body biasing for to allow for performance-power trade-off, a bypass mode for applying nominal biasing, source-biasing for reduced-leakage operation, and a power-down mode for power-gated circuits; iii) Compatible with any V _DD scaling approach, allowing the invention to be operational in static or dynamically changing V _DD environments; iv) Performance boosting or performance compensation, allowing for FBB for higher performance operation, or for parametric yield enhancement; and v) Aspects of the invention allow for a modular and scalable solution to on-chip body bias control. BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will now be described by way of example, with reference to the appended drawings in which: figure 1 is a schematic block diagram of an on-chip body bias generator circuit; figure 2a is a schematic representation of a p-well embodiment of a DAC buffer circuit; figure 2b is a schematic representation of a n-well embodiment of a DAC buffer circuit; figure 3 is a schematic block diagram of an open-loop body bias control scheme; figure 4 is a flow chart for a method of performance compensation; figure 5 is a schematic block diagram of a closed-loop body bias control scheme; figure 6 is a schematic circuit diagram of an adaptive voltage scaling scheme using transistor switches; figure 7 is a schematic diagram of connections to and from a body bias generator circuit; figure 8 is a circuit diagram of n-well and p-well body bias generator circuits connected to an adaptive voltage scaling system; figure 9 is an alternative circuit diagram of the n-well and p-well body bias generator circuits of figure 8; figure 10 is a further alternative circuit diagram of the n-well and p- well body bias generator circuits of figures 8 and 9; figure 11 is an expanded circuit diagram of the n-well and p-well body bias generator circuits of figure 10; figure 12 is a further expanded circuit diagram of the n-well and p- well body bias generator circuits of figure 11 ; figure 13 is a circuit diagram illustrating an arrangement of internal and external reference sources; figure 14 is a block diagram of a body bias generator circuit as connected to a reference circuit and a digital island; figure 15 is a diagram of a resistor network for an RDAC; figures 16a-c illustrate in block form connections between a base unit and extension units of a body bias generator circuit; figure 17 illustrates connections to and from a base unit of a body bias generator circuit; and figure 18 illustrates connections to and from an extension unit of a body bias generator circuit; and figure 19 illustrates schematically a relationship between a number of body bias generator modular units and a load capacitance.

Figure 1 shows a conceptual block diagram of a proposed body bias generator circuit according to the invention. The circuit 100 comprises three basic blocks: a reference current generator 110, a digital- to-analog (DAC) buffer stage 120, and a power mode controller 130. The DAC buffer stage 120 comprises an input stage 121 , a gain stage 122 and an output stage 123. The DAC buffer stage 120 is supplied with full supply voltages V _D D, V _S S as well as core supply voltages V _S sc, V _D DC-

A power management unit or power management software (not shown) may be used to provide inputs to the power mode controller 130, the inputs including a mode of operation input 140, and a digital body bias code 150 for instructing the circuit 100 to output a required level of bias voltage. Optionally, an additional body bias reference code 160 can be provided to the power mode controller 130, which may be required for compensation of process-dependent performance spreads. An additional 'bypass' mode input 170 may be provided to cause the circuit 100 to generate nominal well biasing outputs. A description of the applied methodology is provided below.

The body bias generator circuit 100 may support several operation modes, including: i) an 'active' mode, in which a chosen body bias voltage is applied to the core, the bias voltage being set by an applied body bias code 150; ii) a 'power-down' mode, in which a well biasing output 180 from the DAC buffer circuit 120 is connected to the core supply voltage V _S sc 131 (for p-well biasing), or to the core supply voltage V _DDC 132 (for n-well biasing); and iii) a 'bypass' mode, in which the well biasing output 180 is connected to the full voltage supply level V _S s 133 (for p-well biasing) or to V _DD 134 (for n-well biasing). For CMOS 45nm technology, the full voltage supply V _DD -V _SS is nominally 1 .1V, and for CMOS 65nm the full voltage supply is nominally 1.2V. The bypass mode can be used for example to perform circuit operation with nominal well biasing conditions, or for setting a source-biasing low-leakage operation when the core operates at a reduced supply.

The DAC buffer circuit 120 is a special analog circuit design in the sense that it can support a power-down operation, its output is referred to the core supply voltage during active mode, and it can be dynamically controlled from the digital power mode controller 130 to set a desired body bias voltage. The DAC buffer output stage 123 is preferably scalable to support driving of different size circuits within a given slew rate budget, as described below with reference to figures 16a-c to 19.

One preferred embodiment of a DAC buffer circuit 120 comprises an R-DAC, i.e. a digital to analog converter comprising a resistor network, connected to a voltage buffer in the form of a rail-to-rail switchable operational amplifier to allow for a low-impedance output. In this context, 'rail-to-rail' means that the op-amp can switch between the full voltage supply range V _DD -V _SS - Figure 2a shows a graphical overview of such a circuit 12Op configured for p-well biasing, while figure 2b shows the corresponding circuit 12On for n-well biasing. Reference numerals in figure 2a correspond to those in figure 2b, but with a suffix p in figure 2a (indicating p-well biasing) replaced with a suffix n in figure 2b (indicating n- well biasing). In figure 2a, a reference current input 23Op and a digital p-well bias code input 15Op are provided to the RDAC 21 Op. A standby input 25Op and an output enable input 26Op are provided by the power mode controller 130 (figure 1 ) to the op-amp 22Op. The standby input 25Op, when activated, disables all current sources in the circuit, while the output enable input 26Op acts to physically disconnect the op-amp output 18Op from the core p-well connection. When the output enable input 26Op is not active, the core p-well output 18Op from the op-amp 22Op is shorted to the supply voltage V _S s- In another mode, the op-amp output may instead be shorted to the core supply voltage V _S sc- The DAC buffer circuit 12Op uses two supply pairs: the RDAC 21Op is powered from the core supply voltage Vssc, while the op-amp is powered from the full supply voltage supply V _D D- Vss- The op-amp 22Op is configured as a buffer so as to provide a low- impedance output 18Op to the core. Various alternative R-DAC implementations are possible. One preferred implementation includes biasing the R-DAC 21 Op at one end using the core supply voltage Vssc, and at the other end of the R-DAC 21 Op with the reference current input 23Op, as shown in figure 2a. Such a configuration offers higher accuracy than when connecting the R-DAC between both core supply voltages Vssc V _D DC-

Figure 3 shows an implementation of the body bias generator circuit 120 (comprising the n-well and p-well versions 12On, 12Op of figure 2), incorporated into an open-loop body bias control scheme. The digital body bias codes 15On, 15Op are provided from an on-chip or off-chip controller 130, together with the Active/PowerDown operation signals 140, 170. The body bias generator circuit 120 provides a well bias voltage output 18On, 18Op to either one or both p-well 13Op and n-well 31 On of a core 320, i.e. to the body of a plurality of MOS transistors implementing a particular function in an IC module. The core 320 can be a whole digital chip, or a part thereof, but preferably consists of a single voltage domain.

The power supply of the core 320, defined by scaled voltages V _DDC , Vssc, can be statically or dynamically voltage-controlled for power management purposes, using variable resistances 33On, 33Op. The schematic circuit diagram of figure 6 illustrates an exemplary embodiment of adaptive voltage scaling using transistors as switches to implement a range of resistance values which act to scale the global supply voltages VDD VSS to the core voltage supplies V _D DC, VSSC- The full voltage supply across the circuit, i.e. V _D D-VSS, is reduced by a voltage drop ΔV, derived from a combination of the voltage drop across a first set of transistors 610 and a second set of transistors 620. With the number of switched transistors in each set being the same, the total voltage drop ΔV is equal to twice the voltage drop ΔV/2 across each set. The core voltages, i.e. those supplied to the CMOS circuit 630, being defined herein as V _DDC and V _S sc, are then given by V _DDC -ΔV/2 and V _S sc+ΔV/2.

Local controllers 640, 650 in individual islands contain registers that are connected to each of the transistor switches in the first and second sets 610, 620. Pmos transistors are connected to the V _DD line, while Nmos transistors are connected to the V _S s line. Each individual transistor switch has a specific on-resistance, and the combination of all switches together acts as the controllable resistances 33On, 33Op (figure 3) connected to each power supply line V _D D, V _S S- When more switches are activated in parallel the resulting parallel resistance of the composite switch reduces, thereby decreasing the voltage drop across it and providing more supply voltage to the digital core circuit 630. The maximum voltage drop applied using this technique is projected to be 0.30V at each of the V _DD and V _S s sides. With a global supply voltage of 1.10V (for CMOS 45nm) the resulting minimum voltage supply voltage across the core circuit will be 0.50V. When all switches are on, the voltage drop will typically be limited to only a few mV, the exact value depending on the number of transistors used.

The parasitic circuit capacitance C of the digital core circuit 630, together with some additional local supply decoupling capacitances act to reduce any switching noise on the internal digital core supply rails at nominal voltages V _D DC, V _S SC-

An example of a V _DD control solution is through use of a low dropout regulator (LDO) circuit in the V _DD and V _S s lines, as indicated in Figure 3. The body bias generator circuit 120 operates relative to the core supply voltages V _D DC, V _D DS, and therefore always provides the desired well bias independent of the supply voltage of the core. For example, considering the p-well 31 Op bias of 0.5V, the voltage at the p-well V _pwe ιι will be V _S sc + 0.5V. When VSSC is increased for voltage scaling purposes, using variable resistor 33Op, V _pW eiι is adjusted accordingly, thereby maintaining the required forward body bias.

Operation of the body bias generator circuit 120 in open-loop configuration is as follows. Instructions are provided, either by user input or by software control, to the control function to instruct the power mode controller 130 to apply a desired body bias code to the core 320. This instruction can be a one-time operation (for example during calibration or boot-up of the chip), or can be made while the core 320 is operational. A one-time operation may be used to red uce a process-dependent performance spread, for example being applied to particular ICs that exhibit a lower than expected performance compared with a nominal performance. Alternatively, body biasing may be applied on the fly to enable performance boosting by applying forward body biasing to one or both wells.

Figure 4 shows a generic example of a flow-chart for chip process- dependent performance compensation using the body bias generator circuit described herein. After starting the calibration process (step 410), the chip performance is measured (step 420) and compared against a typical or nominal performance level. If the chip meets its typical performance (step 430), the calibration is stopped (step 440). Forward body biasing (FBB) is applied or increased (step 450) if the chip does not meet typical performance (step 430), i.e. if the chip is slower than expected. Depending on the available measurement data, FBB may be applied for one or both wells. In the case where the maximum FBB is reached (e.g. 0.6V FBB), or in case a leakage target is exceeded (step 460), the calibration is stopped (step 440) and the previous FBB setting is used. Otherwise, if a repeat test of typical performance is passed (step 430), the calibration is stopped (step 440) and the current FBB setting is used.

Table 1 below illustrates an example of a high-performance profile for a core using the body biasing scheme described herein. In an active operation mode of the core, defined as a "Hyper" profile, a maximum FBB is applied to the core such that the core operates at higher performance. In 65nm CMOS, it may be possible to achieve about 20% extra performance using this technique, but at the cost of increase power losses. Since FBB also increases leakage, it is desired to have a nominal body biasing profile, for low-activity processing (under an 'energy aware' or 'performance aware' mode). FBB may also be disabled in a standby mode (e.g. a cool or cryogenic mode), for low-leakage, i.e. low power, operation.

Table 1 : Example performance profiles.

Various different approaches may be taken to implement the control function. The control function can be implemented by means of an on-chip memory or a power mode controller. Other implementations are, for example, through use of an off-chip controller implemented in a companion chip. Alternatively, it may be possible to embed an on-chip sensor circuit to measure the chip performance. In preferred embodiments, all the functionality of the body bias generator circuit is provided on-chip, which provides the advantages of allowing for a modular and self-contained system. Figure 5 shows a possible application of the body bias generator circuit 120 when used in a closed-loop body bias control scheme. In this case, the core 320 is equipped with an on-chip speed sensor circuit 510 that can measure silicon performance-sensitive variations in either NMOS or PMOS transistors, and feed back performance indications to the power mode controller 130. A special ring oscillator design can be used for this purpose, an example circuit design of such ring oscillator being provided by Reference [8] listed below, with figure 8h for a PMOS implementation and figure 8i for a NMOS implementation, although other ring oscillators not sensitive to NMOS or PMOS may be used.

The closed-loop body bias control scheme shown in figure 5 makes use of an on-chip power mode controller 130. The controller 130 compares measured silicon performance against a performance reference 530 as provided by a power management unit or software. In order to do this comparison, the controller 130 needs to have an absolute time reference, which is supplied by a low-frequency reference clock 520. The performance reference 530 also includes setting of operation profiles such as performance boosting or source-biased low-leakage operation. The latter operation may be applied when the chip is operating at a reduced voltage supply, for example at retention voltage, i.e. the lowest power supply voltage a circuit can be powered at while maintaining stored logic states. The well voltage is then applied to perform reverse body biasing (RBB) to reduce core leakage. The power mode controller 130 may also have a calibration input 550 to start the calibration process as described above with reference to figure 4, and a calibration ready output 540 to indicate when calibration is finished. Closed-loop body bias control also makes it possible to perform automatic performance setting of the core 320 against a desired performance value.

Figure 7 illustrates a block diagram of an exemplary body bias generator circuit, showing the various inputs and outputs required to operate the circuit 100. The circuit 100 is provided with both full supply voltage lines V _D D, V _S S and core supply voltages V _D DC, V _S SC- Nw_bias and Pw_bias inputs, in the form of multi-bit digital input lines, provide the digital values for the n-well and p-well bias voltage outputs V_Nwell, V_Pwell. The input lines may be in the form of 6-bit control words, i.e. providing a range of 64 discrete values (from zero to full) for the n-well and p-well bias voltages. Output lines outp_nw, outn_pw, outp_pw, outn_pw are provided for expansion of the circuit using one or more expansion blocks (described below). A reference voltage Vref, which may be generated from a resistive divider between V _DD and V _S s, i.e. proportional to the supply voltage, is provided at a further input. Enable and Mode control inputs are provided to select which one of four different modes the circuit 100 is to be operated in.

Fig u res 8 to 1 3 il l ustrate varying levels of an exem plary implementation of a body bias generator circuit according to the invention, configured to provide exemplary varying body bias voltages of between 0 and 50OmV. As shown in figure 8, the body bias voltage generators for each of the p-well and n-well bias voltages can be regarded as floating voltage sources, connected between V _S sc and the p-well connection, and between V _DDC and the n-well connection respectively.

Each body bias generator is digitally controllable, digital control being implemented using buffered D/A converters, as shown in figure 9. The DACs 910, 920 are each supplied with the scaled voltages V _D DC, V _S SC input via a digital to analog converter (e.g. a resistor network, as outlined above) connected across the full supply voltage V _D D, V _S S (these connections not shown in figure 9).

Each of the buffered D/A converters needs to be able to drive the large well capacitors, within the boundaries of the required specifications. A simple and effective solution for this is to implement this circuit as a resistor ladder DAC and a voltage buffer with a low-ohmic output, such as the circuit shown in figure 10.

Each resistor ladder DAC (or RDAC) may be a simple resistor string, for example having a total value of 300kΩ with a set of switches at suitable spacings, so as to provide the desired output voltages to each buffer 1050, 1060, the buffers being in the form of op-amps configured to supply the voltage to the n-well and p-well of the core. By supplying each RDAC with a suitable current source 1030, 1040, the required 'floating' voltage source construction shown in figure 8 is obtained.

The required current sources 1030, 1040 may be defined by use of current mirrors and a feedback circuit that derives the required reference current from an externally applied reference voltage source Vref and an internal resistor Rref. This arrangement is shown in figure 11 , in which the reference resistor Rref is matched to the DAC resistor banks RDAC1 RDAC2. The architecture of the bias body generator circuit may be further completed by adding an enable input ENB to the body bias buffer op-amps 1050, 1060 and the reference circuit 1110, as shown in figure 1 2. Additional switches 1120a-d short circuit the body bias outputs to the global supply voltage rails V _D D, V _S S or the core voltage supply rails V _D DC, Vssc, when the body bias control buffers are disabled. Two logical inputs ENB and MODE, shown in figure 12, and their logical inverses, are used to control switches 1 120a-d, i.e. switches 1 120a, 1 12Od are closed when both ENB and MODE are low, and switches 1 120b, 1 120c are closed when ENB is low and MODE is high.

The different mode settings for the body bias generator circuit of figure 12 are summarised in Table 2 below. The control input terminals 'Enable' and 'Mode' determine if the circuit is in an active or standby mode. In the active mode (i.e. when Enable is high), a selection is made between whether the circuit operates with an internal or external reference voltage, according to whether Mode is high or low. In standby mode (i.e. when Enable is low), a selection is made if the well switches connect to the global or to the core supplies.

Table 2: Body bias generator mode settings.

The reference voltage Vref for the body bias generator circuit can be selected to be either internal or external, as shown in Fig. 13. When the input MODE is high, the internal reference voltage Vref is derived from the global V _D D supply, and thus becomes proportional to this global V _D D voltage. The nominal value for Vref is 70OmV for a V _DD voltage of 1.1V. When MODE is low, an external reference voltage may be connected, e.g. a bandgap reference circuit. This external reference voltage should have a nominal voltage of 70OmV, with respect to the global V _S s-

A block diagram of a complete body bias generator circuit is shown in figure 14. A reference circuit 1410 supplies reference current supplies Irefnw, Irefpw to respective RDAC circuits 142On, 142Op. Each RDAC circuit 142On, 142Op also receives inputs from respective decoders 143On, 143Op, which receive digital Nw_bias and Pw_bias signals. The RDAC circuits 142On, 142Op supply voltage signals V_NW, V_PW to respective n-well and p-well voltage buffers 144On, 144Op, which supply body bias voltage signals Nw_out and Pw_out to the core or digital island 1450.

The reference circuit 1410 in figure 14 corresponds to the implementation shown in figure 12. The current mirrors in the circuit are preferably cascoded, in order to obtain a sufficiently high output impedance. The output reference current Irefnw, Irefpw is proportional to Vref applied and is inversely proportional to the internal reference resistor Rref. The internal reference resistor is preferably chosen to match the resistors used in the RDACs 142On, 142Op.

Each decoder 143On, 143Op is configured to convert the 6-bit words received as inputs into the 16 bit lines HSJines, VS_lines fed to each respective RDAC 142On, 142Op. The first 3 bits of each 6-bit word are converted into 8 horizontal bit-lines, and the second 3 bits are converted into vertical bit-lines. These 2x8 bit lines select the proper switch in an array of switches making up each RDAC 142On, 142Op. Each RDAC 142On, 142Op converts the 2x8 bit lines received from the respective decoders 143On , 143Op into a voltage signal for a respective voltage buffer 144On, 144Op. Each RDAC is connected to a reference current l _ref (from the reference circuit 1410) and to either V _DDC or Vssc- The voltage at l _ref is V _DDC - 50OmV or VssC + 500 mV. An exemplary resistor network for an RDAC is illustrated in figure 15.

Each voltage buffer 144On, 144Op receives the voltage output from a respective RDAC 142On, 142Op. Switches are incorporated into the buffers 144On, 144Op as described above with reference to figure 12, the switches controlled by the ENB (Enable) and MODE signals. To allow for a flexible implementation on an integrated circuit, a body bias generator circuit according to the invention may comprise two or more modular parts, comprising a base unit and one or more expansion un its. The base unit circuit module comprises all the essential components detailed above for providing the required p-well and n-well bias voltages, whereas each expansion unit circuit module allows for the bias voltages to be applied to a larger core by boosting the maximum current to be supplied by the circuit.

One particular implementation of a body bias generator is shown in figures 16a-c. A base unit 1610 may for example by itself be capable of driving n-well and p-well bias voltages for a digital island of 0.5 mm ² in 45nm CMOS technology. If a larger digital island is to be connected, the base unit 1610 may be expanded by adding one or more expansion units 1620a, 1620b. Each expansion unit 1620a, 1620b may for example be configured to extend the drive capability of the base unit 1610 in additional 0.5 mm ² units. A maximum of 8 expansion units can typically be connected to one base unit. The layout of the circuit modules is such that the modules can be simply combined and connected by abutment, as shown in figures 16b and 16c, with connections between the circuit modules provided along adjoining edges 1630, 1640. Connections for the global (or circuit) voltage supply and the core voltage supply are provided along adjoining edges of the base module and extension modules 1620a, 1620b.

Each module 1610, 1620a, 1620b is preferably surrounded by N and P diffusion guard rings, covered by a metal layer. The outer guard ring is connected to V _S s, while the inner guard ring is connected to V _DD - All other terminals have their pins at the boundary of the layout. An exemplary implementation of a base module 1610 is shown schematically in figure 17, illustrating the various connections around the perimeter of the module 1610. An exemplary implementation of an extension module 1620 is shown schematically in figure 18.

As the number of extension modules increases, the current capability of the overall circuit increases, allowing the circuit to drive cores having larger overall capacitances. Figure 19 illustrates a relationship between the number of drive units and the maximum load capacitance the circuit is able to drive. One unit, i.e. a base module alone, is capable of driving up to 500 pF. Each additional extension unit increases this by a further 1000 pF. The body bias generator circuits described herein would typically be configured to apply forward body bias (FBB) only. The circuits could be modified to apply reverse body biasing (RBB), but this would require a negative voltage supply line in addition to the V _D D and V _S s lines. Other embod iments are intentional ly with in the scope of the invention as defined by the appended claims.

The following documents are to be incorporated herein by reference:

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[8] M. Bhushan, et.al., "Ring oscillators for CMOS process tuning and variability control", In: IEEE Transactions on Semiconductor Manufacturing, Volume 19, Issue 1 , Feb. 2006 Page(s):10 - 18 [9] EP 1759460 A1 : Adaptive Power Control of Power Supply for Integrated

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[10] US 2006/0123368 A1 : Real-Time Adaptive Control for Best IC Performance.