CONTAMINANTS AND ARRESTING CRACKS DURING DIRECT-BONDING PROCESSES

RELATED APPLICATIONS

[0001] This patent application claims the benefit of priority to U.S. Non- Provisional Patent No. 16/553,879, filed August 28, 2019, and U.S. Non- Provisional Patent No. 16/553,535, filed on August 28, 2019, and U.S. Provisional Patent No. 62/724,270 to Gao et al., filed on August 29, 2018 and incorporated by reference herein in its entirety.

BACKGROUND

[0002] Fig. 1 shows conventional pitfalls that occur while forming bonds during direct-bonding processes used in microelectronics fabrication and packaging. Nonbonding areas called bonding voids or just“voids” can occur in the bonding interface between two surfaces being joined, and these voids can weaken the direct bond being formed.

[0003] Direct-bonding processes take place between two nonmetal, inorganic dielectric surfaces, or may take place between two surfaces that also have metal pads to be bonded together, for making an electrical interconnect, for example. When metal features are also present in the bonding interface, the bonding process may be called direct hybrid bonding.

[0004] The detrimental voids in the bonding interface may occur due to lack of a buffer area in the interface to make space for stray particles and other undesirable byproducts of the direct-bonding processes. With nowhere else to go, the stray particles stay between the surfaces being joined causing random voids in the bond. Some stray particles, foreign materials, and other imperfections have a tendency to create relatively large voids between the surfaces being bonded. In direct bond interconnect (DBI®) hybrid bonding processes (available from Invensas Bonding Technologies, Inc., formerly Ziptronix, Inc., an Xperi Corporation company, San Jose, CA), these concerns are magnified because the undesirable voids can occur on electrical leads that are only a few hundred nanometers or even a few tens of nanometers in width. High performance is often required of such ultrafine electrical leads. High bandwidth memory, such as HBM2 memory, for example, may demand signal speeds up to 2.4 Gbps per pin or even higher speeds, and SerDes signaling may need to pass through a bonded interface at 112 Gbps, for example.

[0005] In Fig. 1 , when undesirable voids 10 have been created in a conventional direct-bonding interface 20, a given void 10 may intervene within the footprint (cross-sectional bond area) 30 of the electrical interconnect being bonded, and the particle itself 40 may also intervene. The void 10 effectively insulates a part of the cross-sectional footprint 30 of the interconnect from carrying the electrical current it would have carried, if bonded. The voids 10 thereby cause compromised input-output (IO) connections and a marked decrease in overall assembly yield and/or reliability of the device being created.

[0006] Such voids 10 have been observed in direct-bonding of silicon wafers that have only a thin layer of native oxide. Because crystalline silicon does not have enough defect sites to capture gas contamination during an annealing step, the formation of voids results from gaseous byproducts. Similarly, when one of the surfaces being bonded is a silicon nitride, the nitride layer is impermeable to the escape of water vapor, hydrogen gas, and other reactant byproducts through diffusion, resulting in formation of the voids 10 during the annealing step. A poor- quality oxide surface that contains residual components from the oxide deposition process may also result in outgassing, and subsequent formation of voids 10 at the bonded interface. Apart from gases that are released during the annealing step, particles and other contaminants on the surfaces prior to bonding, that were not removed during the cleaning processes or that were deposited even after the cleaning processes, also lead to the formation of voids 10.

[0007] In addition, the edges of the surfaces 20 being bonded may have chipping 50, micro-fractures 60, and residue that are present from being diced or sawn along the edges. These likewise create bonding voids 10, that may weaken the bond between surfaces being joined, even when they do not interfere with electrical conduction of an interconnect.

[0008] The tendency of small particles 40 to create voids 10 during bonding is accentuated in microelectronic fabrication processes by the bonding surfaces typically being ultra-flat, after flattening processes such as chemical-mechanical planarization (CMP). Because the bonding surfaces are so flat, a small particle 40 (for example, one micron in diameter) may cause a bonding void of ten microns or larger in diameter.

SUMMARY

[0009] Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes and arresting the propagation of cracks. Example surfaces for direct-bonding are provided with predesigned recesses, sinks, traps, trenches, or cavities (hereinafter “recesses) to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined. The recesses can also prevent cracks and fissures from propagating along a surface or across a layer. Such random voids are detrimental and can compromise both bond integrity and electrical conductivity of interconnects being bonded. [0010] In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of detrimental random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process. The recess may be less than 10 nm and may be nonoperational such that the particles or contaminants do not come in contact with operational components or circuitry.

[0011] This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used as an aid in limiting the scope of the claimed subject matter.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Certain embodiments of the disclosure will hereafter be described with reference to the accompanying drawings, wherein like reference numerals denote like elements. It should be understood, however, that the accompanying figures illustrate the various implementations described herein and are not meant to limit the scope of various technologies described herein. [0013] Fig. 1 is a diagram of conventional bonding voids, and their deleterious effect on bond integrity and electrical performance of direct-bonded interconnects.

[0014] Fig. 2 is a diagram showing various bonding and annealing scenarios, demonstrating how contaminants affect direct-bonding and example recesses to capture the contaminants.

[0015] Fig. 3 is a diagram showing example techniques for alleviating undesirable voids (voids not shown) and improving bond strength and integrity in manufacture of microelectronic packages.

[0016] Fig. 4 is a diagram of example patterns and arrays of recesses provided in bonding surfaces.

[0017] Fig. 5 is a diagram showing particle movement during bonding wave propagation, and placement of predesigned surface recesses in areas of maximum particle distribution.

[0018] Fig. 6 is a diagram of an example bonding surface with a large non bonding area, or recess, for capturing contaminants.

[0019] Fig. 7 is a diagram of an example bonding surface with recesses added to the surface to arrest propagation of bonding voids.

[0020] Fig. 8 is a diagram of an example bonding surface with large area non-bonded areas, or recesses, on both sides of a die or wafer, for making stacked structures. [0021] Fig. 9 is a diagram of an example bonding surface with large non bonding areas, or recesses, for capturing contaminants and ribbed bonding areas for improving bond propagation and increasing the overall bond contact area between joined surfaces.

[0022] Fig. 10 is a diagram showing conductive traces in the large area recesses with resulting electrical benefits.

[0023] Fig. 11 is a diagram of surfaces for direct hybrid bonding, with pads indented or dished to capture contaminants and protect bond integrity.

[0024] Fig. 12 is a flow diagram of an example method of enhancing bonds in microelectronic devices.

[0025] Fig. 13 is a flow diagram of an example method of enhancing bonds in microelectronic devices by determining locations of contaminants and capturing the contaminants.

[0026] Fig. 14 is a flow diagram of an example method of enhancing bonds in microelectronic devices by placing a recess in a bonding surface to arrest stress forces.

[0027] Fig. 15 is a flow diagram of an example method of building large area recesses around direct-bonding areas to capture contaminants around the direct- bonding areas in microelectronic devices.

[0028] Fig. 16 is a flow diagram of an example method of improving electrical characteristics of conductive traces by routing the traces in large area recesses. [0029] Fig. 17 is a flow diagram of an example method of placing indented or dished pads at a bonding surface to collect contaminants and enhance bonds in microelectronic devices.

[0030] Fig. 18 is a diagram of conventional rough sidewalls on a die and build-up layer with micro-fractures and resultant compromise of a dielectric bonding layer.

[0031] Fig. 19 is a diagram of a conventional process for sawing or dicing dies from a wafer, with chipping and compromise of the dielectric bonding layer.

[0032] Fig. 20 is a diagram of an example process for creating peripheral protective channels on a die to arrest cracking and chipping of the die and dielectric bonding layers, and to capture contaminants from interfering with a direct-bonding process.

[0033] Fig. 21 is a continuation of the example process of Fig. 20.

[0034] Fig. 22 is a diagram of various example configurations of the peripheral protective channels for arresting cracking and chipping of the die and dielectric bonding layers, and for capturing contaminants from interfering with a direct-bonding process

[0035] Fig. 23 is a diagram of different example configurations of peripheral protective channels at the dielectric bonding interface between two direct-bonded dies. DETAILED DESCRIPTION

Overview

[0036] This disclosure describes bond enhancement in microelectronics by trapping contaminants and arresting cracks during direct-bonding processes. Example surface structures and confinement techniques provide bond enhancement for fabrication of microelectronic components by capturing and sequestering particles, contaminants, and gaseous byproducts in predesigned recesses in the bonding surface during direct-bonding processes, and by arresting the propagation of cracks. Direct-bonding processes may be oxide-to- oxide bonding between nonmetals, such as dielectrics, or may be direct hybrid bonding that also includes metal-to-metal bonding at the bonding interface.

[0037] In example systems, bonding surfaces that have been planarized to a high degree of flatness are provided with recesses, sinks, traps, or cavities at predetermined places to capture small particles and gaseous byproducts of bonding that can create relatively large voids between the two surfaces being joined. Example recesses may be manufactured into a die or wafer during fabrication, at locations where particles collect when the particles move during bond wave propagation, during the direct-bonding. The recesses may also be generated in arrays, patterns, or bands at predetermined locations by etching a surface to be bonded. Recesses may be repeated in a stepped reticule pattern at the wafer level, for example, or may be placed by an aligner or alignment process.

Example Systems and Techniques

[0038] Fig. 2 shows various bonding and annealing scenarios, demonstrating how contaminants affect direct-bonding. In a first example, silicon wafers with native oxide are processed and then bonded in a room temperature direct- bonding process. In scenario 200, after 15 minutes at an annealing temperature of 150 °C, voids are not discernible, or are barely discernible by techniques such as confocal scanning acoustic microscopy (CSAM). In scenario 202, after 2 hours at an annealing temperature of 250 °C, numerous voids 10 are clearly visible on the CSAM image. The voids 10 may be the results of localized debonding caused by gaseous byproducts such as water and hydrogen molecules. The reactant byproducts may be generated and voids formed due to the dielectrics on silicon wafer, e.g., silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, etc. For example, low temperature oxide deposited via silane and TEOS processes can generate more reactant byproducts than silicon alone, which lead to generating voids during the bonding process. These voids may grow further during annealing at higher temperature. When void propagation is not prevented or checked, debonding and delamination can sometimes spread across the bonded surfaces. [0039] Scenario 204 shows movement of contaminant particles during direct- bonding. It has been discovered that certain direct-bonding processes cause contaminants, such as particles on the bonding surface, to move during bond wave propagation, as shown in scenario 204. When a pair of wafers with numerous small particles on the bonding surface are bonded together with the bonding initiated at the wafer center 206, the particles become mobile and are moved outward along the propagating bonding wave and then deposited by these forces in rings, for example rings 208 & 210 & 212 on the wafer. In scenario 214, when a pair of wafers with much fewer particles is bonded together, the particles also move and come to rest in a ring or rings along the bonding wave, although in fewer numbers. One or more example predesigned recesses 216 may be placed at or near each ring of maximum particle concentration.

[0040] Example systems determine locations where mobilized particles collect, and then place one or more predesigned recesses 216 next to the critical bonding areas as sinks or traps to collect and store the particles to prevent formation of bonding voids 10 in these critical areas.

[0041] Fig. 3 shows example techniques for alleviating undesirable voids (voids not shown) and improving bond strength and integrity in manufacture of microelectronic packages. [0042] In an implementation, a microelectronic component presents a first bonding surface 300. A second bonding surface 302 is suitable for bonding with the first bonding surface 300. Both surfaces are typically ultra-flat after CMP for direct-bonding or direct hybrid bonding. The two surfaces 300 & 302 may be surfaces of a first die and a second die in a D2D package construction, or a die and a wafer in D2W package construction, or may both be wafer surfaces in a W2W process, for example. In direct oxide-to-oxide bonding, the two surfaces 300 & 302 may be nonmetals, such as inorganic dielectric materials. In direct hybrid bonding the two surfaces 300 & 302 may include both dielectrics and metal conductors 301 & 303, such as pads, pins, leads, and connectors to be joined across the bonding interface.

[0043] In an implementation, the first bonding surface 300 is provided with predesigned recesses 304 & 304’ to capture at least one substance detrimental to the bond between the first bonding surface 300 and the second bonding surface 302. The planar dimension of the predesigned recess 304 can range from submicron in extent to tens or hundreds of microns. The depths of each predesigned recess 304 can vary from a few nanometers for trapping gaseous contaminants to several microns or more for trapping solid particles. Oxide-to- oxide direct-bonding, or other types of dielectric bonding, may release water vapor and hydrogen gas, for example. Chemical vapor deposited (CVD) oxides may also outgas during an annealing phase, as shown in scenario 202 of Fig. 2. [0044] Sometimes, if the dielectric layer being bonded has enough inherent defects, the gaseous byproducts are sinked innately, and detrimental voids 10 that could form randomly during an annealing step do not occur. Design of bonding surfaces 300 & 302 may include providing materials for the surfaces 300 & 302 that have inherent recesses with dimensions calculated to capture particles or other contaminants of the direct-bonding process at hand. Various schemes may be applied to create or provide surfaces 300 & 302 with a calculated degree of porosity, for example. If the dielectric layer does not have enough inherent spaces or pores to trap at least gases, then the gas molecules tend to aggregate in random locations to cause formation of the detrimental voids 10 during annealing. In contrast to the randomly formed bonding voids 10 which negatively affect electrical performance of the parts, the predesigned recess areas 304 & 304’ in designated places do not impact electrical performance adversely, but may improve the bond. In some cases predesigned recess 304 & 304’ can even enhance electrical performance.

[0045] Spacing between example recesses 304 & 304’ can be configured to relate to the relative cleanliness of the bonding process, the type of materials being bonded, and to the type of contaminants and bonding byproducts being generated by the bonding step or annealing step. If there is little debris and only a low level of byproducts, then the recesses 304 & 304’ may be smaller, and/or spaced further apart. (The recesses 304 shown in Fig. 3 are not to scale.) For example, conductive leads 301 & 303 to be bonded together may only be a few microns in width, and the recesses 304 imparted by etching, for example, may be even smaller, or may be larger.

[0046] The recesses 304 may be provided on only one surface 300. Or, recesses 306 & 308 may also be provided on both surfaces 300 & 302, with random alignment of the recesses 306 & 308 with respect to each other across the bonding interface.

[0047] Recesses 310 & 312 may be provided on both surfaces 300 & 302 and aligned with each other, so that each recess 310 & 312 forms half or some other fractional part of a resulting final recess 314 at the bonded interface 316. Aligning the recesses 310 & 312 with each other minimizes the unbonded surface area between the first bonding surface 300 and the second bonding surface 302.

[0048] Although the recesses 304 & 306 & 308 & 310 & 312 shown in Fig. 3 all appear to be of similar depth and width, they may have different depths, different widths, as well as different shapes. For example, recesses 304 & 304’ formed on the same surface 300 may have different shape, depth, and/or width. In another example, recesses 306 and 308 formed on different surfaces 300 and 302 may have different shapes, depths, and/or widths. Also, a single recess may have multiple depths. [0049] In Fig. 4, the predesigned recesses 402 & 404 & 406 & 408 (not to scale) of different shapes may be traps, sinks, cavities, indents, cups, or dished surfaces to be used for capturing contaminants. The predesigned recesses 402 & 404 & 406 & 408 may be arrayed or patterned to fit the specific direct-bonding process used and the type of materials being bonded. Predesigned recesses 402 & 404 & 406 & 408 are placed to make the bonding areas around them stronger with more consistent bonds. But since the recesses 402 & 404 & 406 & 408 themselves take up some of the bonding area, the minimum number of recesses 402 & 404 & 406 & 408 needed to immunize the bonding areas from contaminants may be calculated ahead of time, or may be determined before placement through an experimental run, for the particular circumstances of the specific direct-bonding process and materials. The sizes and spacing of predetermined recesses 402 & 404 & 406 & 408 may be customized to best capture particulate contaminants of one size, or bonding reaction byproducts of another size or type, or byproducts of an annealing step. Or, the sizes and spacing of predetermined recesses 402 & 404 & 406 & 408 may be customized for all, or averaged in view of all types of contaminants from all sources. In another example, a recess that has any shape may also include surface texturing to create nanopores or micropores on the surface of the recess. For example, porous silicon may use this scheme. [0050] In an implementation, a coating or deposition of palladium metal 408 or other hydride-forming metal may be added to the predesigned recesses to absorb hydrogen gas byproducts. Palladium, as used in microelectronics can absorb up to 900 times its own volume in hydrogen. Also, besides depositing palladium or a hydride-forming metal, any other metal or dielectric that can absorb and/or occlude reaction byproduct gases, moisture or a contaminant may also be deposited in the one or more predesigned recesses 402, 404, 406, 408. For example, one or more recesses may also be deposited with getter materials. Different getter materials can have different properties. For example, aluminum (Al) can have a getter capacity of about 1 Pa-l/mg against oxygen (O2). Barium (Ba) can have a getter capacity of about 0.69 Pa-l/mg against carbon dioxide (CO2), about 11.5 Pa-l/mg against hydrogen (H2), and about 2 Pa-l/mg against (O2). Titanium (Ti) can have about 4.4 Pa-l/mg against (O2). Thus, in some embodiments, the deposited material can be selected based on the types of gases that are likely to be present in the environment in which the bonded structure will be used.

[0051] In an implementation, a distributed pattern or array of recesses 402 & 404 & 406 & 408 may have first recesses 404 sized and spaced from each other for trapping fine particle contaminants, and second recesses 406 sized and spaced from each other for trapping a reaction byproduct, such as a gas, from a direct-bonding or annealing step. The recess 408 may run along the entire outer perimeter of the die. A contaminant to be captured may be a gaseous byproduct of an oxide-to-oxide direct-bonding process, a gaseous byproduct of a hybrid direct-bonding process, a gaseous byproduct of a bonding processes involving a chemical vapor deposition (CVD) oxide, a gaseous byproduct of a bonding processes involving a thermal oxide (TOX) silicon wafer or die, a gaseous byproduct of a bonding processes involving a silicon nitride surface, or a gaseous byproduct of a silicon-to-silicon direct-bonding process, for example.

[0052] Fig. 5 shows various example bonding wave patterns that occur during direct-bonding, and predesigned recesses in response to the bonding wave patterns. Various bonding waves have been found to mobilize particles and sweep the particles into characteristic patterns or resting places on bonding surfaces during direct-bonding.

[0053] In one scenario, at example bonding interface 502, propagation of the bonding wave front proceeds from one side to the other of an active bonding area 504 and sweeps the contaminants off their original positions in the direction of the propagating bonding wave front. The bonding interface 502 may be used in an example die-to-wafer (D2W) process using a porous bond head with left- edge-first contact that creates transverse bonding wave propagation, with moving particles distributed to a right side position. Predesigned traps, such as lines 506 & 508 of recessed areas can be placed at or near right angles to the direction of bonding wave propagation to collect the particles, for example near the active bonding area 504. The lines 506 and 508 of recessed areas can be placed such that the series of recesses in line 508 coincides with the series of openings of the recesses in lines 506 so that the contaminants not trapped in the line 506 of recesses move further in the direction of bonding wave propagation and are trapped in the line 508 of recesses. In the example D2W process, one or more linear bands of the recesses 506 & 508 can be placed at the locations of maximum particle distribution on the right side, for example.

[0054] In one technique, the recessed areas 506 & 508 can be allocated near bonding initiation locations to avoid contamination of the active bonding area 504 from the outset. When an active bonding area 504 is near the end of bonding wave propagation, then large traps 506 & 508 can be placed ahead of the active bonding area 504 to collect contaminants swept from other areas. These placement techniques can be useful in die-to-wafer (D2W) and die-to-die (D2D) direct-bonding processes. Some placements of the recesses 506 & 508 are useful for wafer-to-wafer (W2W) processes too.

[0055] At example bonding interface 509, propagation of the bonding wave front proceeds from a center line and proceeds to two sides 510 & 512, sweeping the contaminants off their original positions and in the direction of the propagating bonding wave fronts. For example, the lines of recessed areas 516/518 and 514/520 are placed such that the series of recesses in lines 514/520 coincides with the series of openings of the recesses in lines 516/518 so that the contaminants not trapped in the recesses of lines 516/518 move further in the direction of bonding wave propagation and are trapped in the recesses of lines 514/520. The bonding interface 509 may be used in an example D2W process using a curved bond head for the center-line-first contact moving to top and bottom edges, with the moving particles directed to the top side 510 and bottom side 512. Predesigned traps, such as recessed lines 514 & 516 and 518 & 520 can be placed at right angles to the direction of bonding wave propagations to collect the particles, for example near the active bonding area 522. The one or more linear bands of the recesses 514 & 516 and 518 & 520 can be placed at the top location 510 and bottom location 512 where maximum particle distribution occurs, for example.

[0056] At example bonding interface 524, propagation of the bonding wave front proceeds from a center point and proceeds outward to four sides 526 & 528 & 530 & 532, sweeping the contaminants off their original positions and in the direction of the propagating bonding wave fronts. Predesigned traps, such as recessed lines or arrays 534 & 536, 538 & 540, 542 & 544, and 546 & 548 can be placed at right angles to the direction of bonding wave propagations to collect the particles, for example near the active bonding area 550. Concentric rings, lines, or bands of the recesses can be placed near the peripheries where maximum particle distribution occurs, for example. [0057] In an example center-first W2W process, direct-bonding may move particles to a particular ring (e.g., 216 in Fig. 2) which may be centrally or peripherally located on the wafer. The recesses for capturing particulate contaminants may be located or concentrated in this ring area.

[0058] The various predesigned recesses in Fig. 5 may be etched grooves or may be sink holes created in the bonding surfaces to trap the particle movement during direct-bonding to protect critical areas from contaminants and detrimental bonding voids. Although, we have shown all the recessed lines or arrays to be outside the bonding area in Fig. 5, they may also be present within the bond area. This may be done to trap the contaminants that may not be displaced to longer distances by the propagating bond wave front.

[0059] Fig. 6 shows an example bonding surface 600 configured with a large area recess 602 (also referred to as a non-bonding area 602) for particle capture, to protect bond integrity of adjacent bonding areas 604 & 606. Bonding with another surface occurs in a bonding footprint area 604, which may off-put contaminants, particles, and byproducts of the bonding reaction to the large area recess 602, which then stores, binds, or sequesters them there. Particles in the large area recess 602 up to a certain size fit into the recess 602 and do not cause delamination in the bonded area 604.

[0060] In an implementation, the large area recess 602 completely surrounds the bonding footprint 604. In an implementation, another peripheral bonding area 606 may surround the large area recess 602 as part of the overall bonding area between the two surfaces that are being joined on either side of the bonding interface. The large area recess 602 can also capture particles and contaminants from the bonding reactions and/or annealing steps of the peripheral bonding area 606.

[0061] Multiple instances of the bonding surface 600 of a die or wafer can be bonded together in a stack 608. The recesses 602 for any one bonding interface can be additive when both sides of a bonding interface have recesses 602 that align. Or, the recess 602 of one bonding surface can capture contaminants for both bonding surfaces, even when one of the bonding surfaces is flat, without any recesses.

[0062] Fig. 7 shows an example bonding surface 700 that uses narrower recesses 702 & 708 for collecting contaminants from around bonding areas 704 & 706. This configuration may be especially applicable to thin and flexible semiconductor dies. Given that dies and wafers have an ultra-flat surface from CMP planarization, an offending particle 40 may also be very flat from the CMP process itself but can still create a large void between the bonded surfaces. Observational data suggest that a one micron particle in a horizontal X-Y dimension, with even lesser vertical height than one micron, may create a ten micron void or an even larger void in the interface between bonded surfaces 700. [0063] In Fig. 7, the relatively narrow recesses 702 have a purpose of providing the bonding interface with maximum bonding area for mechanical strength. Narrow recesses 702 surrounding a bonding area 704 can arrest the propagation of delaminating forces between surfaces bonded together as well as capture contaminants detrimental to direct-bonding. The narrow recesses 702 relieve stress forces that propagate delamination, whether caused by a particle 40 within the bond interface or not. Although recess 702 is shown completely surrounding bond area 704 in Fig. 7, in another implementation, recess 702 may only partially surround bond area 704.

[0064] In an implementation, narrow encompassing recess 702 forms a moat around bonding area 704, that prevents void propagation or a delaminating process from intruding into the bonding area 704 from outside the bonding area 704. Although, only one encompassing recess 702 is shown in Fig. 7, multiple recesses 702, partially or completely surrounding the bonding area 704, may be used, circumscribing each other with bands of bonding area between them, or in other configurations wherein each of the multiple recesses 702 partially surrounds at least a central bonding area 704. A pattern of other recesses (not shown) may also be deployed in the large bonding area 706, to relieve the stress forces that would lead to delamination of the surfaces from each other in the large bonding area 706. Placement of periodic recesses at intervals to relieve such stresses has an effect analogously similar to drilling a hole at the end of a crack in a material, to arrest the cracking process, or like adding aggregate rocks to cement to form concrete, in which propagation of a crack in the concrete is internally arrested when the crack meets a rock component of the concrete, which disperses the crack energy.

[0065] Likewise, a peripheral recess 708 prevents delamination from originating at the edges of the bonding surface 700, where the die has been sawn or diced, and where contaminant particles are likely to have collected. The ratio of the bonded surface 704 & 706 to recessed non-bonding surface areas 702 & 708 can vary, and can be any ratio between what is illustrated in Fig 6 and what is illustrated in Fig 7, for example.

[0066] The recessed areas 702 in a stack 710 formed by two or more bonded dies or wafers, can arrest the stress forces caused by a particle 40 and the resulting delamination 10. Such stresses can also be arrested and relieved by a recessed area 702, when the recessed area 702 is present in only one of the two surfaces being bonded.

[0067] Fig. 8 shows a die or wafer with large area recesses 802 (non bonding areas) for capturing contaminants on both front and back sides of the die or wafer. The example in Fig. 8 differs from the example in Fig. 6, in that the die or wafer that is shown has example bonding areas 804 & 806 on both top and bottom sides of the die or wafer. The recesses 802 on each side of the two-sided die or wafer may be large area recesses 802, as shown, but can also be recesses 802 with small or even microscopic horizontal spans. Bonding with another surface on another die or wafer occurs at bonding footprints 804 & 804’ and 806 & 806’, which expel contaminants, particles, and byproducts of the bonding reactions into the large area recesses 802 & 802’, which bind or sequester the contaminants there.

[0068] As shown in stack 808, particles up to a certain size fit in the large area recesses 802 & 802’, where they cannot further delaminate the bonded areas 804 & 804’. The large area recess 802 or 802’ can accommodate contaminant particles 40 that are twice as large as the particles captured by the large area recess 602 in Fig. 6, when the stacked large area recesses 802 & 802’ abut each other, providing twice the vertical height as the large area recess shown in Fig. 6. The respective large area recesses 802 & 802’ completely surround each respective bonding footprint 804 & 804’. In an implementation, respective peripheral bonding areas 806 & 806’ surround respective large area recesses 802 & 802’ and become part of the surface area of the overall bond between bonded surfaces 800. The same large area recesses 802 & 802’ also capture particles and contaminants from the peripheral bonding areas 806 & 806’.

[0069] Fig. 9 shows an example bonding surface 900 that is a variation of the bonding surface 600 shown in Fig. 6. In Fig. 9, strips or ribs of bonding area, such as strips 902 & 904, are located between the central bonding area footprint 908 and the peripheral bonding area 910, connecting the two. The ribbed bonding area strips 902 & 904 improve bond propagation and increase the overall bond contact area between surfaces 900 being joined. The resulting large area recesses 906, although smaller than that in Fig. 6, trap particles and reaction byproducts to protect bond integrity. Bonding with another surface occurs in the central bonding area footprint 908, the peripheral bonding area 910, and the various rib bonding areas 902 & 904, all of which may off-put contaminants, particles, and byproducts of the bonding reaction to the large area recesses 906 located between these. Particles up to a certain size that fit in the large area recesses 906 are removed from causing or propagating further delamination in the bonded areas 908 & 910 & 902 & 904. Likewise, the large area recesses 906 also capture particles and contaminants from annealing steps.

[0070] Although Figs. 6-9 show a central rectangular bonding area, characteristic for use in DRAM HBM applications, the layout of a given bonding surface can include multiple active bonding areas, and these can be separated by recessed areas to capture contaminants. Active bonding areas can also be connected together, with isolated recessed areas that have random shapes predesigned into the layout. One or more active bonding areas in a given implementation can be any shape, such as square, rectangular, circular, polygonal, star-shaped, and so forth. [0071] Fig. 10 shows a stack structure 1002, such as stacked dies 1004 that have been bonded into the stack 1002 by joining bonding surfaces of the example dies 1004 at bonding interfaces 1006 & 1008, for example. The large area recesses 1010 provide an electrical benefit for conductive traces 1012 that are placed to traverse the recesses 1010, causing signals that run in traces 1012 in the recesses 1010 to have lower dielectric loss, and lower capacitive loss than those traces 1012 embedded in or laminated between semiconductor materials such as silicon. The dielectric loss and the capacitive loss can be controlled, for example, by configuring a geometry of an air space in a given recess 1010. The signal-carrying benefit can be significant when the conductive traces 1012 traverse relatively large area recesses 1010.

[0072] Fig. 11 shows a first bonding surface 1100 and a second bonding surface 1102, with conductive pads 1104 & 1106 for making an electrical interconnect to be joined from the respective surfaces 1100 & 1102 when the surfaces are bonded. The bonding surfaces 1100 & 1102 may be surfaces undergoing a D2W join or a W2W join. The bonding technique can be a direct dielectric bonding or direct hybrid bonding process. Relatively larger size pads 1108, which may be nonoperational dummy pads unconnected to circuitry, are distributed among the conductive pads 1104 & 1106. These larger pads 1108 are subject to a degree of dishing 1110 during one or more chemical mechanical planarization steps (CMP), creating deeper recesses 1110 in the pads 1108 compared to conventional recesses in pads 1104 or 1106 with narrower width. In an implementation, the deeper recesses can be placed to capture loose particles and bonding reaction byproducts. Significant dishing for capturing contaminants may occur or may be obtained to form an example recess 1110 when the width of the pad 1108 is 10 pm or greater, or at least two-times larger than the electrical conductive pads 1104 and 1106, which may be DBI pads, for example.

[0073] Alternatively, larger pads 1112 may be intentionally recessed from the bonding surface 1100 by design and manufacture. Such recessed pads 1112 can be wide or narrow, depending on the amount of contaminants to be captured to protect the bond. As the bond is formed, some particles and gaseous byproducts of the bonding reaction tend to move to any space available as the gap between surfaces 1100 & 1102 disappears, resulting in contaminants and byproducts being trapped in the recess 1114. Locations of particle build-up can also be determined by calculation or observation. The larger pads 1112 with predesigned recesses 1114 can be placed at the determined locations of particle build-up.

[0074] CSAM, or confocal scanning acoustic microscopy images, have shown that the predesigned recesses successfully sequester particles and bond reaction byproducts, resulting in very few bonding voids. The absence of voids provides a strong bond with high bond integrity and full electrical connection of bonded interconnects. Electrical tests of the bonded interconnects affirm the results of the CSAM images, that the example predesigned recesses result in a notable absence of undesirable bonding voids.

Example Methods

[0075] Fig. 12 shows an example method 1200 for enhancing bonds in microelectronic devices. Operations of the example method 1200 are shown in individual blocks.

[0076] At block 1202, recesses are provided in a bonding surface of a die or wafer.

[0077] At block 1204, the bonding surface is planarized to flatness for direct- bonding. The example method 1200 may be used with other general types of bonding operations. CMP or other measures may be used to obtain a surface flatness suitable for direct-bonding and direct hybrid bonding processes. Some or all of the recesses may be formed during or after this step instead of at block 1202.

[0078] At block 1206, the bonding surface is joined in a direct-bonding operation or a direct hybrid bonding operation to another bonding surface, allowing the recesses to capture particles, contaminants, and bonding reaction byproducts. [0079] Fig. 13 shows another example method 1300 for enhancing bonds in microelectronic devices. Operations of the example method 1300 are shown in individual blocks.

[0080] At block 1302, a location is determined at which particles collect during a direct-bonding process between a first bonding surface and a second bonding surface, wherein propagation of a bonding wave front during the direct- bonding process mobilizes and moves the particles.

[0081] At block 1304, a recess is placed in the first bonding surface or the second bonding surface at the location to prevent the particles from interfering with the direct-bonding process.

[0082] At block 1306, the first surface and the second surface are direct- bonded together.

[0083] A recess may be placed in both the first bonding surface and the second bonding surface at or near the location.

[0084] A first recess in the first bonding surface may be vertically aligned with a second recess in the second bonding surface across a bonding interface between the first bonding surface and the second bonding surface, to make an additive or composite recess across the bonding interface.

[0085] In an implementation, predesigned recesses can be created in a bonding surface by etching. Locations where build-up of particles occurs in higher concentrations can be determined by calculating or observing propagation of a bonding wave front proceeding from one side of an active bonding area to an opposing side of the active bonding area. Or, the bonding wave front may proceed from a center line of an active bonding area to two opposing sides of the active bonding area. Likewise, the bonding wave front may proceed from a center point of an active bonding area to four sides of the active bonding area (or may propagate in even more directions and to more sides).

[0086] Linear recesses, or a pattern of one or more lines of point recesses, may be placed at right angles to a direction of bonding wave propagation to collect the particles.

[0087] Recess dimensions can vary according to application and according to the likely contaminants. In an implementation, the horizontal width of a recess may be less than one micron or may even be nanometers in extent, and larger up to hundreds of microns in width.

[0088] The depth dimension of an example recess can range from a few nanometers for trapping gaseous contaminants to several microns for trapping particles. The depth of the recess (es) may be larger than pad thickness used in a direct hybrid bonding (e.g., DBI) bonding process. The recess (es) may be devoid of active componentry, MEMS devices, etc., in order to isolate the contaminants away from potentially sensitive areas of the microelectronic devices. The recess (es) may also be limited in the x, y, and z directions to maximize regions for circuitry, MEMS, or other operational features. [0089] In an implementation, predesigned recesses can also be implemented in some wafers, for example, by selecting or creating a material with a given porosity or other inherent pattern of recesses.

[0090] Fig. 14 shows another example method 1400 for enhancing bonds in microelectronic devices. Operations of the example method 1400 are shown in individual blocks.

[0091] At block 1402, a location or the direction of likely propagation of a stress force is determined for a bonding interface of a direct-bonding operation.

[0092] At block 1404, one or more recesses are placed in a bonding surface at the location or along the direction, to arrest propagation of the stress force. In an implementation, a pattern of periodic recesses or holes can provide“breaks” for stress forces acting in the horizontal plane of a microscale direct-bonding interface.

[0093] At block 1406, the bonding surface with the one or more recesses is direct-bonded to another surface.

[0094] Fig. 15 shows another example method 1500 for enhancing bonds in microelectronic devices. Operations of the example method 1500 are shown in individual blocks. [0095] At block 1502, a large area recess is formed completely around an active bonding area for direct-bonding, the active bonding area within a horizontal plane of a bonding surface.

[0096] At block 1504, the bonding surface is direct-bonded to another surface, with the large area recess capturing contaminants adverse to the direct- bonding in the active bonding area.

[0097] Fig. 16 shows another example method 1600 for enhancing bonds in microelectronic devices. Operations of the example method 1600 are shown in individual blocks.

[0098] At block 1602, a large area recess is formed near an active bonding area for direct-bonding. The active bonding area is within a horizontal plane of a bonding surface.

[0099] At block 1604, a conductive trace is routed through the large area recess. The large area recess lowers the dielectric loss and/or capacitive loss of the conductive trace.

[00100] At block 1606, the bonding surface is direct-bonded to another surface. The large area recess captures contaminants adverse to the direct- bonding that occurs in the active bonding area. [00101] Fig. 17 shows another example method 1700 for enhancing bonds in microelectronic devices. Operations of the example method 1700 are shown in individual blocks.

[00102] At block 1702, pads placed at a bonding surface are indented, or dished by a chemical mechanical planarization (CMP) process.

[00103] At block 1704, the bonding surface is direct-bonded to another surface, while the indented or dished pads capture contaminants detrimental to the direct-bonding process.

[00104] Fig. 18 shows a close-up view of rough sidewall edges 1802 of surfaces 1804 of dies to be bonded, including conventional chipping 50 (also shown in Fig. 1) caused by the surfaces 1804 being diced or sawn along the edges. Resulting residues from the sawing or dicing may also be present. The surfaces 1804 may be microelectronic dies, but may be other surfaces suitable for bonding. The rough and chipped edges 50 may spawn further chipping or crumbling of the edge 1802 or micro-fractures 60 (Fig. 1) in the surfaces 1804, which may propagate further across the surfaces 1804 when pressure is applied for bonding, or when the surfaces 1804 thermally expand and contract. The chipping 50 may occur at edges of the die material (e.g., silicon) or at edges of a dielectric layer (polymer material). In a cross-sectional side view of a bonded structure 1806 between two of the surfaces 1804, the chipping 50 results in a post bonding defect 1808, such as a gap or void, between the two bonded surfaces 1804.

[00105] Fig. 19 shows a conventional process and production circumstances in which the rough sidewall edges 1802 and chipping 50 of die material and dielectric layers can occur, and propagate. A substrate 1902 with a smooth bonding surface 1904 has a coating, such as a dielectric layer 1906. A resist layer 1908 is then applied and patterned. Etching 1910 is performed through a wiring layer (not shown) in the dielectric layer 1906 and into a portion of the substrate material 1902. Next, the dies are sawn for singulation, creating narrower saw cut lanes 1912 within the etch regions 1910 of the substrate 1902. The resist layer 1908 is removed. The sawing-dicing of lanes 1912 during the singulation step may cause chipping 50 of the dielectric layer 1906, as shown in the bottom close-up view or cracks 60 in the dielectric layer 1906.

[00106] Fig. 20 shows an example process for making protective cavities, recesses, trenches, channels, and so forth, near the edges of dies or dielectric bonding layers, in order to arrest the propagation of stresses, chipping, crumbling, cracking, fissuring, and fracturing of a rough, chipped, or compromised edge that may be present from sawing, dicing, singulation, or other processes.

[00107] A substrate 2002 with a smooth bonding surface 2004 has a coating, such as a dielectric layer 2006. A resist layer 2008 is applied and patterned. For each of the underlying dies 2010 & 2012 & 2014, the patterning of the resist layer 2008 creates an outer trench or channel 2016 and an inner trench or channel 2018 near the edge of each die, where the die will be sawn or diced from a wafer. These channels 2016 & 2018 may be patterned to follow a periphery of the given die. For example, for die 2012, the outer channel 2016 represents the lane where the die 2012 will be sawn or diced, and the inner channel 2018 represents the position of a protection channel 2018 for arresting chipping, fissure propagation, and/or microfracture propagation from the sawing or dicing procedure.

[00108] An etching process 2020 using the patterned resist layer 2008 as template, etches through the dielectric layer 2006, through wiring layers (not shown) within the dielectric layer 2006, and etches a distance, or a predetermined depth into the substrate material 2002 of the dies 2010 & 2012 & 2014. Next, narrower saw cuts 2022 for singulating the dies may be made in the outer channels 2016 with respect to each die 2010 & 2012 & 2014.

[00109] In Fig. 21 , the process of Fig. 20 continues with resist stripping 2102 and die cleaning. Each die 2012 resulting from the process now has a smooth dielectric bonding layer for direct bonding or direct hybrid bonding to another die or wafer, and has die protection channels 2018 located near edges of the dielectric layer 2006 that have been sawn. These die protection channels or recesses 2018 arrest the propagation of any chipping, crumbling, fissuring, or fracturing of the dielectric bonding layer 2006 near the edges, thereby increasing the yield of good dies 2012 and good die stacks or microelectronic packages made from the dies 2012.

[00110] Fig. 22 shows different example styles for implementing the protection channels 2018 in the semiconductor material of a die 2012 or in the dielectric bonding layer 2006 of a die 2012, or in both.

[00111] Besides arresting the propagation of stresses, chipping, crumbling, cracking, fissuring, and fracturing at the edges of dies 2012 or dielectric layers 2006, the protection channels 2018 can also act as recesses for holding residues from the dicing or sawing operation itself that would interfere with direct bonding at the smooth dielectric bonding layer 2006, or can act as a getter space for capturing byproducts of the direct bonding operations or other environmental contaminants that would interfere with a direst bonding process or cause voids 10 in the direct bonding interface. The protection channel 2018 acting as a recess for capturing contaminants is also shown at recess 404 in Fig. 4.

[00112] Fig. 22 shows different example implementations of the protection channels 2018 of Fig. 21. In configuration 2202, a top view of the die 2012 has the protection channels 2018 as peripheral cavities or trenches around the periphery of the die 2012, through the top dielectric bonding layer and into the semiconductor material of the die 2012, or into a substrate material if the surface being direct bonded is not a die 2012. [00113] In configuration 2204, a top view of the die 2012 has protection channels 2018 as multiple parallel peripheral cavities or trenches around the periphery of the die 2012, through the top dielectric bonding layer and into the semiconductor material of the die 2012, or into a substrate material if the surface being direct bonded is not a die 2012.

[00114] In configuration 2206, a top view of the die 2012 has protection channels 2018 as cross-cut peripheral cavities or trenches around the periphery of the die 2012, through the top dielectric bonding layer and into the semiconductor material of the die 2012, or into a substrate material if the surface being direct bonded is not a die 2012.

[00115] In configuration 2208, a top view of the die 2012 has protection channels 2018 as discontinuous peripheral cavities or trenches or an array of discontinuous cavities disposed parallel or nonparallel (with respect to the edges of the die) around the periphery of the die 2012, through the top dielectric bonding layer and into the semiconductor material of the die 2012, or into a substrate material if the surface being direct bonded is not a die 2012. In one embodiment, the top view of the channels 2018 may comprise one or more arrays of curvilinear lines or geometric features.

[00116] Fig. 23 shows two dies direct-bonded together at the interface of their respective dielectric bonding layers 2006. At configuration 2302, the peripheral protective channels 2018 of each respective die line up vertically to provide a single protective channel 2018 through both dielectric layers, now direct-bonded together. This configuration may be desirable for arresting the propagation of some types of micro-fissures from crossing the direct-bonding interface, and for collecting some types of contaminants, to remove the contaminants from interfering with the direct bonding process.

[00117] At configuration 2304, the protective channels 2018 are vertically staggered. The horizontal offset of the peripheral protective channels 2018 may provide some structural advantages, and can be useful for collecting some kinds of contaminants that would interfere with the direct bonding process.

[00118] Example configuration 2306 shows the vertically staggered protective channels 2018 with a local chipping process 2308 arrested by one of the protective channels 2018.

[00119] In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols have been set forth to provide a thorough understanding of the disclosed embodiments. In some instances, the terminology and symbols may imply specific details that are not required to practice those embodiments. For example, any of the specific dimensions, quantities, material types, fabrication steps and the like can be different from those described above in alternative embodiments. The term“coupled” is used herein to express a direct connection as well as a connection through one or more intervening circuits or structures. The terms“example,”“embodiment,” and “implementation” are used to express an example, not a preference or requirement. Also, the terms“may” and“can” are used interchangeably to denote optional (permissible) subject matter. The absence of either term should not be construed as meaning that a given feature or technique is required.

[00120] Various modifications and changes can be made to the embodiments presented herein without departing from the broader spirit and scope of the disclosure. For example, features or aspects of any of the embodiments can be applied in combination with any other of the embodiments or in place of counterpart features or aspects thereof. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

[00121] While the present disclosure has been disclosed with respect to a limited number of embodiments, those skilled in the art, having the benefit of this disclosure, will appreciate numerous modifications and variations possible given the description. It is intended that the appended claims cover such modifications and variations as fall within the true spirit and scope of the disclosure.