Title:
BONDING MEMBER FOR SEMICONDUCTOR DEVICES
Document Type and Number:
WIPO Patent Application WO/2022/059286
Kind Code:
A1
Abstract:
A bonding member 10 which is used for the purpose of bonding a semiconductor device 20 and a substrate 30, and which is provided with: a thermal stress relaxation layer 11 that is composed of any one of Ag, Cu, Au and Al; a first Ag brazing material layer 12 that is mainly composed of Ag and Sn and is provided on a surface of the thermal stress relaxation layer, to said surface the semiconductor device being to be bonded; a second Ag brazing material layer 13 that is mainly composed of Ag and Sn and is provided on a surface of the thermal stress relaxation layer, to said surface the substrate being to be bonded; a first barrier layer 14 that is composed of Ni and/or an Ni alloy and is provided between the thermal stress relaxation layer and the first Ag brazing material layer; and a second barrier layer 15 that is composed of Ni and/or an Ni alloy and is provided between the stress relaxation layer and the second Ag brazing material layer. The thermal conductivity of this bonding member after a power cycle test is 200 W/m·K or more.
Inventors:
FUKUI AKIRA (JP)
FUKUI TOSHIE (JP)
FUKUI TOSHIE (JP)
Application Number:
PCT/JP2021/024313
Publication Date:
March 24, 2022
Filing Date:
June 28, 2021
Export Citation:
Assignee:
SUPERUFO291 TEC (JP)
International Classes:
H01L23/36; B23K35/14; B23K35/30; H01L21/52
Domestic Patent References:
| WO2017183222A1 | 2017-10-26 |
Foreign References:
| JP2006032888A | 2006-02-02 | |||
| JP2019079960A | 2019-05-23 | |||
| JPH04192341A | 1992-07-10 | |||
| JP2020098848A | 2020-06-25 | |||
| JP2001110959A | 2001-04-20 | |||
| JPH0534979B2 | 1993-05-25 | |||
| JP2013229474A | 2013-11-07 | |||
| JP2019036603A | 2019-03-07 | |||
| JP2019079960A | 2019-05-23 |
Other References:
KATSUAKI SUGANUMA ET AL.: "System Integration of Wide Band Gap Semiconductors", 31 May 2016, CMC PUBLISHING CO., LTD
"MODULE MOUNTING", December 2008, OSAKA UNIVERSITY
SHINICHI YASAKA ET AL.: "STUDY OF POWER CYCLING TEST METHODS FOR EVALUATION OF DIE ATTACH MATERIALS", KANAGAWA INDUSTRIAL TECHNOLOGY CENTER, 1 October 2016 (2016-10-01)
AKIRA MOROZUMI ET AL.: "Reliability design technique in power semiconductor module", 10 February 2001, FUJI ELECTRIC CO., LTD.
KOJI YAMAGUCHI ET AL.: "Quality and Reliability Integration Technology in Automotive Semiconductor Products", 10 March 2011, FUJI ELECTRIC CO., LTD.
See also references of EP 4174934A4
"MODULE MOUNTING", December 2008, OSAKA UNIVERSITY
SHINICHI YASAKA ET AL.: "STUDY OF POWER CYCLING TEST METHODS FOR EVALUATION OF DIE ATTACH MATERIALS", KANAGAWA INDUSTRIAL TECHNOLOGY CENTER, 1 October 2016 (2016-10-01)
AKIRA MOROZUMI ET AL.: "Reliability design technique in power semiconductor module", 10 February 2001, FUJI ELECTRIC CO., LTD.
KOJI YAMAGUCHI ET AL.: "Quality and Reliability Integration Technology in Automotive Semiconductor Products", 10 March 2011, FUJI ELECTRIC CO., LTD.
See also references of EP 4174934A4
Attorney, Agent or Firm:
KYOTO INTERNATIONAL PATENT LAW OFFICE (JP)
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