CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 62/307,056, filed on March 11, 2016, and U.S. Non-Provisional Patent Application No.

15/442,886, filed on February 27, 2017, which are incorporated herein by reference in their entirety.

TECHNICAL FIELD

[0002] The present disclosure generally relates to a high power factor buck-boost (flyback) converter and control circuit and method used therein.

SUMMARY

[0003] Figure 1 depicts a related-art high power factor discontinuous conduction-mode (DCM) flyback converter for receiving input voltage V _EST from a rectified AC line voltage source 100 and for delivering regulated DC output voltage VOU _T to an output load 190. The flyback converter of Figure 1 includes: a magnetic element 103 having a primary winding PRI, and a secondary winding SEC; a controlled switch 102 having a gate and a drain terminals; a rectifier diode 105; and an output filtering capacitor 106.

[0004] The flyback converter of Figure 1 also includes a control circuit, which includes an integrator 107 having inverting and a non-inverting inputs for integrating the difference between VOU _T and a reference voltage V _REF , and having an output for delivering the resulting integral voltage. The control circuit also includes a clock signal CLK, a source of linear ramp voltage V _RAMP , and a comparator 108 having an output, and inverting and non-inverting inputs for comparing the output voltage of the integrator 107 and the ramp voltage V _RAMP - The control circuit may also include a flip-flop circuit 109 for turning the controlled switch 102 on and off repeatedly at a high frequency rate, having an output Q coupled to the gate of the switch 102, a set input S for receiving the clock signal CLK and for toggling the output Q on when CLK is received, and a reset input R for receiving the output of the comparator 108 and for toggling the output Q off.

[0005] Figure 2 illustrates the gate waveform 202 of the voltage at the gate of switch 102, and the drain voltage waveform 201 of the drain voltage V _D at the drain of switch 102. The converter of Figure 1 is operated at a fixed switching period Tsw determined by the clock signal CLK. The time interval TO _N represents the conductive state of the switch 102. The non- conductive state is represented by conduction of the diode 105 followed by a post-conduction oscillation of the drain voltage 201.

[0006] The integration time constant of the integrator 107 is selected much greater than a period of the rectified AC line voltage 100 and, therefore, the time interval TO _N can be considered to be constant over an individual AC line cycle. The input current of a DCM flyback converter averaged over one switching cycle can be expressed as:

[0007] where Reff=LpRi Tsw ToN ² is the effective input resistance. The converter of Figure 1 features natural unity power factor, since both TO _N and Tsw are fixed.

[0008] However, the natural high power factor flyback converter of Figure 1 operates in deep discontinuous conduction mode. As a result, the switch 102 is stressed with high peak and RMS current causing high conduction and turn-off power losses. At high switching frequency (or low Tsw) and high voltage V _D across the switch 102, turn-on power losses also become significant due to large parasitic energy stored in output capacitance of the switch 102 and other parasitic capacitances.

[0009] Figure 3 shows another related-art high power factor discontinuous conduction- mode (DCM) flyback converter including all elements of the converter of Figure 1 , except wherein the clock signal CLK is replaced by a valley detector circuit 101 for detecting a post- conduction oscillation valley of the drain voltage 201 and for triggering the set input S to turn the switch 102 on when the valley is detected. This minimum-voltage valley switching is illustrated by a drain voltage waveform 210 of the switch 102 shown in Figure 4.

[0010] The converter of Figure 3 achieves improved efficiency compared to the converter of Figure 1 due to the smallest peak and RMS current possible for a DCM converter and due to turning the switch 102 on at minimum possible voltage across it. However, the switching period Tsw becomes variable over the AC line cycle of the input voltage 100, causing non-constant effective input resistance R _eff and, therefore, distortion of input current. Hence, a control circuit is needed to overcome the deficiencies of constant-ToN control in the converter of Figure 3.

[0011] According to an aspect of one or more exemplary embodiments, there is provided a high power- factor buck-boost converter for receiving input voltage from a rectified AC line voltage source and for delivering regulated DC output voltage to an output load that may include a magnetic element, a controlled switch having a gate terminal and a drain terminal that is coupled to the magnetic element, a rectifier diode coupled to the magnetic element, an output smoothing capacitor coupled to the rectifier diode, and a control circuit having an output coupled to the gate terminal of the controlled switch for repeatedly turning the controlled switch off for a first time duration and on for a second time duration. The second time duration may be determined as a function of the first time duration immediately preceding the second time duration.

[0012] The high power-factor buck-boost converter may also include a valley detection circuit configured to detect a post-conduction oscillation valley of a voltage at the drain terminal of the controlled switch, wherein the valley detection circuit may output a control signal, which may be used by the control circuit to control the controlled switch. The control circuit may cause the controlled switch to turn on once the control signal is received from the valley detection circuit.

[0013] The control circuit may turn the controlled switch on no sooner than when the rectifier diode becomes reverse-biased. The control circuit may determine the second time duration such that the quotient of the square of the second time duration and the sum of the first time duration and the second time duration is substantially constant over a cycle of the rectified AC line voltage.

[0014] According to an aspect of one or more exemplary embodiments, the high power- factor buck-boost converter may include an error detector circuit configured to receive as inputs an output voltage from the output smoothing capacitor and a reference voltage, and output a difference voltage that is equal to the difference between the output voltage and the reference voltage. The control circuit may use the difference voltage to determine the first time duration and the second time duration. The high power-factor buck-boost converter may also include an integrator circuit configured to generate a control voltage that is a time integral of the difference voltage, wherein, the control circuit may determine the first time duration and second time duration based on the control voltage. [0015] According an aspect of one or more exemplary embodiments, the high power- factor buck-boost converter may also include a current sense circuit configured to measure an output current of the high power- factor buck-boost converter and output a sense voltage that is proportional to a measured output current of the high power-factor buck-boost converter. The error detector circuit may be configured to receive as inputs the sense voltage, and a reference voltage. The error detector circuit may be configured to output a difference voltage that is equal to the difference between the sense voltage and the reference voltage.

[0016] According to yet another aspect of one or more exemplary embodiments, the high power-factor buck-boost converter may include an analog differential integrator configured to receive as inputs an output voltage from the output smoothing capacitor and a reference voltage, and output a difference voltage that is equal to the difference between the output voltage and the reference voltage, wherein the analog differential integrator is configured to generate a control voltage that is a time integral of the difference voltage.

[0017] According to still another aspect of one or more exemplary embodiments, the control circuit may include a flip-flop circuit configured to turn the controlled switch on and off repeatedly at a high frequency rate, a controlled ramp generator configured to generate a linear voltage ramp having a slew rate that is proportional to the control voltage, a fixed ramp generator configured to generate a quadratic voltage ramp having a slew rate that is proportional to a time duration of an active state of an output of the flip-flop circuit, and a comparator circuit configured to compare the linear voltage ramp and the quadratic voltage ramp.

[0018] The fixed ramp generator may reset the quadratic ramp voltage to an initial level in response to the output of the flip-flop circuit entering an inactive state. The comparator circuit may include an output that is coupled to a reset input of the flip-flop circuit, wherein the output of the comparator circuit may be configured to terminate the active state of the output of the flip- flop circuit and reset the linear voltage ramp to an initial level in response to the quadratic voltage ramp exceeding the linear voltage ramp.

[0019] According to yet another aspect of one or more exemplary embodiments, the high power-factor buck-boost converter may include a combined signal generator configured to receive the control voltage and generate an output voltage, and a comparator circuit configured to compare the output voltage generated by the combined signal generator and an initial voltage level. Then output of the comparator circuit may be coupled to a reset input of the combined signal generator to reset the output voltage of the combined signal generator to the initial voltage level, and the combined signal generator may include an input that is coupled to an output of the flip-flop circuit.

[0020] According to another aspect of one or more exemplary embodiments, there is provided a method of achieving a high power factor in a DCM buck-boost converter. The method may include turning a controlled switch of the buck-boost converter off; generating a linear signal ramp; determining whether a magnetic element that is coupled to the controlled switch is in a discontinuous conduction mode; in response to determining that the magnetic element is in a discontinuous conduction mode, determining whether a time duration of a non- conductive state of the controlled switch has reached an end of the non-conductive state; in response to determining that the time duration of the non-conductive state of the controlled switch has reached the end of the non-conductive state, turning on the controlled switch;

generating a quadratic signal ramp; determining whether the quadratic signal ramp exceeds the linear signal ramp; and in response to determining that the quadratic signal ramp exceeds the linear signal ramp, turning the controlled switch off. [0021] According to still another aspect of one or more exemplary embodiments, there is provided a method of achieving a high power factor in a DCM buck-boost converter. The method may include turning a controlled switch of the buck-boost converter off; determining whether a magnetic element that is coupled to the controlled switch is in a discontinuous conduction mode; in response to determining that the magnetic element is in a discontinuous conduction mode, determining whether a time duration of a non-conductive state of the controlled switch has reached an end of the non-conductive state; in response to determining that the time duration of the non-conductive state of the controlled switch has reached the end of the non-conductive state, computing a time duration of a conductive state of the controlled switch as a function of the time duration of the non-conductive state.

[0022] According to an aspect of one or more exemplary embodiments, there is provided a high power- factor buck-boost converter that may include a magnetic element, a controlled switch having a gate terminal and a drain terminal that is coupled to the magnetic element, a rectifier diode coupled to the magnetic element, an output smoothing capacitor coupled to the rectifier diode, and a control circuit having an output coupled to the gate terminal of the controlled switch for repeatedly turning the controlled switch off for a first time duration, turning the controlled switch on for a second time duration immediately following the first time duration, and turning the controlled switch on for a third time duration immediately preceding the first time duration. The first time duration may include a time duration of a non-conductive state of the rectifier diode, and the second time duration may be determined as a function of the third time duration and the time duration of a non-conductive state of the rectifier diode.

[0023] The control circuit may generate a fourth time duration as a product of the third time duration and the quotient of the input voltage and the output voltage. The control circuit may determine the second time duration such that the quotient of the square of the second time duration and the sum of the fourth time duration, the time duration of a non-conductive state of the rectifier diode, and the second time duration is substantially constant over a cycle of the rectified AC line voltage.

[0024] The magnetic element may include a primary winding and a secondary winding having a turns ratio. The control circuit may generate the fourth time duration as a product of the third time duration and the quotient of the input voltage and the output voltage reflected to the primary winding by the turns ratio.

BRIEF DESCRIPTION OF DRAWINGS

[0025] Fig. 1 illustrates flyback converter according to the related art.

[0026] Fig. 2 illustrates voltage waveforms of the flyback converter shown in Fig. 1.

[0027] Fig. 3 illustrates another flyback converter according to the related art.

[0028] Fig. 4 illustrates voltage waveforms of the flyback converter shown in Fig. 3.

[0029] Fig. 5 illustrates a flyback converter according to an exemplary embodiment.

[0030] Fig. 5a illustrates a flyback converter according to another exemplary

embodiment.

[0031] Fig. 6 is a waveform diagram illustrating the performance of the exemplary flyback converter of Fig. 5.

[0032] Fig. 7 is a flowchart illustrating a control method for a flyback converter according an exemplary embodiment.

[0033] Fig. 8 illustrates a flyback converter according to another exemplary embodiment.

[0034] Fig. 9 is a flowchart illustrating a real-time control method for a flyback converter according to an exemplary embodiment. [0035] Fig. 10 illustrates a flyback converter according to yet another exemplary embodiment.

[0036] Fig. 1 1 is a waveform diagram illustrating the performance of the exemplary flyback converter of Fig. 10.

[0037] Fig. 12 illustrates a flyback converter according to yet another exemplary embodiment.

[0038] Fig. 13 is a waveform diagram illustrating the performance of the exemplary flyback converter of Fig. 12.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

[0039] Reference will now be made in detail to the following exemplary embodiments, which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. The exemplary embodiments may be embodied in various forms without being limited to the exemplary embodiments set forth herein. Descriptions of well-known parts are omitted for clarity.

[0040] Figure 5 shows a high power factor discontinuous conduction-mode (DCM) flyback converter according to an exemplary embodiment of the present disclosure. Referring to Fig. 5, the flyback converter of the exemplary embodiment may receive an input voltage V _EST from a rectified AC line voltage source 100 and deliver a regulated DC output voltage VOU _T to an output load 190. The flyback converter of Figure 5 may include a magnetic element 103 having a primary winding PRI, and a secondary winding SEC; a controlled switch 102 having a gate terminal and a drain terminal; a rectifier diode 105; an output smoothing capacitor 106; and a control circuit 199 having a TON output coupled to the gate terminal of the switch 102 for turning the switch on and off repeatedly at a high frequency rate. The flyback converter of Figure 5 may also include a valley detector 101. The control circuit 199 may also include a clock input CLK coupled to the valley detector 101.

[0041] Figure 5a depicts a converter according to another exemplary embodiment that is similar to the exemplary embodiment of Figure 5, but wherein the magnetic element 103 is replaced by an inductor 303 having a single winding.

[0042] Figure 6 illustrates operation of the exemplary flyback converter of Figure 5. Waveform 202 represents the voltage at the output TON controlling the gate of the switch 102, where ΤΟΝ _,Π is a conductive state of the switch 102, ToFF,n-i is its non-conductive state immediately preceding ΤΟ _Ν,Π - Waveform 210 represents an exemplary drain voltage V _D of the switch 102.

[0043] In order to maintain discontinuous conduction-mode (DCM), the control circuit 199 permits a conductive state ΤΟ _Ν,Π of the switch 102 no sooner than the diode 105 becomes reverse-biased. This condition can be fulfilled by design, or using one of the known zero-current detection methods. Once the DCM operation is guaranteed, the switch 102 conducts for a time duration ΤΟ _Ν,Π computed in accordance with the following control law:

— n

¹ OFF,n-l ^{T 1} ΟΝ, ^η ^2)

[0044] where To is a time constant substantially fixed over a cycle of the rectified AC line voltage.

[0045] As shown in equation (2), the control law is iterative, since ΤΟ _Ν,Π in any given switching cycle is determined by ToFF,n-i in a preceding cycle, which, in turn, is an explicit function of ΤοΝ,η-i- Moreover, a direct substitution of TO _FF,II - _I with (m^ToN.n-i+AT) can be made in the control law equation (2), which yields equation (2a): [0047] Substituting steady-state values of TO _N , TO _FF , and TSW=TO _N +TO _FF in equation (2), the following equation (3) is obtained:

[0048] Equation (3) guaranties unity power factor in a DCM flyback converter in spite of the individually varying TO _N and Tsw- The corresponding effective resistance given by the equation (1) can now be expressed as It is to be noted that, as long as DCM is guaranteed, the high power-factor control law of Equation (2) holds true regardless of a specific moment when a time ΤΟΝ _,Π begins.

[0049] Equation (2) may be solved for ΤΟ _Ν,Π in a predictive way by computing it prior to a conductive state of the switch 102. This can be done by using one of the known iterative root- finding methods, bracketing or open, or by direct calculation of the root, as shown in Equation (4): _l_ . OFF,n-l

¹ ON ~ ^~

T

(4)

[0050] With continued reference to Figure 6, a voltage level 299 designates

VD=VIN+VOR, where VoR=n-ViN, and is the PRI-to-SEC turn ratio of the magnetic element 103. Voltage level 200 designates where k is a constant coefficient less than unity. Waveform 205 represents a time duration ΔΤ within To _FF, n-i where the drain voltage V _D falls below the voltage level 200. The waveform 203 illustrates an exemplary signal at CLK of the control circuit 199 received from the valley detector 101. [0051 ] In operation, the switch 102 turns on once the signal 203 is received at CLK. The switch 102 conducts for a time duration ΤΟ _Ν,Π computed in accordance with the equation (2). Predictive computing of ΤΟ _Ν,Π may require finite time. The control circuit 199 may use the time ΔΤ to perform this computation. In such case, the control circuit 199 may use a modified version of Equation (2), which is shown below in Equation (5): o

(T _C ^ + AT)+ T _C

(5)

[0052] where Tc, _n -i ⁼ To _FF ,n-i-AT is measured instead, and ΔΤ is assumed known.

Alternatively, ΔΤ may be determined from preceding switching cycles.

[0053] Figure 7 illustrates a control method according to an exemplary embodiment of the present disclosure for achieving high power factor in a DCM flyback converter. The method of the exemplary embodiment may include the steps of switching the switch 102 off at step 701. At step 702, it is determined whether the magnetic element is in a discontinuous conduction mode. If not, the method continues checking whether the magnetic element 103 is in a discontinuous conduction mode. Once it is determined that the magnetic element 103 is in a discontinuous conduction mode, at step 703 the method permits the end of the non-conductive state at an arbitrary moment determined by any known criterion. If the end of the non-conductive state has been reached, the method computes the required time duration of a conductive state of the switch 102 using Equation (2). Equation (2) can be solved by using one of the known iterative root-finding methods, bracketing or open, or by direct calculation of the root.

[0054] Figure 8 shows a high power factor flyback converter of Figure 5 that may additionally include an error detector 107 for receiving the output voltage VOU _T and a reference voltage V _REF and for generating a difference voltage V _REF - VOU _T , an integrator 191 for generating a time integral V _ERR of the difference voltage, and wherein the control circuit 199 includes an additional input Vc for receiving V _ERR .

[0055] The control circuit 199 of Figure 8 may use the control law of Equation (5a) below:

T O, N/.

■ a - V E,RR

¹ T OFF,n-l + ^{T 1} T ΟΝ,η

[0056] where a is a constant coefficient. By using the control law of Equation (5a), the control circuit 199 may achieve regulation of the output voltage VOU _T to the reference V _REF - Alternatively, the error detector 107 may receive voltage from a current sense element 194 proportional to measured output current of the flyback converter.

[0057] As opposed to predictively computing ΤΟ _Ν,Π , a real-time solution of Equation (2) is possible. Figure 9 depicts a real-time control method according to an exemplary embodiment of the present disclosure for achieving high power factor in a DCM flyback converter. The method may include the following steps. At step 901, a linear signal ramp V ₁ (t)=a ₁ t may be generated, where ai is a constant coefficient, and 't' is the time variable having its initial value t=0 at a moment of a turn-off transition of the switch 102. At step 902, it is determined whether the magnetic element is in a discontinuous conduction mode. If not, the method generates the linear signal ramp in step 901, and continues checking whether the magnetic element 103 is in a discontinuous conduction mode. Once it is determined that the magnetic element 103 is in a discontinuous conduction mode, at step 903 the method permits the end of the non-conductive state at an arbitrary moment determined by any known criterion. If the duration of the non- conductive state of the switch 102 has reached the end, the switch 102 is turned on at step 904. At step 905, a quadratic signal ramp V ₂ (t) is generated according to the following Equation (6):

V ₂ (t)=a ₂ (t-T ₀ FF) ² (6)

[0058] At step 906, it is determined whether the quadratic signal ramp V ₂ (t) exceeds the linear signal ramp Vi(t). Once it is determined that the quadratic signal ramp V ₂ (t) exceeds the linear signal ramp Vi(t), the switch 102 is turned off at step 907.

[0059] Figure 10 depicts a high power factor flyback converter of Figure 8, wherein the error detector 107 and the integrator 191 may be represented by an analog differential integrator circuit 311, and wherein the control circuit 199 may be an analog circuit including: a flip-flop circuit 313 for turning the controlled switch 102 on and off repeatedly at a high frequency rate, having an output Q, a set input S coupled to the valley detector 101 for activating the output Q, and a reset input R for deactivating the output Q; a controlled ramp generator 309 configured to generate a linear voltage ramp having a slew rate proportional to the output voltage V _ERR of the integrator 311 ; a fixed ramp generator 310 configured to generate a quadratic voltage ramp having a slew rate proportional to the time duration of an active state of the output Q, and for resetting the ramp voltage 310 to its initial level once the output Q becomes inactive; and a comparator 312 that may have a differential pair of inputs for comparing the voltage ramps 309 and 310, and may include an output coupled to the reset input R of the flip-flop 313 for terminating an active state of Q and for resetting ramp voltage 309 to its initial level once ramp voltage 310 exceeds ramp voltage 309.

[0060] Figure 11 illustrates the operation of the exemplary embodiment shown in Figure 10. Referring to Fig. 11, waveform 201 is the drain voltage V _D of the switch 102; waveform 202 is the voltage at the output Q of flip-flop circuit 313; and waveforms 251 and 252 represent the ramp voltages 309 and 310, respectively.

[0061] The ramp 251 begins with the time period ToFF(n-i) preceding each active state of the output Q, whereas the quadratic ramp 252 begins with the active state of the output Q. The active state of the output Q is terminated when the ramp voltage 252 exceeds the ramp voltage 251. The resulting control equation can be written as shown in Equation (7): T ⁺ ) ^ ^

[0062] where oti and a ₂ are constant coefficients. Substituting α=α ₂ /αι in Equation (7) yields Equation (5a).

[0063] Figure 12 depicts a high power factor flyback converter of Figure 10, wherein the controlled ramp generator 309 and the fixed ramp generator 310 have been replaced with a single combined signal generator 315, and wherein the comparator 312 has a differential pair of inputs for comparing an output voltage of the signal generator 315 and an initial voltage level 255. The signal generator 315 may include an output coupled to the non-inverting input of the comparator 312; an input TON coupled to the output Q of flip-flop circuit 313; a reset input coupled to the output of the comparator 312 for resetting the output of the generator 315 to an initial voltage level 255; and an input VERR coupled to the output of the integrator 31 1.

[0064] Figure 13 illustrates the operation of the exemplary embodiment shown in Figure 12. Referring to Fig. 13, waveform 201 is the drain voltage VD of the switch 102; a waveform 202 is the voltage at the output Q of flip-flop circuit 313; waveform 261 represent the output voltage of the generator 315; and a dotted line 265 designates the initial voltage level 255. The waveform 261 is composed as the difference voltage of the waveforms 251 and 252 of Figure 11. [0065] Although the inventive concepts of the present disclosure have been described and illustrated with respect to exemplary embodiments thereof, it is not limited to the exemplary embodiments disclosed herein and modifications may be made therein without departing from the scope of the inventive concepts.