Title:
BUFFER CIRCUIT AND DRIVER CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2005/057229
Kind Code:
A1
Abstract:
A buffer circuit comprises an output circuit that keeps the output impedance constant and that outputs an output signal having an output voltage that is approximately the same as the input voltage of an input signal; first and second transistors that are series connected to respective terminals of the output circuit and that supply, to the respective terminals thereof, voltages in accordance with the magnitude of the input or output voltage so as to reduce the power consumption in the output circuit for protection thereof; a first base voltage control unit that supplies a base voltage to the first transistor to control the first transistor; and a second base voltage control unit that supplies a base voltage to the second transistor to control the second transistor.
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Inventors:
MATSUMOTO NAOKI (JP)
Application Number:
PCT/JP2004/018214
Publication Date:
June 23, 2005
Filing Date:
December 07, 2004
Export Citation:
Assignee:
ADVANTEST CORP (JP)
MATSUMOTO NAOKI (JP)
MATSUMOTO NAOKI (JP)
International Classes:
G01R31/317; G01R31/319; (IPC1-7): G01R31/3181
Foreign References:
| JPH09321607A | 1997-12-12 | |||
| JPH08166429A | 1996-06-25 |
Other References:
See also references of EP 1703291A4
Attorney, Agent or Firm:
Ryuka, Akihiro (22-1 Nishi-Shinjuku 6-chom, Shinjuku-ku Tokyo, JP)
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