Title:
BUFFER, MEMORY DEVICE, AND MEMORY BUS SIGNAL PROCESSING METHOD
Document Type and Number:
WIPO Patent Application WO/2022/057911
Kind Code:
A1
Abstract:
A buffer and a memory device. The buffer is used for connecting to a processor by means of a first memory bus, and for connecting to a memory particle by means of a second memory bus, wherein the first memory bus and the second memory bus comply with different standards. The memory device (200) comprises a buffer (211) and a plurality of memory particles (210). A processor and a memory particle which comply with different memory standards are matched and operate normally, and the performance of a memory device that supports a new standard is realized by using a memory particle that supports an old standard, thereby solving the problem in an initial stage of a memory particle supporting the new standard. For example, a processor that supports a DDR5 standard and a memory particle that supports DDR4 are matched and operate normally, and the performance of a memory device that supports the DDR5 standard is realized, thereby solving the problems of costs being high, the production capacity being low, and the quality being at risk in an initial stage of a DDR5 memory particle.
Inventors:
WU FENG (CN)
Application Number:
PCT/CN2021/119196
Publication Date:
March 24, 2022
Filing Date:
September 18, 2021
Export Citation:
Assignee:
HUAWEI TECH CO LTD (CN)
International Classes:
G06F13/16
Domestic Patent References:
| WO2020172551A1 | 2020-08-27 |
Foreign References:
| CN111045963A | 2020-04-21 | |||
| CN102541772A | 2012-07-04 |
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