BUFFERS WITH REDUCED VOLTAGE INPUT/OUTPUT SIGNALS

Title:

BUFFERS WITH REDUCED VOLTAGE INPUT/OUTPUT SIGNALS

Document Type and Number:

WIPO Patent Application WO2002029972

Kind Code:

A3

Abstract:

A buffer circuit that operates with reduced voltage input and output signals is described. The buffer circuit receives an input signal having reduced voltage range and generates an output signal with the reduced voltage range. The reduced voltage range is form 0 volts to VRED, where VRED is less than VCC, the voltage used to operate most of the logic in the integrated circuit. The use of a buffer circuit that receives and generates signals with a reduced voltage range advantageously reduces power consumption.

Inventors:

MUELLER GERHARD
HANSON DAVID R

Application Number:

PCT/US2001/029192

Publication Date:

July 10, 2003

Filing Date:

September 19, 2001

Export Citation:

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Assignee:

INFINEON TECHNOLOGIES CORP (US)
IBM (US)

International Classes:

H03K19/0185; (IPC1-7): H03K19/0185; H03K19/00

Foreign References:

US5266848A	1993-11-30
US5903142A	1999-05-11
US4920284A	1990-04-24
US6191636B1	2001-02-20

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